Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56384 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2046 |
1 |
|
|
T5 |
8 |
|
T14 |
7 |
|
T16 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57669 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
761 |
1 |
|
|
T42 |
14 |
|
T60 |
13 |
|
T61 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56403 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2027 |
1 |
|
|
T3 |
1 |
|
T5 |
22 |
|
T13 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56418 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2012 |
1 |
|
|
T3 |
1 |
|
T5 |
18 |
|
T13 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56381 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2049 |
1 |
|
|
T3 |
1 |
|
T5 |
14 |
|
T13 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52705 |
1 |
|
|
T2 |
7 |
|
T3 |
10 |
|
T4 |
11 |
no_err_inj |
5725 |
1 |
|
|
T3 |
4 |
|
T5 |
18 |
|
T13 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56354 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2076 |
1 |
|
|
T5 |
4 |
|
T14 |
8 |
|
T16 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57677 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
753 |
1 |
|
|
T42 |
12 |
|
T60 |
12 |
|
T61 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39245 |
1 |
|
|
T4 |
11 |
|
T5 |
141 |
|
T12 |
84 |
auto[1] |
19185 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56293 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2137 |
1 |
|
|
T5 |
26 |
|
T13 |
1 |
|
T14 |
13 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56358 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2072 |
1 |
|
|
T3 |
1 |
|
T5 |
18 |
|
T13 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56321 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2109 |
1 |
|
|
T3 |
1 |
|
T5 |
24 |
|
T14 |
11 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56435 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
1995 |
1 |
|
|
T5 |
10 |
|
T14 |
4 |
|
T16 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55824 |
1 |
|
|
T3 |
14 |
|
T5 |
268 |
|
T12 |
84 |
auto[1] |
2606 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
13 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57723 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
707 |
1 |
|
|
T42 |
18 |
|
T60 |
11 |
|
T61 |
11 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57703 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
727 |
1 |
|
|
T42 |
22 |
|
T60 |
10 |
|
T61 |
7 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57702 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
728 |
1 |
|
|
T42 |
21 |
|
T60 |
12 |
|
T61 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55109 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
269 |
auto[1] |
3321 |
1 |
|
|
T3 |
14 |
|
T5 |
12 |
|
T13 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54589 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
3841 |
1 |
|
|
T12 |
84 |
|
T29 |
61 |
|
T31 |
69 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56394 |
1 |
|
|
T2 |
7 |
|
T3 |
12 |
|
T4 |
11 |
auto[1] |
2036 |
1 |
|
|
T3 |
2 |
|
T5 |
23 |
|
T14 |
12 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56345 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T4 |
11 |
auto[1] |
2085 |
1 |
|
|
T3 |
1 |
|
T5 |
19 |
|
T14 |
7 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56248 |
1 |
|
|
T2 |
7 |
|
T3 |
12 |
|
T4 |
11 |
auto[1] |
2182 |
1 |
|
|
T3 |
2 |
|
T5 |
20 |
|
T13 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56401 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2029 |
1 |
|
|
T5 |
10 |
|
T14 |
10 |
|
T16 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52599 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
5831 |
1 |
|
|
T5 |
6 |
|
T14 |
4 |
|
T16 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54733 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
3697 |
1 |
|
|
T30 |
89 |
|
T58 |
95 |
|
T59 |
75 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58430 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56360 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2070 |
1 |
|
|
T5 |
10 |
|
T14 |
12 |
|
T16 |
5 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56352 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2078 |
1 |
|
|
T5 |
10 |
|
T14 |
8 |
|
T16 |
8 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56379 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
11 |
auto[1] |
2051 |
1 |
|
|
T5 |
8 |
|
T14 |
5 |
|
T16 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
51028 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
259 |
auto[0] |
no_err_inj |
4081 |
1 |
|
|
T5 |
10 |
|
T14 |
17 |
|
T15 |
13 |
auto[1] |
err_inj |
1677 |
1 |
|
|
T3 |
10 |
|
T5 |
4 |
|
T13 |
8 |
auto[1] |
no_err_inj |
1644 |
1 |
|
|
T3 |
4 |
|
T5 |
8 |
|
T13 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53214 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
250 |
auto[0] |
auto[1] |
1895 |
1 |
|
|
T5 |
19 |
|
T14 |
5 |
|
T26 |
9 |
auto[1] |
auto[0] |
3131 |
1 |
|
|
T3 |
13 |
|
T5 |
12 |
|
T13 |
13 |
auto[1] |
auto[1] |
190 |
1 |
|
|
T3 |
1 |
|
T14 |
2 |
|
T17 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53239 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
252 |
auto[0] |
auto[1] |
1870 |
1 |
|
|
T5 |
17 |
|
T14 |
7 |
|
T26 |
11 |
auto[1] |
auto[0] |
3119 |
1 |
|
|
T3 |
13 |
|
T5 |
11 |
|
T13 |
12 |
auto[1] |
auto[1] |
202 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53102 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
249 |
auto[0] |
auto[1] |
2007 |
1 |
|
|
T5 |
20 |
|
T14 |
7 |
|
T26 |
9 |
auto[1] |
auto[0] |
3146 |
1 |
|
|
T3 |
12 |
|
T5 |
12 |
|
T13 |
11 |
auto[1] |
auto[1] |
175 |
1 |
|
|
T3 |
2 |
|
T13 |
2 |
|
T14 |
6 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53279 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
252 |
auto[0] |
auto[1] |
1830 |
1 |
|
|
T5 |
17 |
|
T14 |
14 |
|
T26 |
6 |
auto[1] |
auto[0] |
3139 |
1 |
|
|
T3 |
13 |
|
T5 |
11 |
|
T13 |
12 |
auto[1] |
auto[1] |
182 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53242 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
255 |
auto[0] |
auto[1] |
1867 |
1 |
|
|
T5 |
14 |
|
T14 |
7 |
|
T26 |
8 |
auto[1] |
auto[0] |
3139 |
1 |
|
|
T3 |
13 |
|
T5 |
12 |
|
T13 |
11 |
auto[1] |
auto[1] |
182 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T17 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53254 |
1 |
|
|
T2 |
7 |
|
T4 |
11 |
|
T5 |
247 |
auto[0] |
auto[1] |
1855 |
1 |
|
|
T5 |
22 |
|
T14 |
7 |
|
T26 |
6 |
auto[1] |
auto[0] |
3149 |
1 |
|
|
T3 |
13 |
|
T5 |
12 |
|
T13 |
12 |
auto[1] |
auto[1] |
172 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T18 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38154 |
1 |
|
|
T4 |
11 |
|
T5 |
133 |
|
T12 |
84 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T5 |
8 |
|
T16 |
7 |
|
T18 |
61 |
auto[1] |
auto[0] |
18230 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
955 |
1 |
|
|
T14 |
7 |
|
T18 |
55 |
|
T27 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38061 |
1 |
|
|
T4 |
11 |
|
T5 |
137 |
|
T12 |
84 |
auto[0] |
auto[1] |
1184 |
1 |
|
|
T5 |
4 |
|
T16 |
7 |
|
T18 |
71 |
auto[1] |
auto[0] |
18293 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
892 |
1 |
|
|
T14 |
8 |
|
T18 |
51 |
|
T27 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37861 |
1 |
|
|
T5 |
129 |
|
T12 |
84 |
|
T13 |
13 |
auto[0] |
auto[1] |
1384 |
1 |
|
|
T4 |
11 |
|
T5 |
12 |
|
T14 |
3 |
auto[1] |
auto[0] |
17963 |
1 |
|
|
T3 |
14 |
|
T5 |
139 |
|
T14 |
176 |
auto[1] |
auto[1] |
1222 |
1 |
|
|
T2 |
7 |
|
T5 |
1 |
|
T11 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38198 |
1 |
|
|
T4 |
11 |
|
T5 |
131 |
|
T12 |
84 |
auto[0] |
auto[1] |
1047 |
1 |
|
|
T5 |
10 |
|
T16 |
6 |
|
T18 |
61 |
auto[1] |
auto[0] |
18237 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
948 |
1 |
|
|
T14 |
4 |
|
T18 |
46 |
|
T27 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34354 |
1 |
|
|
T4 |
11 |
|
T5 |
135 |
|
T12 |
84 |
auto[0] |
auto[1] |
4891 |
1 |
|
|
T5 |
6 |
|
T16 |
8 |
|
T18 |
78 |
auto[1] |
auto[0] |
18245 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
940 |
1 |
|
|
T14 |
4 |
|
T18 |
59 |
|
T27 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38029 |
1 |
|
|
T4 |
11 |
|
T5 |
138 |
|
T12 |
84 |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T5 |
3 |
|
T26 |
9 |
|
T18 |
33 |
auto[1] |
auto[0] |
18316 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T5 |
124 |
auto[1] |
auto[1] |
869 |
1 |
|
|
T3 |
1 |
|
T5 |
16 |
|
T14 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38047 |
1 |
|
|
T4 |
11 |
|
T5 |
131 |
|
T12 |
84 |
auto[0] |
auto[1] |
1198 |
1 |
|
|
T5 |
10 |
|
T26 |
11 |
|
T18 |
31 |
auto[1] |
auto[0] |
18347 |
1 |
|
|
T2 |
7 |
|
T3 |
12 |
|
T5 |
127 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T3 |
2 |
|
T5 |
13 |
|
T14 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38037 |
1 |
|
|
T4 |
11 |
|
T5 |
136 |
|
T12 |
84 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T5 |
5 |
|
T13 |
1 |
|
T26 |
11 |
auto[1] |
auto[0] |
18321 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T5 |
127 |
auto[1] |
auto[1] |
864 |
1 |
|
|
T3 |
1 |
|
T5 |
13 |
|
T14 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38023 |
1 |
|
|
T4 |
11 |
|
T5 |
132 |
|
T12 |
84 |
auto[0] |
auto[1] |
1222 |
1 |
|
|
T5 |
9 |
|
T13 |
1 |
|
T26 |
7 |
auto[1] |
auto[0] |
18270 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
123 |
auto[1] |
auto[1] |
915 |
1 |
|
|
T5 |
17 |
|
T14 |
13 |
|
T18 |
46 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38062 |
1 |
|
|
T4 |
11 |
|
T5 |
139 |
|
T12 |
84 |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T5 |
2 |
|
T13 |
1 |
|
T26 |
6 |
auto[1] |
auto[0] |
18356 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T5 |
124 |
auto[1] |
auto[1] |
829 |
1 |
|
|
T3 |
1 |
|
T5 |
16 |
|
T14 |
14 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38083 |
1 |
|
|
T4 |
11 |
|
T5 |
133 |
|
T12 |
84 |
auto[0] |
auto[1] |
1162 |
1 |
|
|
T5 |
8 |
|
T13 |
1 |
|
T26 |
6 |
auto[1] |
auto[0] |
18320 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T5 |
126 |
auto[1] |
auto[1] |
865 |
1 |
|
|
T3 |
1 |
|
T5 |
14 |
|
T14 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38091 |
1 |
|
|
T4 |
11 |
|
T5 |
133 |
|
T12 |
84 |
auto[0] |
auto[1] |
1154 |
1 |
|
|
T5 |
8 |
|
T16 |
4 |
|
T18 |
67 |
auto[1] |
auto[0] |
18288 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
897 |
1 |
|
|
T14 |
5 |
|
T18 |
62 |
|
T27 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38122 |
1 |
|
|
T4 |
11 |
|
T5 |
131 |
|
T12 |
84 |
auto[0] |
auto[1] |
1123 |
1 |
|
|
T5 |
10 |
|
T16 |
8 |
|
T18 |
68 |
auto[1] |
auto[0] |
18230 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T5 |
140 |
auto[1] |
auto[1] |
955 |
1 |
|
|
T14 |
8 |
|
T18 |
65 |
|
T27 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37494 |
1 |
|
|
T4 |
11 |
|
T5 |
141 |
|
T12 |
84 |
auto[0] |
auto[1] |
1751 |
1 |
|
|
T13 |
13 |
|
T18 |
58 |
|
T27 |
14 |
auto[1] |
auto[0] |
17615 |
1 |
|
|
T2 |
7 |
|
T5 |
128 |
|
T11 |
18 |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T3 |
14 |
|
T5 |
12 |
|
T14 |
25 |