Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123869840

1

T1

1773

T2

41041

T3

29889

auto[1]

1490232

1

T2

98

T3

392

T4

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123894094

1

T1

1773

T2

40551

T3

29987

auto[1]

1465978

1

T2

588

T3

294

T4

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8037211	1			T1	113		T2	803		T3	2677
auto[IdleSt]	24222588	1			T1	1660		T2	25047		T3	6526
auto[ClkMuxSt]	38677	1			T2	7		T3	4		T4	11
auto[CntIncrSt]	38340	1			T2	7		T3	4		T4	11
auto[CntProgSt]	1884386	1			T2	100		T3	8		T4	40
auto[TransCheckSt]	29716	1			T3	4		T5	64		T12	68
auto[TokenHashSt]	55640171	1			T3	221		T5	167260		T12	16317
auto[FlashRmaSt]	31184	1			T3	4		T5	62		T12	40
auto[TokenCheck0St]	13991	1			T3	4		T5	30		T12	27
auto[TokenCheck1St]	10487	1			T3	4		T5	27		T12	26
auto[TransProgSt]	491978	1			T3	8		T5	637		T12	37
auto[PostTransSt]	14762966	1			T2	9164		T3	6241		T4	652
auto[ScrapSt]	271276	1			T5	4198		T12	3		T15	621
auto[EscalateSt]	7431857	1			T2	6011		T3	7353		T4	1483
auto[InvalidSt]	12453086	1			T3	7222		T5	198421		T13	454

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2158	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12453086	1			T3	7222		T5	198421		T13	454
EscalateSt	7431857	1			T2	6011		T3	7353		T4	1483
ScrapSt	271276	1			T5	4198		T12	3		T15	621
PostTransSt	14762966	1			T2	9164		T3	6241		T4	652
TransProgSt	491978	1			T3	8		T5	637		T12	37
TokenCheck1St	10487	1			T3	4		T5	27		T12	26
TokenCheck0St	13991	1			T3	4		T5	30		T12	27
FlashRmaSt	31184	1			T3	4		T5	62		T12	40
TokenHashSt	55640171	1			T3	221		T5	167260		T12	16317
TransCheckSt	29716	1			T3	4		T5	64		T12	68
CntProgSt	1884386	1			T2	100		T3	8		T4	40
CntIncrSt	38340	1			T2	7		T3	4		T4	11
ClkMuxSt	38677	1			T2	7		T3	4		T4	11
IdleSt	24222588	1			T1	1660		T2	25047		T3	6526
ResetSt	8037211	1			T1	113		T2	803		T3	2677
arcs[ResetSt=>IdleSt]	58710	1			T1	1		T2	8		T3	14
arcs[IdleSt=>ScrapSt]	321	1			T5	2		T12	1		T15	2
arcs[IdleSt=>ClkMuxSt]	38408	1			T2	7		T3	4		T4	11
arcs[ClkMuxSt=>CntIncrSt]	38340	1			T2	7		T3	4		T4	11
arcs[CntIncrSt=>PostTransSt]	2080	1			T5	10		T14	8		T16	8
arcs[CntIncrSt=>CntProgSt]	36188	1			T2	7		T3	4		T4	11
arcs[CntProgSt=>PostTransSt]	5371	1			T2	7		T4	11		T5	21
arcs[CntProgSt=>TransCheckSt]	29716	1			T3	4		T5	64		T12	68
arcs[TransCheckSt=>PostTransSt]	3914	1			T5	8		T14	5		T16	4
arcs[TransCheckSt=>TokenHashSt]	25650	1			T3	4		T5	56		T12	64
arcs[TokenHashSt=>PostTransSt]	10838	1			T5	26		T14	26		T16	22
arcs[TokenHashSt=>FlashRmaSt]	14091	1			T3	4		T5	30		T12	31
arcs[FlashRmaSt=>TokenCheck0St]	13991	1			T3	4		T5	30		T12	27
arcs[TokenCheck0St=>PostTransSt]	3471	1			T5	3		T14	7		T16	7
arcs[TokenCheck0St=>TokenCheck1St]	10487	1			T3	4		T5	27		T12	26
arcs[TokenCheck1St=>PostTransSt]	665	1			T5	1		T14	1		T18	6
arcs[TransProgSt=>PostTransSt]	8950	1			T3	4		T5	26		T12	15
arcs[IdleSt=>EscalateSt]	161	1			T29	4		T31	10		T51	7
arcs[ClkMuxSt=>EscalateSt]	68	1			T29	3		T31	1		T51	2
arcs[CntIncrSt=>EscalateSt]	72	1			T12	1		T29	1		T31	1
arcs[CntProgSt=>EscalateSt]	1101	1			T12	7		T29	3		T31	14
arcs[TransCheckSt=>EscalateSt]	152	1			T12	4		T29	9		T31	1
arcs[TokenHashSt=>EscalateSt]	721	1			T12	33		T16	1		T18	1
arcs[FlashRmaSt=>EscalateSt]	100	1			T12	4		T29	1		T31	5
arcs[TokenCheck0St=>EscalateSt]	33	1			T12	1		T55	2		T56	1
arcs[TokenCheck1St=>EscalateSt]	141	1			T12	6		T31	4		T51	4
arcs[TransProgSt=>EscalateSt]	731	1			T12	5		T29	14		T31	18
arcs[PostTransSt=>EscalateSt]	5656	1			T2	7		T4	11		T5	21
arcs[InvalidSt=>EscalateSt]	15158	1			T3	7		T5	140		T13	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8037036	1			T1	113		T2	803		T3	2677
auto[0]	auto[IdleSt]	24222475	1			T1	1660		T2	25047		T3	6526
auto[0]	auto[ClkMuxSt]	38637	1			T2	7		T3	4		T4	11
auto[0]	auto[CntIncrSt]	38292	1			T2	7		T3	4		T4	11
auto[0]	auto[CntProgSt]	1883644	1			T2	100		T3	8		T4	40
auto[0]	auto[TransCheckSt]	29605	1			T3	4		T5	64		T12	64
auto[0]	auto[TokenHashSt]	55639709	1			T3	221		T5	167260		T12	16296
auto[0]	auto[FlashRmaSt]	31119	1			T3	4		T5	62		T12	38
auto[0]	auto[TokenCheck0St]	13972	1			T3	4		T5	30		T12	27
auto[0]	auto[TokenCheck1St]	10401	1			T3	4		T5	27		T12	22
auto[0]	auto[TransProgSt]	491497	1			T3	8		T5	637		T12	34
auto[0]	auto[PostTransSt]	14760001	1			T2	9163		T3	6241		T4	646
auto[0]	auto[ScrapSt]	271231	1			T5	4198		T12	2		T15	621
auto[0]	auto[EscalateSt]	5954556	1			T2	5914		T3	6965		T4	895
auto[0]	auto[InvalidSt]	12445507	1			T3	7218		T5	198351		T13	452
auto[1]	auto[ResetSt]	175	1			T12	5		T29	5		T31	4
auto[1]	auto[IdleSt]	113	1			T29	3		T31	9		T51	5
auto[1]	auto[ClkMuxSt]	40	1			T29	1		T31	1		T55	1
auto[1]	auto[CntIncrSt]	48	1			T12	1		T29	1		T31	1
auto[1]	auto[CntProgSt]	742	1			T12	5		T29	3		T31	9
auto[1]	auto[TransCheckSt]	111	1			T12	4		T29	8		T31	1
auto[1]	auto[TokenHashSt]	462	1			T12	21		T18	1		T29	11
auto[1]	auto[FlashRmaSt]	65	1			T12	2		T31	3		T51	4
auto[1]	auto[TokenCheck0St]	19	1			T55	2		T191	1		T192	3
auto[1]	auto[TokenCheck1St]	86	1			T12	4		T31	3		T51	3
auto[1]	auto[TransProgSt]	481	1			T12	3		T29	13		T31	14
auto[1]	auto[PostTransSt]	2965	1			T2	1		T4	6		T5	9
auto[1]	auto[ScrapSt]	45	1			T12	1		T31	1		T51	2
auto[1]	auto[EscalateSt]	1477301	1			T2	97		T3	388		T4	588
auto[1]	auto[InvalidSt]	7579	1			T3	4		T5	70		T13	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8037062	1			T1	113		T2	803		T3	2677
auto[0]	auto[IdleSt]	24222482	1			T1	1660		T2	25047		T3	6526
auto[0]	auto[ClkMuxSt]	38628	1			T2	7		T3	4		T4	11
auto[0]	auto[CntIncrSt]	38291	1			T2	7		T3	4		T4	11
auto[0]	auto[CntProgSt]	1883655	1			T2	100		T3	8		T4	40
auto[0]	auto[TransCheckSt]	29613	1			T3	4		T5	64		T12	67
auto[0]	auto[TokenHashSt]	55639695	1			T3	221		T5	167260		T12	16293
auto[0]	auto[FlashRmaSt]	31121	1			T3	4		T5	62		T12	37
auto[0]	auto[TokenCheck0St]	13967	1			T3	4		T5	30		T12	26
auto[0]	auto[TokenCheck1St]	10390	1			T3	4		T5	27		T12	21
auto[0]	auto[TransProgSt]	491494	1			T3	8		T5	637		T12	34
auto[0]	auto[PostTransSt]	14760193	1			T2	9158		T3	6241		T4	647
auto[0]	auto[ScrapSt]	271229	1			T5	4198		T12	2		T15	621
auto[0]	auto[EscalateSt]	5978609	1			T2	5429		T3	7062		T4	993
auto[0]	auto[InvalidSt]	12445507	1			T3	7219		T5	198351		T13	450
auto[1]	auto[ResetSt]	149	1			T12	5		T29	6		T31	4
auto[1]	auto[IdleSt]	106	1			T29	3		T31	6		T51	5
auto[1]	auto[ClkMuxSt]	49	1			T29	3		T31	1		T51	2
auto[1]	auto[CntIncrSt]	49	1			T12	1		T29	1		T51	1
auto[1]	auto[CntProgSt]	731	1			T12	3		T29	2		T31	10
auto[1]	auto[TransCheckSt]	103	1			T12	1		T29	8		T31	1
auto[1]	auto[TokenHashSt]	476	1			T12	24		T16	1		T29	9
auto[1]	auto[FlashRmaSt]	63	1			T12	3		T29	1		T31	4
auto[1]	auto[TokenCheck0St]	24	1			T12	1		T55	2		T56	1
auto[1]	auto[TokenCheck1St]	97	1			T12	5		T31	1		T51	3
auto[1]	auto[TransProgSt]	484	1			T12	3		T29	5		T31	11
auto[1]	auto[PostTransSt]	2773	1			T2	6		T4	5		T5	12
auto[1]	auto[ScrapSt]	47	1			T12	1		T31	1		T51	2
auto[1]	auto[EscalateSt]	1453248	1			T2	582		T3	291		T4	490
auto[1]	auto[InvalidSt]	7579	1			T3	3		T5	70		T13	4