Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1537837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1755706

1

T1

182

T2

164

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2958568	1			T1	255		T2	156		T3	51
values[0x0]	166988	1			T1	112		T2	60		T3	26
values[0x1]	167987	1			T1	141		T2	57		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1221033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2072510

1

T1

224

T2

181

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8867	1			T1	5		T2	1		T4	9
valid_sources[0x01]	9464	1			T1	2		T4	4		T11	1
valid_sources[0x02]	8697	1			T1	1		T2	1		T4	11
valid_sources[0x03]	8890	1			T1	3		T2	1		T4	21
valid_sources[0x04]	8913	1			T1	1		T10	12		T11	2
valid_sources[0x05]	9154	1			T4	12		T10	8		T11	3
valid_sources[0x06]	11245	1			T1	3		T4	5		T10	6
valid_sources[0x07]	8730	1			T1	3		T4	2		T10	2
valid_sources[0x08]	13523	1			T1	3		T4	2		T11	7
valid_sources[0x09]	8665	1			T10	3		T11	5		T12	7
valid_sources[0x0a]	9043	1			T1	1		T2	2		T4	4
valid_sources[0x0b]	10328	1			T1	1		T2	3		T4	27
valid_sources[0x0c]	8778	1			T2	1		T4	9		T11	2
valid_sources[0x0d]	10832	1			T1	1		T2	5		T4	25
valid_sources[0x0e]	8909	1			T1	5		T10	3		T11	3
valid_sources[0x0f]	8883	1			T1	2		T4	17		T10	9
valid_sources[0x10]	78616	1			T2	1		T4	1		T10	4
valid_sources[0x11]	9338	1			T1	3		T2	3		T4	7
valid_sources[0x12]	9359	1			T1	3		T4	9		T10	3
valid_sources[0x13]	9120	1			T1	3		T2	1		T4	5
valid_sources[0x14]	10821	1			T1	3		T4	16		T10	3
valid_sources[0x15]	11285	1			T2	2		T4	1		T10	14
valid_sources[0x16]	8779	1			T1	1		T4	22		T10	8
valid_sources[0x17]	9313	1			T1	3		T2	2		T12	4
valid_sources[0x18]	10378	1			T1	1		T4	8		T10	10
valid_sources[0x19]	9929	1			T1	1		T10	3		T11	4
valid_sources[0x1a]	9339	1			T1	4		T4	26		T10	4
valid_sources[0x1b]	11762	1			T1	4		T4	6		T11	2
valid_sources[0x1c]	8756	1			T1	4		T2	2		T4	6
valid_sources[0x1d]	9048	1			T1	1		T2	1		T4	1
valid_sources[0x1e]	8831	1			T1	1		T2	3		T4	5
valid_sources[0x1f]	9242	1			T2	1		T4	9		T11	1
valid_sources[0x20]	8361	1			T1	1		T4	2		T10	6
valid_sources[0x21]	9689	1			T1	2		T4	22		T12	2
valid_sources[0x22]	24742	1			T1	1		T4	9		T10	19
valid_sources[0x23]	26011	1			T1	3		T2	2		T4	7
valid_sources[0x24]	34338	1			T4	18		T10	4		T11	7
valid_sources[0x25]	8935	1			T1	1		T4	31		T10	11
valid_sources[0x26]	9151	1			T1	4		T2	3		T4	1
valid_sources[0x27]	9889	1			T4	7		T10	12		T11	4
valid_sources[0x28]	9992	1			T2	5		T4	14		T10	7
valid_sources[0x29]	9566	1			T1	2		T2	4		T4	10
valid_sources[0x2a]	8689	1			T1	5		T2	1		T4	7
valid_sources[0x2b]	8910	1			T2	2		T10	11		T11	2
valid_sources[0x2c]	10175	1			T1	1		T4	6		T11	3
valid_sources[0x2d]	9353	1			T2	4		T3	84		T10	2
valid_sources[0x2e]	12200	1			T2	1		T4	3		T10	3
valid_sources[0x2f]	9180	1			T1	2		T4	14		T10	7
valid_sources[0x30]	10239	1			T1	2		T2	2		T4	8
valid_sources[0x31]	10426	1			T1	5		T4	16		T10	15
valid_sources[0x32]	9079	1			T1	3		T10	17		T11	2
valid_sources[0x33]	9011	1			T1	1		T2	2		T4	6
valid_sources[0x34]	8839	1			T1	1		T2	2		T4	17
valid_sources[0x35]	9325	1			T1	1		T4	8		T11	6
valid_sources[0x36]	9231	1			T1	2		T2	2		T4	13
valid_sources[0x37]	8923	1			T1	1		T2	1		T4	9
valid_sources[0x38]	8838	1			T1	4		T4	4		T11	5
valid_sources[0x39]	10476	1			T1	3		T2	2		T4	12
valid_sources[0x3a]	9020	1			T1	3		T4	1		T10	8
valid_sources[0x3b]	9054	1			T4	3		T11	2		T12	4
valid_sources[0x3c]	8818	1			T1	2		T2	1		T4	3
valid_sources[0x3d]	9479	1			T10	6		T11	4		T12	4
valid_sources[0x3e]	9022	1			T2	1		T4	9		T10	8
valid_sources[0x3f]	8630	1			T1	2		T2	2		T4	7
valid_sources[0x40]	8934	1			T1	2		T2	3		T4	24
valid_sources[0x41]	10021	1			T1	1		T2	2		T4	3
valid_sources[0x42]	8810	1			T1	7		T2	1		T4	8
valid_sources[0x43]	9003	1			T1	1		T2	2		T4	3
valid_sources[0x44]	11242	1			T1	4		T2	1		T10	6
valid_sources[0x45]	8996	1			T1	1		T2	1		T4	5
valid_sources[0x46]	9136	1			T1	9		T2	1		T4	4
valid_sources[0x47]	9361	1			T1	5		T4	1		T11	2
valid_sources[0x48]	9207	1			T11	5		T12	4		T15	5
valid_sources[0x49]	10430	1			T1	4		T2	6		T4	5
valid_sources[0x4a]	11113	1			T1	2		T4	30		T10	10
valid_sources[0x4b]	131276	1			T1	1		T2	1		T4	3
valid_sources[0x4c]	9155	1			T2	1		T4	12		T10	3
valid_sources[0x4d]	8676	1			T1	2		T2	1		T4	11
valid_sources[0x4e]	10580	1			T1	3		T10	1		T11	3
valid_sources[0x4f]	10207	1			T1	2		T2	1		T4	9
valid_sources[0x50]	9018	1			T1	1		T2	1		T4	14
valid_sources[0x51]	9037	1			T1	1		T2	2		T4	17
valid_sources[0x52]	8806	1			T1	1		T2	2		T4	12
valid_sources[0x53]	12964	1			T1	2		T4	7		T10	1
valid_sources[0x54]	12054	1			T2	2		T4	3		T10	1
valid_sources[0x55]	9207	1			T1	2		T2	1		T3	14
valid_sources[0x56]	8895	1			T4	10		T10	6		T11	2
valid_sources[0x57]	9192	1			T1	3		T4	16		T10	5
valid_sources[0x58]	9480	1			T1	4		T2	2		T4	22
valid_sources[0x59]	8974	1			T1	2		T2	1		T4	13
valid_sources[0x5a]	9204	1			T2	1		T4	20		T11	4
valid_sources[0x5b]	8624	1			T1	6		T4	16		T11	5
valid_sources[0x5c]	9814	1			T4	8		T11	10		T12	5
valid_sources[0x5d]	8895	1			T1	5		T2	1		T4	11
valid_sources[0x5e]	8696	1			T2	1		T4	21		T10	5
valid_sources[0x5f]	8760	1			T1	2		T4	11		T10	1
valid_sources[0x60]	9311	1			T1	7		T2	3		T4	17
valid_sources[0x61]	8556	1			T1	2		T4	15		T10	3
valid_sources[0x62]	8845	1			T1	2		T2	1		T4	11
valid_sources[0x63]	9708	1			T1	3		T2	2		T4	11
valid_sources[0x64]	9134	1			T1	1		T4	4		T10	5
valid_sources[0x65]	9316	1			T1	7		T4	4		T10	18
valid_sources[0x66]	8494	1			T1	2		T4	8		T10	3
valid_sources[0x67]	8708	1			T4	2		T10	12		T11	1
valid_sources[0x68]	9730	1			T1	1		T2	1		T4	5
valid_sources[0x69]	8758	1			T1	1		T2	1		T4	6
valid_sources[0x6a]	9034	1			T1	2		T2	1		T4	15
valid_sources[0x6b]	8688	1			T1	1		T4	5		T10	1
valid_sources[0x6c]	8583	1			T2	1		T4	5		T10	5
valid_sources[0x6d]	9038	1			T1	1		T4	6		T10	4
valid_sources[0x6e]	15030	1			T1	2		T2	4		T4	15
valid_sources[0x6f]	9085	1			T1	5		T4	3		T10	8
valid_sources[0x70]	9241	1			T1	1		T2	1		T4	3
valid_sources[0x71]	12522	1			T1	3		T2	2		T4	4
valid_sources[0x72]	9837	1			T3	1		T4	11		T10	16
valid_sources[0x73]	9260	1			T1	2		T4	15		T10	7
valid_sources[0x74]	9087	1			T1	2		T2	3		T4	1
valid_sources[0x75]	10619	1			T2	1		T4	8		T10	7
valid_sources[0x76]	9410	1			T1	3		T4	21		T11	1
valid_sources[0x77]	9331	1			T2	1		T4	8		T10	1
valid_sources[0x78]	8810	1			T1	5		T2	2		T10	11
valid_sources[0x79]	10401	1			T1	2		T10	4		T11	3
valid_sources[0x7a]	8874	1			T1	2		T4	32		T10	2
valid_sources[0x7b]	10382	1			T1	3		T4	22		T10	9
valid_sources[0x7c]	69330	1			T1	2		T2	3		T4	8
valid_sources[0x7d]	10438	1			T1	1		T4	24		T10	5
valid_sources[0x7e]	9289	1			T1	1		T2	2		T4	14
valid_sources[0x7f]	9569	1			T2	1		T4	8		T10	10
valid_sources[0x80]	8928	1			T4	19		T10	10		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1466675

1

T1

121

T2

62

T3

27

values[0x0]

all_enables

biggest_size

144849

1

T1

36

T2

52

T3

10

values[0x1]

all_enables

biggest_size

144182

1

T1

25

T2

50

T3

8