Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	97082776	14201	0	0
claim_transition_if_regwen_rd_A	97082776	1875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97082776	14201	0	0
T35	1418	0	0	0
T38	370757	0	0	0
T39	330163	0	0	0
T40	0	9	0	0
T49	0	3	0	0
T54	39769	0	0	0
T62	292270	7	0	0
T84	1521	0	0	0
T85	1378	0	0	0
T96	0	2	0	0
T99	0	1	0	0
T134	0	3	0	0
T135	0	6	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	30472	0	0	0
T140	215571	0	0	0
T141	55145	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97082776	1875	0	0
T103	0	24	0	0
T119	0	48	0	0
T121	0	66	0	0
T136	122596	4	0	0
T142	0	14	0	0
T143	0	10	0	0
T144	0	27	0	0
T145	0	8	0	0
T146	0	4	0	0
T147	0	5	0	0
T148	1403	0	0	0
T149	1772	0	0	0
T150	35796	0	0	0
T151	1370	0	0	0
T152	33516	0	0	0
T153	42132	0	0	0
T154	313024	0	0	0
T155	438660	0	0	0
T156	27826	0	0	0