Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1487803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1702571

1

T1

269

T3

10

T4

733

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2857897	1			T1	315		T4	800		T11	29
values[0x0]	166035	1			T1	79		T3	26		T4	192
values[0x1]	166442	1			T1	77		T3	31		T4	216

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1180864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2009510

1

T1

318

T3

14

T4

837

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9259	1			T1	1		T4	5		T21	127
valid_sources[0x01]	14357	1			T4	5		T14	15		T46	3
valid_sources[0x02]	9635	1			T1	2		T4	7		T14	2
valid_sources[0x03]	10955	1			T1	1		T4	2		T21	114
valid_sources[0x04]	8666	1			T1	4		T4	3		T45	1
valid_sources[0x05]	10841	1			T1	3		T4	6		T14	25
valid_sources[0x06]	107456	1			T1	1		T4	10		T14	5
valid_sources[0x07]	10015	1			T1	1		T4	4		T13	1
valid_sources[0x08]	8848	1			T1	6		T4	12		T45	1
valid_sources[0x09]	47249	1			T1	3		T4	3		T15	20
valid_sources[0x0a]	9101	1			T1	1		T4	7		T11	6
valid_sources[0x0b]	9992	1			T1	1		T4	6		T14	6
valid_sources[0x0c]	9391	1			T4	4		T13	2		T21	104
valid_sources[0x0d]	9777	1			T1	3		T4	7		T11	7
valid_sources[0x0e]	9682	1			T1	2		T4	5		T46	5
valid_sources[0x0f]	9195	1			T1	4		T4	4		T7	1
valid_sources[0x10]	9400	1			T1	1		T4	6		T14	10
valid_sources[0x11]	9686	1			T4	4		T14	1		T46	5
valid_sources[0x12]	9372	1			T1	1		T4	8		T14	7
valid_sources[0x13]	9658	1			T1	4		T4	5		T14	1
valid_sources[0x14]	9474	1			T1	4		T4	5		T46	2
valid_sources[0x15]	9493	1			T4	4		T14	10		T46	9
valid_sources[0x16]	9206	1			T1	3		T4	2		T13	2
valid_sources[0x17]	10118	1			T1	6		T4	8		T11	1
valid_sources[0x18]	11544	1			T1	2		T4	1		T13	2
valid_sources[0x19]	9513	1			T1	2		T4	5		T21	95
valid_sources[0x1a]	9576	1			T1	6		T4	7		T11	2
valid_sources[0x1b]	9596	1			T4	3		T14	3		T46	8
valid_sources[0x1c]	11059	1			T4	6		T13	3		T45	1
valid_sources[0x1d]	10910	1			T1	1		T4	10		T14	11
valid_sources[0x1e]	10770	1			T1	1		T4	3		T14	8
valid_sources[0x1f]	28135	1			T1	3		T4	3		T13	2
valid_sources[0x20]	9656	1			T4	6		T14	9		T15	43
valid_sources[0x21]	17104	1			T4	2		T17	2		T21	122
valid_sources[0x22]	12988	1			T1	5		T4	4		T14	2
valid_sources[0x23]	31858	1			T4	2		T14	6		T17	4
valid_sources[0x24]	8871	1			T4	5		T46	8		T7	1
valid_sources[0x25]	12338	1			T1	6		T4	9		T46	8
valid_sources[0x26]	15173	1			T1	1		T4	6		T46	1
valid_sources[0x27]	10188	1			T1	2		T4	3		T45	1
valid_sources[0x28]	9264	1			T1	3		T4	3		T14	10
valid_sources[0x29]	28795	1			T1	6		T4	1		T14	2
valid_sources[0x2a]	9174	1			T1	1		T4	3		T13	1
valid_sources[0x2b]	9758	1			T4	1		T14	5		T21	113
valid_sources[0x2c]	11639	1			T4	2		T14	1		T46	4
valid_sources[0x2d]	9347	1			T1	1		T4	6		T15	52
valid_sources[0x2e]	9181	1			T1	3		T4	4		T21	122
valid_sources[0x2f]	23443	1			T4	4		T20	14078		T21	90
valid_sources[0x30]	9374	1			T4	9		T17	4		T46	1
valid_sources[0x31]	11870	1			T1	8		T4	2		T13	1
valid_sources[0x32]	8888	1			T4	3		T14	1		T21	107
valid_sources[0x33]	9313	1			T1	1		T4	4		T18	8
valid_sources[0x34]	13550	1			T1	2		T4	2		T13	1
valid_sources[0x35]	11649	1			T1	2		T4	7		T13	1
valid_sources[0x36]	67665	1			T4	5		T11	3		T14	4
valid_sources[0x37]	11050	1			T1	6		T4	5		T18	8
valid_sources[0x38]	11254	1			T1	2		T4	7		T14	1
valid_sources[0x39]	9742	1			T1	3		T4	9		T14	2
valid_sources[0x3a]	10617	1			T1	1		T4	4		T17	3
valid_sources[0x3b]	43098	1			T1	2		T4	5		T21	94
valid_sources[0x3c]	13625	1			T1	1		T4	11		T14	4
valid_sources[0x3d]	9241	1			T1	1		T4	7		T14	10
valid_sources[0x3e]	9790	1			T1	3		T4	4		T46	1
valid_sources[0x3f]	8971	1			T1	3		T4	5		T14	3
valid_sources[0x40]	8942	1			T1	3		T4	7		T14	2
valid_sources[0x41]	9952	1			T4	2		T46	1		T21	66
valid_sources[0x42]	9334	1			T1	1		T4	3		T13	2
valid_sources[0x43]	9659	1			T4	2		T21	92		T44	2
valid_sources[0x44]	9756	1			T4	2		T14	6		T21	80
valid_sources[0x45]	9225	1			T1	4		T4	5		T45	1
valid_sources[0x46]	9523	1			T1	3		T4	7		T14	1
valid_sources[0x47]	9327	1			T4	4		T14	8		T18	49
valid_sources[0x48]	10265	1			T4	3		T14	11		T17	4
valid_sources[0x49]	9065	1			T1	4		T4	1		T14	9
valid_sources[0x4a]	10727	1			T1	2		T4	1		T14	2
valid_sources[0x4b]	11130	1			T1	4		T4	1		T15	2
valid_sources[0x4c]	10986	1			T1	1		T4	2		T46	9
valid_sources[0x4d]	9505	1			T4	6		T14	8		T18	105
valid_sources[0x4e]	9390	1			T4	7		T14	1		T46	4
valid_sources[0x4f]	15912	1			T4	3		T15	7		T18	46
valid_sources[0x50]	10518	1			T4	1		T11	2		T14	4
valid_sources[0x51]	9319	1			T1	1		T4	8		T14	1
valid_sources[0x52]	9005	1			T1	2		T4	3		T14	6
valid_sources[0x53]	9313	1			T1	1		T4	6		T17	1
valid_sources[0x54]	10454	1			T1	2		T4	3		T14	10
valid_sources[0x55]	9139	1			T1	1		T4	4		T13	3
valid_sources[0x56]	9388	1			T4	6		T11	2		T13	1
valid_sources[0x57]	9044	1			T1	2		T4	8		T14	2
valid_sources[0x58]	9795	1			T1	1		T4	5		T14	4
valid_sources[0x59]	9625	1			T1	1		T4	7		T18	76
valid_sources[0x5a]	15060	1			T1	3		T4	4		T14	4
valid_sources[0x5b]	10676	1			T4	7		T17	2		T46	1
valid_sources[0x5c]	9423	1			T1	2		T4	3		T46	5
valid_sources[0x5d]	11285	1			T1	1		T4	5		T15	17
valid_sources[0x5e]	8752	1			T1	1		T4	4		T14	3
valid_sources[0x5f]	9451	1			T1	2		T4	5		T46	4
valid_sources[0x60]	38514	1			T1	4		T4	3		T14	8
valid_sources[0x61]	9037	1			T4	6		T14	3		T20	7
valid_sources[0x62]	10879	1			T1	4		T4	7		T46	3
valid_sources[0x63]	12898	1			T1	1		T4	4		T14	2
valid_sources[0x64]	8909	1			T4	8		T21	101		T44	13
valid_sources[0x65]	9387	1			T1	2		T4	5		T13	1
valid_sources[0x66]	9476	1			T1	2		T4	3		T13	1
valid_sources[0x67]	10079	1			T1	1		T4	2		T14	7
valid_sources[0x68]	10247	1			T1	2		T4	8		T14	1
valid_sources[0x69]	9332	1			T4	10		T14	27		T46	5
valid_sources[0x6a]	9736	1			T4	4		T14	5		T21	100
valid_sources[0x6b]	9710	1			T1	2		T4	12		T14	3
valid_sources[0x6c]	9102	1			T4	5		T45	2		T21	98
valid_sources[0x6d]	9538	1			T1	1		T4	2		T13	4
valid_sources[0x6e]	9486	1			T1	1		T4	4		T21	125
valid_sources[0x6f]	9185	1			T1	3		T4	2		T14	8
valid_sources[0x70]	9203	1			T1	1		T14	12		T18	6
valid_sources[0x71]	9565	1			T1	1		T4	5		T45	1
valid_sources[0x72]	9358	1			T14	4		T18	1		T46	4
valid_sources[0x73]	9280	1			T1	1		T4	5		T45	1
valid_sources[0x74]	9802	1			T4	5		T46	6		T21	104
valid_sources[0x75]	9505	1			T1	8		T4	9		T18	2
valid_sources[0x76]	12085	1			T4	2		T14	3		T46	5
valid_sources[0x77]	9890	1			T1	3		T4	3		T14	4
valid_sources[0x78]	9311	1			T1	2		T4	4		T13	2
valid_sources[0x79]	10992	1			T1	1		T4	8		T18	11
valid_sources[0x7a]	9318	1			T1	3		T4	4		T14	1
valid_sources[0x7b]	10885	1			T1	3		T4	10		T14	1
valid_sources[0x7c]	9575	1			T1	8		T4	1		T14	7
valid_sources[0x7d]	10065	1			T1	4		T4	3		T11	1
valid_sources[0x7e]	9611	1			T1	2		T4	7		T14	11
valid_sources[0x7f]	20181	1			T4	5		T14	6		T17	1
valid_sources[0x80]	10119	1			T1	4		T4	2		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1416092

1

T1

135

T4

377

T11

1

values[0x0]

all_enables

biggest_size

144111

1

T1

67

T3

5

T4

164

values[0x1]

all_enables

biggest_size

142368

1

T1

67

T3

5

T4

192