Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95861829	15770	0	0
claim_transition_if_regwen_rd_A	95861829	1335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95861829	15770	0	0
T20	288611	12	0	0
T21	688906	0	0	0
T22	35148	0	0	0
T44	41471	0	0	0
T52	32786	0	0	0
T54	0	13	0	0
T57	42883	0	0	0
T58	36274	0	0	0
T67	1175	0	0	0
T90	0	8	0	0
T91	0	7	0	0
T92	52728	0	0	0
T93	4176	0	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	7	0	0
T138	0	1	0	0
T139	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95861829	1335	0	0
T56	0	9	0	0
T101	0	9	0	0
T104	0	23	0	0
T106	0	16	0	0
T140	120450	7	0	0
T141	0	261	0	0
T142	0	6	0	0
T143	0	63	0	0
T144	0	21	0	0
T145	0	15	0	0
T146	18355	0	0	0
T147	33799	0	0	0
T148	38128	0	0	0
T149	25978	0	0	0
T150	37298	0	0	0
T151	1589	0	0	0
T152	2810	0	0	0
T153	30431	0	0	0
T154	35128	0	0	0