Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49874 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
89 |
auto[1] |
1759 |
1 |
|
|
T4 |
10 |
|
T25 |
9 |
|
T19 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50905 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
728 |
1 |
|
|
T17 |
13 |
|
T38 |
16 |
|
T53 |
21 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49921 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1712 |
1 |
|
|
T1 |
8 |
|
T5 |
1 |
|
T26 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49922 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1711 |
1 |
|
|
T1 |
8 |
|
T18 |
2 |
|
T36 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49916 |
1 |
|
|
T1 |
71 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1717 |
1 |
|
|
T1 |
6 |
|
T26 |
1 |
|
T92 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46950 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
no_err_inj |
4683 |
1 |
|
|
T5 |
8 |
|
T23 |
8 |
|
T26 |
3 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49824 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
89 |
auto[1] |
1809 |
1 |
|
|
T4 |
10 |
|
T25 |
6 |
|
T19 |
23 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50845 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
788 |
1 |
|
|
T17 |
23 |
|
T38 |
18 |
|
T53 |
22 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36332 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
15301 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49896 |
1 |
|
|
T1 |
66 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1737 |
1 |
|
|
T1 |
11 |
|
T5 |
1 |
|
T23 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49877 |
1 |
|
|
T1 |
65 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1756 |
1 |
|
|
T1 |
12 |
|
T23 |
1 |
|
T19 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49874 |
1 |
|
|
T1 |
70 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1759 |
1 |
|
|
T1 |
7 |
|
T23 |
1 |
|
T26 |
2 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49846 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
86 |
auto[1] |
1787 |
1 |
|
|
T4 |
13 |
|
T25 |
15 |
|
T19 |
28 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49530 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
2103 |
1 |
|
|
T13 |
9 |
|
T16 |
8 |
|
T24 |
13 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50890 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
743 |
1 |
|
|
T17 |
15 |
|
T38 |
15 |
|
T53 |
16 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50869 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
764 |
1 |
|
|
T17 |
20 |
|
T38 |
11 |
|
T53 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50907 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
726 |
1 |
|
|
T17 |
22 |
|
T38 |
9 |
|
T53 |
6 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49051 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
2582 |
1 |
|
|
T5 |
15 |
|
T23 |
11 |
|
T26 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47858 |
1 |
|
|
T1 |
77 |
|
T4 |
99 |
|
T11 |
90 |
auto[1] |
3775 |
1 |
|
|
T2 |
72 |
|
T14 |
74 |
|
T35 |
84 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49880 |
1 |
|
|
T1 |
71 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1753 |
1 |
|
|
T1 |
6 |
|
T5 |
2 |
|
T26 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49917 |
1 |
|
|
T1 |
66 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1716 |
1 |
|
|
T1 |
11 |
|
T5 |
2 |
|
T18 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49889 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
1744 |
1 |
|
|
T1 |
8 |
|
T5 |
1 |
|
T26 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49845 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
88 |
auto[1] |
1788 |
1 |
|
|
T4 |
11 |
|
T25 |
11 |
|
T19 |
21 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46003 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
85 |
auto[1] |
5630 |
1 |
|
|
T4 |
14 |
|
T12 |
52 |
|
T25 |
14 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48051 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[1] |
3582 |
1 |
|
|
T11 |
90 |
|
T68 |
81 |
|
T69 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51633 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49898 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
85 |
auto[1] |
1735 |
1 |
|
|
T4 |
14 |
|
T25 |
9 |
|
T19 |
29 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49821 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
88 |
auto[1] |
1812 |
1 |
|
|
T4 |
11 |
|
T25 |
7 |
|
T19 |
20 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49817 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
83 |
auto[1] |
1816 |
1 |
|
|
T4 |
16 |
|
T25 |
8 |
|
T19 |
25 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45653 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
no_err_inj |
3398 |
1 |
|
|
T19 |
6 |
|
T20 |
1 |
|
T46 |
8 |
auto[1] |
err_inj |
1297 |
1 |
|
|
T5 |
7 |
|
T23 |
3 |
|
T26 |
7 |
auto[1] |
no_err_inj |
1285 |
1 |
|
|
T5 |
8 |
|
T23 |
8 |
|
T26 |
3 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47473 |
1 |
|
|
T1 |
66 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1578 |
1 |
|
|
T1 |
11 |
|
T20 |
24 |
|
T21 |
20 |
auto[1] |
auto[0] |
2444 |
1 |
|
|
T5 |
13 |
|
T23 |
11 |
|
T26 |
10 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T5 |
2 |
|
T18 |
1 |
|
T92 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47428 |
1 |
|
|
T1 |
65 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T1 |
12 |
|
T20 |
13 |
|
T21 |
15 |
auto[1] |
auto[0] |
2449 |
1 |
|
|
T5 |
15 |
|
T23 |
10 |
|
T26 |
10 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T23 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47450 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1601 |
1 |
|
|
T1 |
8 |
|
T20 |
17 |
|
T21 |
13 |
auto[1] |
auto[0] |
2439 |
1 |
|
|
T5 |
14 |
|
T23 |
11 |
|
T26 |
8 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T5 |
1 |
|
T26 |
2 |
|
T36 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47478 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1573 |
1 |
|
|
T1 |
8 |
|
T20 |
18 |
|
T21 |
14 |
auto[1] |
auto[0] |
2444 |
1 |
|
|
T5 |
15 |
|
T23 |
11 |
|
T26 |
10 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T18 |
2 |
|
T36 |
1 |
|
T20 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47488 |
1 |
|
|
T1 |
71 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T1 |
6 |
|
T20 |
21 |
|
T21 |
13 |
auto[1] |
auto[0] |
2428 |
1 |
|
|
T5 |
15 |
|
T23 |
11 |
|
T26 |
9 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T26 |
1 |
|
T92 |
1 |
|
T21 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47488 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T1 |
8 |
|
T20 |
15 |
|
T21 |
17 |
auto[1] |
auto[0] |
2433 |
1 |
|
|
T5 |
14 |
|
T23 |
11 |
|
T26 |
9 |
auto[1] |
auto[1] |
149 |
1 |
|
|
T5 |
1 |
|
T26 |
1 |
|
T36 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35231 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
89 |
auto[0] |
auto[1] |
1101 |
1 |
|
|
T4 |
10 |
|
T25 |
9 |
|
T19 |
10 |
auto[1] |
auto[0] |
14643 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
658 |
1 |
|
|
T19 |
4 |
|
T50 |
8 |
|
T72 |
16 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35201 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
89 |
auto[0] |
auto[1] |
1131 |
1 |
|
|
T4 |
10 |
|
T25 |
6 |
|
T19 |
13 |
auto[1] |
auto[0] |
14623 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
678 |
1 |
|
|
T19 |
10 |
|
T50 |
6 |
|
T72 |
14 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35124 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T13 |
9 |
|
T16 |
8 |
|
T24 |
13 |
auto[1] |
auto[0] |
14406 |
1 |
|
|
T5 |
15 |
|
T18 |
12 |
|
T19 |
105 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T7 |
18 |
|
T19 |
9 |
|
T20 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35228 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
86 |
auto[0] |
auto[1] |
1104 |
1 |
|
|
T4 |
13 |
|
T25 |
15 |
|
T19 |
15 |
auto[1] |
auto[0] |
14618 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
683 |
1 |
|
|
T19 |
13 |
|
T50 |
5 |
|
T72 |
17 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31402 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
85 |
auto[0] |
auto[1] |
4930 |
1 |
|
|
T4 |
14 |
|
T12 |
52 |
|
T25 |
14 |
auto[1] |
auto[0] |
14601 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
700 |
1 |
|
|
T19 |
13 |
|
T50 |
10 |
|
T72 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35390 |
1 |
|
|
T1 |
66 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
942 |
1 |
|
|
T1 |
11 |
|
T92 |
1 |
|
T20 |
24 |
auto[1] |
auto[0] |
14527 |
1 |
|
|
T5 |
13 |
|
T7 |
18 |
|
T18 |
11 |
auto[1] |
auto[1] |
774 |
1 |
|
|
T5 |
2 |
|
T18 |
1 |
|
T20 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35394 |
1 |
|
|
T1 |
71 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
938 |
1 |
|
|
T1 |
6 |
|
T26 |
1 |
|
T92 |
1 |
auto[1] |
auto[0] |
14486 |
1 |
|
|
T5 |
13 |
|
T7 |
18 |
|
T18 |
10 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T5 |
2 |
|
T18 |
2 |
|
T19 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35367 |
1 |
|
|
T1 |
65 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
965 |
1 |
|
|
T1 |
12 |
|
T23 |
1 |
|
T20 |
13 |
auto[1] |
auto[0] |
14510 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
791 |
1 |
|
|
T19 |
1 |
|
T20 |
1 |
|
T21 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35382 |
1 |
|
|
T1 |
66 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
950 |
1 |
|
|
T1 |
11 |
|
T23 |
1 |
|
T36 |
1 |
auto[1] |
auto[0] |
14514 |
1 |
|
|
T5 |
14 |
|
T7 |
18 |
|
T18 |
11 |
auto[1] |
auto[1] |
787 |
1 |
|
|
T5 |
1 |
|
T18 |
1 |
|
T21 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35418 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
914 |
1 |
|
|
T1 |
8 |
|
T36 |
1 |
|
T20 |
18 |
auto[1] |
auto[0] |
14504 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
10 |
auto[1] |
auto[1] |
797 |
1 |
|
|
T18 |
2 |
|
T20 |
1 |
|
T21 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35387 |
1 |
|
|
T1 |
69 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
945 |
1 |
|
|
T1 |
8 |
|
T26 |
1 |
|
T36 |
1 |
auto[1] |
auto[0] |
14534 |
1 |
|
|
T5 |
14 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T5 |
1 |
|
T20 |
1 |
|
T21 |
3 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35217 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
83 |
auto[0] |
auto[1] |
1115 |
1 |
|
|
T4 |
16 |
|
T25 |
8 |
|
T19 |
13 |
auto[1] |
auto[0] |
14600 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
701 |
1 |
|
|
T19 |
12 |
|
T50 |
13 |
|
T72 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35209 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
88 |
auto[0] |
auto[1] |
1123 |
1 |
|
|
T4 |
11 |
|
T25 |
7 |
|
T19 |
11 |
auto[1] |
auto[0] |
14612 |
1 |
|
|
T5 |
15 |
|
T7 |
18 |
|
T18 |
12 |
auto[1] |
auto[1] |
689 |
1 |
|
|
T19 |
9 |
|
T50 |
12 |
|
T72 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34897 |
1 |
|
|
T1 |
77 |
|
T2 |
72 |
|
T4 |
99 |
auto[0] |
auto[1] |
1435 |
1 |
|
|
T23 |
11 |
|
T26 |
10 |
|
T36 |
11 |
auto[1] |
auto[0] |
14154 |
1 |
|
|
T7 |
18 |
|
T19 |
102 |
|
T20 |
21 |
auto[1] |
auto[1] |
1147 |
1 |
|
|
T5 |
15 |
|
T18 |
12 |
|
T19 |
12 |