Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96719812

1

T1

26329

T2

25112

T3

1246

auto[1]

1335533

1

T1

3168

T2

9004

T4

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96698597

1

T1

26527

T2

24346

T3

1246

auto[1]

1356748

1

T1

2970

T2

9770

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6917531	1			T1	8433		T2	6646		T3	141
auto[IdleSt]	19521277	1			T1	1255		T2	5421		T3	209
auto[ClkMuxSt]	34859	1			T2	61		T4	99		T11	90
auto[CntIncrSt]	34553	1			T2	59		T4	99		T11	90
auto[CntProgSt]	1859648	1			T2	4563		T4	1035		T11	180
auto[TransCheckSt]	27027	1			T2	35		T4	78		T11	90
auto[TokenHashSt]	39701999	1			T2	3135		T4	1920		T11	15734
auto[FlashRmaSt]	28046	1			T2	73		T4	60		T11	112
auto[TokenCheck0St]	12449	1			T2	26		T4	23		T11	38
auto[TokenCheck1St]	9133	1			T2	25		T4	14		T11	15
auto[TransProgSt]	551446	1			T2	88		T4	181		T14	139
auto[PostTransSt]	11899067	1			T2	3		T3	896		T4	16402
auto[ScrapSt]	205195	1			T14	6		T19	1943		T46	38
auto[EscalateSt]	6404864	1			T1	8790		T2	13981		T4	1440
auto[InvalidSt]	10846423	1			T1	11007		T17	2867		T5	13379

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1828	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10846423	1			T1	11007		T17	2867		T5	13379
EscalateSt	6404864	1			T1	8790		T2	13981		T4	1440
ScrapSt	205195	1			T14	6		T19	1943		T46	38
PostTransSt	11899067	1			T2	3		T3	896		T4	16402
TransProgSt	551446	1			T2	88		T4	181		T14	139
TokenCheck1St	9133	1			T2	25		T4	14		T11	15
TokenCheck0St	12449	1			T2	26		T4	23		T11	38
FlashRmaSt	28046	1			T2	73		T4	60		T11	112
TokenHashSt	39701999	1			T2	3135		T4	1920		T11	15734
TransCheckSt	27027	1			T2	35		T4	78		T11	90
CntProgSt	1859648	1			T2	4563		T4	1035		T11	180
CntIncrSt	34553	1			T2	59		T4	99		T11	90
ClkMuxSt	34859	1			T2	61		T4	99		T11	90
IdleSt	19521277	1			T1	1255		T2	5421		T3	209
ResetSt	6917531	1			T1	8433		T2	6646		T3	141
arcs[ResetSt=>IdleSt]	51963	1			T1	71		T2	66		T3	1
arcs[IdleSt=>ScrapSt]	291	1			T14	2		T19	2		T46	1
arcs[IdleSt=>ClkMuxSt]	34617	1			T2	61		T4	99		T11	90
arcs[ClkMuxSt=>CntIncrSt]	34553	1			T2	59		T4	99		T11	90
arcs[CntIncrSt=>PostTransSt]	1812	1			T4	11		T25	7		T19	20
arcs[CntIncrSt=>CntProgSt]	32678	1			T2	59		T4	88		T11	90
arcs[CntProgSt=>PostTransSt]	4551	1			T4	10		T13	9		T16	8
arcs[CntProgSt=>TransCheckSt]	27027	1			T2	35		T4	78		T11	90
arcs[TransCheckSt=>PostTransSt]	3592	1			T4	16		T11	40		T25	8
arcs[TransCheckSt=>TokenHashSt]	23322	1			T2	35		T4	62		T11	50
arcs[TokenHashSt=>PostTransSt]	10128	1			T4	39		T11	12		T12	52
arcs[TokenHashSt=>FlashRmaSt]	12549	1			T2	29		T4	23		T11	38
arcs[FlashRmaSt=>TokenCheck0St]	12449	1			T2	26		T4	23		T11	38
arcs[TokenCheck0St=>PostTransSt]	3287	1			T4	9		T11	23		T17	20
arcs[TokenCheck0St=>TokenCheck1St]	9133	1			T2	25		T4	14		T11	15
arcs[TokenCheck1St=>PostTransSt]	617	1			T4	1		T11	15		T17	2
arcs[TransProgSt=>PostTransSt]	7601	1			T2	1		T4	13		T14	1
arcs[IdleSt=>EscalateSt]	247	1			T2	4		T14	14		T35	7
arcs[ClkMuxSt=>EscalateSt]	64	1			T2	2		T14	2		T57	3
arcs[CntIncrSt=>EscalateSt]	63	1			T14	3		T42	1		T57	1
arcs[CntProgSt=>EscalateSt]	1100	1			T2	24		T14	17		T35	27
arcs[TransCheckSt=>EscalateSt]	113	1			T35	2		T58	5		T42	3
arcs[TokenHashSt=>EscalateSt]	643	1			T2	6		T14	7		T35	9
arcs[FlashRmaSt=>EscalateSt]	100	1			T2	3		T14	2		T35	1
arcs[TokenCheck0St=>EscalateSt]	29	1			T2	1		T62	1		T63	1
arcs[TokenCheck1St=>EscalateSt]	155	1			T2	3		T14	4		T35	2
arcs[TransProgSt=>EscalateSt]	760	1			T2	21		T14	18		T35	27
arcs[PostTransSt=>EscalateSt]	4794	1			T2	1		T4	10		T13	9
arcs[InvalidSt=>EscalateSt]	12882	1			T1	62		T17	20		T5	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6917366	1			T1	8433		T2	6642		T3	141
auto[0]	auto[IdleSt]	19521118	1			T1	1255		T2	5418		T3	209
auto[0]	auto[ClkMuxSt]	34818	1			T2	60		T4	99		T11	90
auto[0]	auto[CntIncrSt]	34512	1			T2	59		T4	99		T11	90
auto[0]	auto[CntProgSt]	1858910	1			T2	4548		T4	1035		T11	180
auto[0]	auto[TransCheckSt]	26946	1			T2	35		T4	78		T11	90
auto[0]	auto[TokenHashSt]	39701578	1			T2	3131		T4	1920		T11	15734
auto[0]	auto[FlashRmaSt]	27974	1			T2	71		T4	60		T11	112
auto[0]	auto[TokenCheck0St]	12433	1			T2	26		T4	23		T11	38
auto[0]	auto[TokenCheck1St]	9044	1			T2	23		T4	14		T11	15
auto[0]	auto[TransProgSt]	550963	1			T2	74		T4	181		T14	129
auto[0]	auto[PostTransSt]	11896650	1			T2	2		T3	896		T4	16396
auto[0]	auto[ScrapSt]	205160	1			T14	4		T19	1943		T46	38
auto[0]	auto[EscalateSt]	5080471	1			T1	5654		T2	5023		T4	852
auto[0]	auto[InvalidSt]	10840041	1			T1	10975		T17	2861		T5	13376
auto[1]	auto[ResetSt]	165	1			T2	4		T14	2		T35	5
auto[1]	auto[IdleSt]	159	1			T2	3		T14	10		T35	6
auto[1]	auto[ClkMuxSt]	41	1			T2	1		T14	2		T57	3
auto[1]	auto[CntIncrSt]	41	1			T14	1		T42	1		T63	1
auto[1]	auto[CntProgSt]	738	1			T2	15		T14	14		T35	21
auto[1]	auto[TransCheckSt]	81	1			T35	1		T58	3		T42	3
auto[1]	auto[TokenHashSt]	421	1			T2	4		T14	3		T35	5
auto[1]	auto[FlashRmaSt]	72	1			T2	2		T14	2		T57	2
auto[1]	auto[TokenCheck0St]	16	1			T62	1		T63	1		T213	1
auto[1]	auto[TokenCheck1St]	89	1			T2	2		T14	2		T35	1
auto[1]	auto[TransProgSt]	483	1			T2	14		T14	10		T35	19
auto[1]	auto[PostTransSt]	2417	1			T2	1		T4	6		T13	4
auto[1]	auto[ScrapSt]	35	1			T14	2		T58	1		T42	1
auto[1]	auto[EscalateSt]	1324393	1			T1	3136		T2	8958		T4	588
auto[1]	auto[InvalidSt]	6382	1			T1	32		T17	6		T5	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6917378	1			T1	8433		T2	6642		T3	141
auto[0]	auto[IdleSt]	19521108	1			T1	1255		T2	5420		T3	209
auto[0]	auto[ClkMuxSt]	34813	1			T2	59		T4	99		T11	90
auto[0]	auto[CntIncrSt]	34516	1			T2	59		T4	99		T11	90
auto[0]	auto[CntProgSt]	1858919	1			T2	4542		T4	1035		T11	180
auto[0]	auto[TransCheckSt]	26955	1			T2	35		T4	78		T11	90
auto[0]	auto[TokenHashSt]	39701562	1			T2	3131		T4	1920		T11	15734
auto[0]	auto[FlashRmaSt]	27979	1			T2	72		T4	60		T11	112
auto[0]	auto[TokenCheck0St]	12430	1			T2	25		T4	23		T11	38
auto[0]	auto[TokenCheck1St]	9013	1			T2	23		T4	14		T11	15
auto[0]	auto[TransProgSt]	550936	1			T2	75		T4	181		T14	123
auto[0]	auto[PostTransSt]	11896608	1			T2	2		T3	896		T4	16398
auto[0]	auto[ScrapSt]	205146	1			T14	5		T19	1943		T46	38
auto[0]	auto[EscalateSt]	5059483	1			T1	5850		T2	4261		T4	1048
auto[0]	auto[InvalidSt]	10839923	1			T1	10977		T17	2853		T5	13376
auto[1]	auto[ResetSt]	153	1			T2	4		T14	3		T35	1
auto[1]	auto[IdleSt]	169	1			T2	1		T14	8		T35	6
auto[1]	auto[ClkMuxSt]	46	1			T2	2		T14	1		T57	2
auto[1]	auto[CntIncrSt]	37	1			T14	2		T42	1		T57	1
auto[1]	auto[CntProgSt]	729	1			T2	21		T14	11		T35	17
auto[1]	auto[TransCheckSt]	72	1			T35	1		T58	4		T42	2
auto[1]	auto[TokenHashSt]	437	1			T2	4		T14	5		T35	7
auto[1]	auto[FlashRmaSt]	67	1			T2	1		T14	2		T35	1
auto[1]	auto[TokenCheck0St]	19	1			T2	1		T62	1		T213	1
auto[1]	auto[TokenCheck1St]	120	1			T2	2		T14	4		T35	2
auto[1]	auto[TransProgSt]	510	1			T2	13		T14	16		T35	16
auto[1]	auto[PostTransSt]	2459	1			T2	1		T4	4		T13	5
auto[1]	auto[ScrapSt]	49	1			T14	1		T58	1		T42	1
auto[1]	auto[EscalateSt]	1345381	1			T1	2940		T2	9720		T4	392
auto[1]	auto[InvalidSt]	6500	1			T1	30		T17	14		T5	3