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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 97.89 95.50 93.31 100.00 98.55 98.51 96.64


Total test records in report: 997
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T810 /workspace/coverage/default/10.lc_ctrl_prog_failure.138726009 May 28 02:49:32 PM PDT 24 May 28 02:49:40 PM PDT 24 59080487 ps
T61 /workspace/coverage/default/3.lc_ctrl_sec_cm.4001258765 May 28 02:49:06 PM PDT 24 May 28 02:49:54 PM PDT 24 834391305 ps
T811 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1341179300 May 28 02:49:39 PM PDT 24 May 28 02:49:50 PM PDT 24 1031762981 ps
T812 /workspace/coverage/default/27.lc_ctrl_alert_test.2603507924 May 28 02:50:30 PM PDT 24 May 28 02:50:38 PM PDT 24 62317544 ps
T813 /workspace/coverage/default/2.lc_ctrl_jtag_errors.1909057837 May 28 02:49:05 PM PDT 24 May 28 02:49:48 PM PDT 24 1891351402 ps
T814 /workspace/coverage/default/8.lc_ctrl_stress_all.1092447950 May 28 02:49:32 PM PDT 24 May 28 02:52:40 PM PDT 24 17762752035 ps
T815 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2150934810 May 28 02:49:46 PM PDT 24 May 28 02:50:04 PM PDT 24 346416557 ps
T816 /workspace/coverage/default/44.lc_ctrl_state_failure.425170996 May 28 02:51:00 PM PDT 24 May 28 02:51:45 PM PDT 24 2303652503 ps
T817 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1202002399 May 28 02:50:18 PM PDT 24 May 28 02:50:37 PM PDT 24 368858017 ps
T818 /workspace/coverage/default/5.lc_ctrl_jtag_access.3343832550 May 28 02:49:21 PM PDT 24 May 28 02:49:29 PM PDT 24 1093448889 ps
T819 /workspace/coverage/default/7.lc_ctrl_prog_failure.3657458994 May 28 02:49:25 PM PDT 24 May 28 02:49:34 PM PDT 24 649059629 ps
T820 /workspace/coverage/default/19.lc_ctrl_stress_all.2455569012 May 28 02:50:18 PM PDT 24 May 28 02:51:15 PM PDT 24 3328175054 ps
T821 /workspace/coverage/default/47.lc_ctrl_state_failure.3821908756 May 28 02:51:18 PM PDT 24 May 28 02:52:00 PM PDT 24 271031705 ps
T822 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4033912140 May 28 02:50:59 PM PDT 24 May 28 02:51:18 PM PDT 24 16081974 ps
T823 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3434537398 May 28 02:50:17 PM PDT 24 May 28 02:50:30 PM PDT 24 882688355 ps
T824 /workspace/coverage/default/21.lc_ctrl_stress_all.3126875136 May 28 02:50:17 PM PDT 24 May 28 02:53:49 PM PDT 24 6119185169 ps
T825 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1985917026 May 28 02:49:43 PM PDT 24 May 28 02:50:00 PM PDT 24 1176855913 ps
T826 /workspace/coverage/default/7.lc_ctrl_security_escalation.320554579 May 28 02:49:18 PM PDT 24 May 28 02:49:33 PM PDT 24 1245760475 ps
T827 /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2713823502 May 28 02:49:27 PM PDT 24 May 28 03:04:19 PM PDT 24 221405794483 ps
T111 /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4248929823 May 28 02:49:22 PM PDT 24 May 28 02:55:09 PM PDT 24 89391645970 ps
T828 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.838396599 May 28 02:49:53 PM PDT 24 May 28 02:50:00 PM PDT 24 809584603 ps
T829 /workspace/coverage/default/15.lc_ctrl_jtag_errors.1947663959 May 28 02:49:44 PM PDT 24 May 28 02:50:20 PM PDT 24 6383123690 ps
T830 /workspace/coverage/default/2.lc_ctrl_smoke.3784244978 May 28 02:49:06 PM PDT 24 May 28 02:49:18 PM PDT 24 92065029 ps
T831 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1418390886 May 28 02:50:10 PM PDT 24 May 28 02:50:23 PM PDT 24 1063244175 ps
T832 /workspace/coverage/default/10.lc_ctrl_state_failure.957616690 May 28 02:49:31 PM PDT 24 May 28 02:50:03 PM PDT 24 499368334 ps
T833 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1448369300 May 28 02:49:58 PM PDT 24 May 28 02:50:13 PM PDT 24 1126232688 ps
T834 /workspace/coverage/default/41.lc_ctrl_stress_all.2434761542 May 28 02:50:54 PM PDT 24 May 28 02:52:41 PM PDT 24 2623758775 ps
T835 /workspace/coverage/default/49.lc_ctrl_alert_test.3774122661 May 28 02:51:26 PM PDT 24 May 28 02:51:48 PM PDT 24 15969882 ps
T82 /workspace/coverage/default/35.lc_ctrl_alert_test.4020420791 May 28 02:50:53 PM PDT 24 May 28 02:51:09 PM PDT 24 28891130 ps
T836 /workspace/coverage/default/24.lc_ctrl_errors.4231961879 May 28 02:50:22 PM PDT 24 May 28 02:50:39 PM PDT 24 388218461 ps
T837 /workspace/coverage/default/12.lc_ctrl_smoke.2444293726 May 28 02:49:41 PM PDT 24 May 28 02:49:50 PM PDT 24 564149281 ps
T838 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3423899736 May 28 02:50:39 PM PDT 24 May 28 02:50:56 PM PDT 24 307661306 ps
T839 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3415994338 May 28 02:49:09 PM PDT 24 May 28 02:49:41 PM PDT 24 3826733488 ps
T840 /workspace/coverage/default/17.lc_ctrl_state_failure.3343452475 May 28 02:49:57 PM PDT 24 May 28 02:50:26 PM PDT 24 1363277859 ps
T841 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2719089551 May 28 02:51:06 PM PDT 24 May 28 02:51:37 PM PDT 24 1693930828 ps
T842 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.276351744 May 28 02:49:01 PM PDT 24 May 28 02:49:27 PM PDT 24 395583612 ps
T843 /workspace/coverage/default/4.lc_ctrl_alert_test.2301494071 May 28 02:49:08 PM PDT 24 May 28 02:49:17 PM PDT 24 67495643 ps
T844 /workspace/coverage/default/1.lc_ctrl_sec_mubi.2456804729 May 28 02:49:06 PM PDT 24 May 28 02:49:25 PM PDT 24 1503243435 ps
T845 /workspace/coverage/default/34.lc_ctrl_security_escalation.3219364496 May 28 02:50:51 PM PDT 24 May 28 02:51:11 PM PDT 24 455664217 ps
T846 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2338713547 May 28 02:50:16 PM PDT 24 May 28 02:50:23 PM PDT 24 24961928 ps
T847 /workspace/coverage/default/29.lc_ctrl_sec_mubi.2265049101 May 28 02:50:37 PM PDT 24 May 28 02:50:58 PM PDT 24 500228739 ps
T848 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.926781262 May 28 02:50:51 PM PDT 24 May 28 02:51:18 PM PDT 24 724223154 ps
T849 /workspace/coverage/default/15.lc_ctrl_jtag_access.2255287043 May 28 02:49:46 PM PDT 24 May 28 02:49:59 PM PDT 24 1555198219 ps
T850 /workspace/coverage/default/15.lc_ctrl_sec_mubi.1030348374 May 28 02:50:14 PM PDT 24 May 28 02:50:29 PM PDT 24 1627947418 ps
T851 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1368742833 May 28 02:49:05 PM PDT 24 May 28 02:49:26 PM PDT 24 194526654 ps
T852 /workspace/coverage/default/11.lc_ctrl_state_post_trans.3187199666 May 28 02:49:36 PM PDT 24 May 28 02:49:46 PM PDT 24 192761672 ps
T853 /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3327780358 May 28 02:50:17 PM PDT 24 May 28 03:13:16 PM PDT 24 147602476760 ps
T854 /workspace/coverage/default/42.lc_ctrl_alert_test.282157391 May 28 02:51:02 PM PDT 24 May 28 02:51:23 PM PDT 24 73516872 ps
T855 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.181484552 May 28 02:49:36 PM PDT 24 May 28 02:49:58 PM PDT 24 321715477 ps
T856 /workspace/coverage/default/40.lc_ctrl_smoke.1738389203 May 28 02:50:54 PM PDT 24 May 28 02:51:12 PM PDT 24 198559313 ps
T857 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.514436545 May 28 02:50:38 PM PDT 24 May 28 02:50:46 PM PDT 24 12429264 ps
T858 /workspace/coverage/default/32.lc_ctrl_state_failure.3651338758 May 28 02:50:40 PM PDT 24 May 28 02:51:20 PM PDT 24 272395761 ps
T859 /workspace/coverage/default/16.lc_ctrl_jtag_access.179600158 May 28 02:49:52 PM PDT 24 May 28 02:50:05 PM PDT 24 329547572 ps
T860 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.564934207 May 28 02:49:21 PM PDT 24 May 28 02:49:42 PM PDT 24 469790601 ps
T861 /workspace/coverage/default/26.lc_ctrl_stress_all.886301152 May 28 02:50:26 PM PDT 24 May 28 02:53:36 PM PDT 24 16904043524 ps
T862 /workspace/coverage/default/0.lc_ctrl_jtag_priority.2853612745 May 28 02:48:55 PM PDT 24 May 28 02:49:06 PM PDT 24 147398449 ps
T863 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3810858492 May 28 02:49:47 PM PDT 24 May 28 02:50:01 PM PDT 24 1172210424 ps
T864 /workspace/coverage/default/0.lc_ctrl_jtag_errors.3944404544 May 28 02:48:57 PM PDT 24 May 28 02:50:27 PM PDT 24 2839510609 ps
T865 /workspace/coverage/default/48.lc_ctrl_sec_mubi.1341491668 May 28 02:51:28 PM PDT 24 May 28 02:52:02 PM PDT 24 1104225299 ps
T866 /workspace/coverage/default/9.lc_ctrl_state_failure.2110224030 May 28 02:49:32 PM PDT 24 May 28 02:50:06 PM PDT 24 823460840 ps
T867 /workspace/coverage/default/21.lc_ctrl_sec_mubi.778717768 May 28 02:50:15 PM PDT 24 May 28 02:50:31 PM PDT 24 1673900065 ps
T868 /workspace/coverage/default/42.lc_ctrl_smoke.4135899842 May 28 02:51:05 PM PDT 24 May 28 02:51:27 PM PDT 24 62056182 ps
T112 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3212398125 May 28 01:42:33 PM PDT 24 May 28 01:42:37 PM PDT 24 206670926 ps
T115 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4007711659 May 28 01:43:17 PM PDT 24 May 28 01:43:20 PM PDT 24 25580335 ps
T145 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2293148948 May 28 01:46:08 PM PDT 24 May 28 01:46:26 PM PDT 24 335730690 ps
T122 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2047532418 May 28 01:43:02 PM PDT 24 May 28 01:43:04 PM PDT 24 16536038 ps
T123 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.988941445 May 28 01:42:26 PM PDT 24 May 28 01:42:33 PM PDT 24 1133900557 ps
T139 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.700501465 May 28 01:42:31 PM PDT 24 May 28 01:42:33 PM PDT 24 120833548 ps
T113 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2864441730 May 28 01:42:33 PM PDT 24 May 28 01:42:36 PM PDT 24 99842477 ps
T869 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1917008045 May 28 01:42:33 PM PDT 24 May 28 01:42:36 PM PDT 24 79447645 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2544670635 May 28 01:46:16 PM PDT 24 May 28 01:46:40 PM PDT 24 2310018699 ps
T114 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.524828709 May 28 01:43:06 PM PDT 24 May 28 01:43:14 PM PDT 24 120779353 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3125990741 May 28 01:46:01 PM PDT 24 May 28 01:46:08 PM PDT 24 68252334 ps
T118 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3726538990 May 28 01:46:09 PM PDT 24 May 28 01:46:31 PM PDT 24 32523902 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.918042781 May 28 01:42:31 PM PDT 24 May 28 01:42:33 PM PDT 24 37379673 ps
T871 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1135403898 May 28 01:42:30 PM PDT 24 May 28 01:42:32 PM PDT 24 32825969 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2633012786 May 28 01:42:44 PM PDT 24 May 28 01:42:46 PM PDT 24 90973222 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.313297866 May 28 01:42:33 PM PDT 24 May 28 01:42:35 PM PDT 24 12778747 ps
T201 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1704152196 May 28 01:46:12 PM PDT 24 May 28 01:46:32 PM PDT 24 19392429 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2577425449 May 28 01:43:17 PM PDT 24 May 28 01:43:20 PM PDT 24 52159559 ps
T117 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2781421089 May 28 01:43:05 PM PDT 24 May 28 01:43:13 PM PDT 24 366405431 ps
T162 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.692811348 May 28 01:43:20 PM PDT 24 May 28 01:43:23 PM PDT 24 15147257 ps
T202 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.936289338 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 247794452 ps
T203 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1727768572 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 38662008 ps
T190 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2673112138 May 28 01:42:35 PM PDT 24 May 28 01:42:37 PM PDT 24 41478215 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1611558053 May 28 01:46:09 PM PDT 24 May 28 01:46:29 PM PDT 24 133286187 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2757510953 May 28 01:44:02 PM PDT 24 May 28 01:44:04 PM PDT 24 20432172 ps
T204 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3204676361 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 21111586 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2990181933 May 28 01:46:04 PM PDT 24 May 28 01:46:16 PM PDT 24 39391311 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1408445774 May 28 01:43:04 PM PDT 24 May 28 01:43:06 PM PDT 24 141942354 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2637478442 May 28 01:46:12 PM PDT 24 May 28 01:46:37 PM PDT 24 584426013 ps
T134 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3496374171 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 152466989 ps
T133 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.449880879 May 28 01:46:09 PM PDT 24 May 28 01:46:32 PM PDT 24 618954885 ps
T124 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1374752055 May 28 01:46:13 PM PDT 24 May 28 01:46:37 PM PDT 24 78816031 ps
T141 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.319345989 May 28 01:42:31 PM PDT 24 May 28 01:42:33 PM PDT 24 247090458 ps
T876 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.664060075 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 16294611 ps
T119 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3400794932 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 174324875 ps
T206 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.98016390 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 53132306 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.788421109 May 28 01:42:32 PM PDT 24 May 28 01:42:36 PM PDT 24 170822263 ps
T877 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3379583878 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 113478040 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3311570998 May 28 01:42:32 PM PDT 24 May 28 01:42:35 PM PDT 24 90018846 ps
T879 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.115902601 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 1129311524 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.818336268 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 49510389 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3614801704 May 28 01:42:48 PM PDT 24 May 28 01:42:50 PM PDT 24 104549436 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.758243507 May 28 01:42:20 PM PDT 24 May 28 01:42:45 PM PDT 24 876636565 ps
T882 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2231509997 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 28217663 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2517932902 May 28 01:46:10 PM PDT 24 May 28 01:46:32 PM PDT 24 510076017 ps
T163 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1690408644 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 188094659 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.445035437 May 28 01:42:34 PM PDT 24 May 28 01:42:38 PM PDT 24 19957572 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2772045726 May 28 01:43:05 PM PDT 24 May 28 01:43:19 PM PDT 24 2398327718 ps
T886 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3995859755 May 28 01:43:18 PM PDT 24 May 28 01:43:21 PM PDT 24 24954337 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1566727993 May 28 01:43:56 PM PDT 24 May 28 01:44:14 PM PDT 24 1342560034 ps
T164 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.765940403 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 17511714 ps
T165 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.923965740 May 28 01:43:08 PM PDT 24 May 28 01:43:18 PM PDT 24 136993784 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.542688165 May 28 01:42:25 PM PDT 24 May 28 01:42:31 PM PDT 24 369494158 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4186591369 May 28 01:42:20 PM PDT 24 May 28 01:42:28 PM PDT 24 259052491 ps
T890 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2665393274 May 28 01:43:07 PM PDT 24 May 28 01:43:12 PM PDT 24 39472576 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.202893436 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 56188332 ps
T892 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1316549999 May 28 01:43:06 PM PDT 24 May 28 01:43:11 PM PDT 24 80363351 ps
T121 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2370388334 May 28 01:43:28 PM PDT 24 May 28 01:43:33 PM PDT 24 185664139 ps
T893 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2414572450 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 42027576 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3543163921 May 28 01:46:12 PM PDT 24 May 28 01:46:33 PM PDT 24 33183678 ps
T138 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.844420116 May 28 01:42:45 PM PDT 24 May 28 01:42:48 PM PDT 24 89889934 ps
T166 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3238389959 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 37094246 ps
T895 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4206910999 May 28 01:42:31 PM PDT 24 May 28 01:42:34 PM PDT 24 367520120 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3249867485 May 28 01:42:34 PM PDT 24 May 28 01:42:37 PM PDT 24 16435589 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1438002046 May 28 01:42:35 PM PDT 24 May 28 01:42:40 PM PDT 24 291709442 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3644739204 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 33014963 ps
T899 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1718838317 May 28 01:46:10 PM PDT 24 May 28 01:46:29 PM PDT 24 11953189 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3894944032 May 28 01:42:31 PM PDT 24 May 28 01:42:38 PM PDT 24 696355916 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4260819128 May 28 01:42:31 PM PDT 24 May 28 01:42:33 PM PDT 24 37376837 ps
T135 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.343688049 May 28 01:43:06 PM PDT 24 May 28 01:43:14 PM PDT 24 263079151 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1064920894 May 28 01:43:04 PM PDT 24 May 28 01:43:06 PM PDT 24 50482975 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4289991259 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 29549257 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1078411752 May 28 01:45:17 PM PDT 24 May 28 01:45:37 PM PDT 24 8651036292 ps
T905 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3431286295 May 28 01:43:08 PM PDT 24 May 28 01:43:14 PM PDT 24 56747616 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3680788050 May 28 01:43:04 PM PDT 24 May 28 01:43:07 PM PDT 24 106860356 ps
T907 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2757308642 May 28 01:43:08 PM PDT 24 May 28 01:43:15 PM PDT 24 81405416 ps
T908 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4093692776 May 28 01:43:08 PM PDT 24 May 28 01:43:14 PM PDT 24 39645605 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1568090408 May 28 01:43:05 PM PDT 24 May 28 01:43:12 PM PDT 24 58131086 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3017522856 May 28 01:42:32 PM PDT 24 May 28 01:42:35 PM PDT 24 89350301 ps
T911 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.292056854 May 28 01:43:05 PM PDT 24 May 28 01:43:12 PM PDT 24 279366555 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2066748931 May 28 01:46:00 PM PDT 24 May 28 01:46:04 PM PDT 24 28301983 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.609307779 May 28 01:44:00 PM PDT 24 May 28 01:44:02 PM PDT 24 151454463 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3587206686 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 36302948 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3834838088 May 28 01:43:05 PM PDT 24 May 28 01:43:16 PM PDT 24 256924576 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.39334255 May 28 01:42:34 PM PDT 24 May 28 01:42:37 PM PDT 24 30236451 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4195765857 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 72403338 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1078867475 May 28 01:42:48 PM PDT 24 May 28 01:42:50 PM PDT 24 16540079 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.295151987 May 28 01:43:06 PM PDT 24 May 28 01:43:13 PM PDT 24 113317032 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3075912739 May 28 01:42:36 PM PDT 24 May 28 01:42:47 PM PDT 24 810463000 ps
T919 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.794382606 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 111728325 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2619436189 May 28 01:44:02 PM PDT 24 May 28 01:44:04 PM PDT 24 203771259 ps
T921 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2733023863 May 28 01:43:06 PM PDT 24 May 28 01:43:40 PM PDT 24 2678992136 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2697386848 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 41899266 ps
T137 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4129753058 May 28 01:43:07 PM PDT 24 May 28 01:43:15 PM PDT 24 138288123 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3676135954 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 49603719 ps
T924 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1784875769 May 28 01:43:02 PM PDT 24 May 28 01:43:04 PM PDT 24 32584587 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3564273996 May 28 01:43:03 PM PDT 24 May 28 01:43:07 PM PDT 24 335398525 ps
T192 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1588592 May 28 01:44:00 PM PDT 24 May 28 01:44:02 PM PDT 24 19596169 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2095957863 May 28 01:42:34 PM PDT 24 May 28 01:42:37 PM PDT 24 42304379 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3027265992 May 28 01:46:04 PM PDT 24 May 28 01:46:14 PM PDT 24 98335270 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.343346015 May 28 01:43:07 PM PDT 24 May 28 01:43:15 PM PDT 24 359007352 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.684397142 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 77400567 ps
T930 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3323884034 May 28 01:43:16 PM PDT 24 May 28 01:43:18 PM PDT 24 68973465 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3056091937 May 28 01:42:31 PM PDT 24 May 28 01:42:36 PM PDT 24 538310163 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2094989468 May 28 01:44:00 PM PDT 24 May 28 01:44:04 PM PDT 24 369223985 ps
T933 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2182659807 May 28 01:43:04 PM PDT 24 May 28 01:43:06 PM PDT 24 93450906 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1656406294 May 28 01:42:33 PM PDT 24 May 28 01:42:36 PM PDT 24 287209047 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1739772956 May 28 01:42:32 PM PDT 24 May 28 01:42:35 PM PDT 24 54608292 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.77757275 May 28 01:46:12 PM PDT 24 May 28 01:46:32 PM PDT 24 23662182 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.37303190 May 28 01:42:34 PM PDT 24 May 28 01:42:37 PM PDT 24 29685451 ps
T136 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3300824921 May 28 01:43:07 PM PDT 24 May 28 01:43:15 PM PDT 24 1236746014 ps
T938 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3592748035 May 28 01:43:06 PM PDT 24 May 28 01:43:11 PM PDT 24 50134754 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143859428 May 28 01:43:05 PM PDT 24 May 28 01:43:12 PM PDT 24 260226133 ps
T940 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3848377489 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 39616951 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3856578575 May 28 01:42:33 PM PDT 24 May 28 01:42:36 PM PDT 24 128683574 ps
T942 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1521305792 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 48993577 ps
T943 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.688451374 May 28 01:43:07 PM PDT 24 May 28 01:43:15 PM PDT 24 72318805 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4029719573 May 28 01:43:04 PM PDT 24 May 28 01:43:09 PM PDT 24 148064199 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1336868154 May 28 01:42:35 PM PDT 24 May 28 01:42:39 PM PDT 24 466126261 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.388042456 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 166711241 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3968449822 May 28 01:42:36 PM PDT 24 May 28 01:42:39 PM PDT 24 14851523 ps
T946 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.487994926 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 85325239 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.365920870 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 19727336 ps
T194 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2401495355 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 14160026 ps
T195 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3542486592 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 38617013 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.443534580 May 28 01:44:20 PM PDT 24 May 28 01:44:25 PM PDT 24 264884596 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4280439961 May 28 01:43:08 PM PDT 24 May 28 01:43:14 PM PDT 24 27858943 ps
T950 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1057376081 May 28 01:43:07 PM PDT 24 May 28 01:43:17 PM PDT 24 351250140 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.78816876 May 28 01:42:47 PM PDT 24 May 28 01:42:50 PM PDT 24 43100931 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1568056284 May 28 01:46:09 PM PDT 24 May 28 01:46:29 PM PDT 24 328970536 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4268492904 May 28 01:46:18 PM PDT 24 May 28 01:46:40 PM PDT 24 45649097 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1474684820 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 143703225 ps
T955 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2619630371 May 28 01:43:16 PM PDT 24 May 28 01:43:19 PM PDT 24 72727309 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.965826184 May 28 01:42:34 PM PDT 24 May 28 01:42:38 PM PDT 24 81311824 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1811908260 May 28 01:43:06 PM PDT 24 May 28 01:43:13 PM PDT 24 39065498 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.301809595 May 28 01:46:09 PM PDT 24 May 28 01:46:40 PM PDT 24 496597143 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4094726114 May 28 01:42:31 PM PDT 24 May 28 01:42:35 PM PDT 24 92562048 ps
T960 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1876653109 May 28 01:42:36 PM PDT 24 May 28 01:42:49 PM PDT 24 1828798146 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1256173145 May 28 01:42:34 PM PDT 24 May 28 01:42:38 PM PDT 24 28451385 ps
T962 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.353846273 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 59340616 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3047109931 May 28 01:42:44 PM PDT 24 May 28 01:42:47 PM PDT 24 189321457 ps
T964 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.425449445 May 28 01:43:04 PM PDT 24 May 28 01:43:09 PM PDT 24 262312436 ps
T131 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.981650487 May 28 01:43:05 PM PDT 24 May 28 01:43:10 PM PDT 24 46011257 ps
T129 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.59564807 May 28 01:42:32 PM PDT 24 May 28 01:42:37 PM PDT 24 130391816 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3097903595 May 28 01:45:33 PM PDT 24 May 28 01:45:36 PM PDT 24 51737247 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2927417733 May 28 01:42:36 PM PDT 24 May 28 01:42:43 PM PDT 24 2593076487 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3457781102 May 28 01:44:01 PM PDT 24 May 28 01:44:05 PM PDT 24 131814011 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2041891642 May 28 01:43:04 PM PDT 24 May 28 01:43:08 PM PDT 24 115447153 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1033305591 May 28 01:46:13 PM PDT 24 May 28 01:46:35 PM PDT 24 155196809 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3374740107 May 28 01:42:34 PM PDT 24 May 28 01:42:38 PM PDT 24 187213344 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3289996130 May 28 01:43:03 PM PDT 24 May 28 01:43:05 PM PDT 24 15388673 ps
T196 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2419219275 May 28 01:43:16 PM PDT 24 May 28 01:43:18 PM PDT 24 13724952 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3251053483 May 28 01:42:47 PM PDT 24 May 28 01:42:50 PM PDT 24 719675683 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1295427059 May 28 01:42:37 PM PDT 24 May 28 01:42:39 PM PDT 24 16329540 ps
T974 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.521022604 May 28 01:43:03 PM PDT 24 May 28 01:43:06 PM PDT 24 517535123 ps
T975 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.981865395 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 51689308 ps
T976 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4222426216 May 28 01:43:03 PM PDT 24 May 28 01:43:05 PM PDT 24 41676172 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.242333266 May 28 01:42:32 PM PDT 24 May 28 01:42:37 PM PDT 24 744368567 ps
T978 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3677904477 May 28 01:42:33 PM PDT 24 May 28 01:42:39 PM PDT 24 547199755 ps
T979 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1524216463 May 28 01:42:32 PM PDT 24 May 28 01:42:34 PM PDT 24 25206059 ps
T197 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2963312907 May 28 01:42:31 PM PDT 24 May 28 01:42:34 PM PDT 24 61938145 ps
T198 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2651061925 May 28 01:43:06 PM PDT 24 May 28 01:43:12 PM PDT 24 13781487 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2841709916 May 28 01:43:06 PM PDT 24 May 28 01:43:14 PM PDT 24 48936770 ps
T981 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4127103832 May 28 01:43:11 PM PDT 24 May 28 01:43:16 PM PDT 24 17962043 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3319820411 May 28 01:46:02 PM PDT 24 May 28 01:46:26 PM PDT 24 1347257447 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2665211002 May 28 01:46:12 PM PDT 24 May 28 01:46:32 PM PDT 24 94278384 ps
T984 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3493458009 May 28 01:43:08 PM PDT 24 May 28 01:43:15 PM PDT 24 86070712 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.713804310 May 28 01:46:09 PM PDT 24 May 28 01:46:29 PM PDT 24 24622090 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3153432072 May 28 01:43:07 PM PDT 24 May 28 01:43:16 PM PDT 24 126152144 ps
T987 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1721337668 May 28 01:43:07 PM PDT 24 May 28 01:43:14 PM PDT 24 125253237 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2111336900 May 28 01:43:05 PM PDT 24 May 28 01:43:31 PM PDT 24 4050229623 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3768100408 May 28 01:44:11 PM PDT 24 May 28 01:44:12 PM PDT 24 22218026 ps
T212 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3994925032 May 28 01:43:08 PM PDT 24 May 28 01:43:15 PM PDT 24 160961863 ps
T126 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2645884005 May 28 01:43:20 PM PDT 24 May 28 01:43:25 PM PDT 24 76874607 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.448163798 May 28 01:43:03 PM PDT 24 May 28 01:43:07 PM PDT 24 1115697297 ps
T125 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1236514252 May 28 01:43:05 PM PDT 24 May 28 01:43:11 PM PDT 24 234688177 ps
T132 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.840967532 May 28 01:43:06 PM PDT 24 May 28 01:43:15 PM PDT 24 128371089 ps
T199 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.15398963 May 28 01:43:07 PM PDT 24 May 28 01:43:13 PM PDT 24 14214976 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3728403146 May 28 01:43:04 PM PDT 24 May 28 01:43:11 PM PDT 24 478596241 ps
T992 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2655052417 May 28 01:42:32 PM PDT 24 May 28 01:42:41 PM PDT 24 2461928624 ps
T993 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1939786314 May 28 01:42:59 PM PDT 24 May 28 01:43:02 PM PDT 24 597763943 ps
T994 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1637277576 May 28 01:45:01 PM PDT 24 May 28 01:45:04 PM PDT 24 170015090 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1986070206 May 28 01:46:11 PM PDT 24 May 28 01:46:34 PM PDT 24 726444573 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3910431032 May 28 01:46:09 PM PDT 24 May 28 01:46:30 PM PDT 24 294496223 ps
T997 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.616356200 May 28 01:42:33 PM PDT 24 May 28 01:42:37 PM PDT 24 200128082 ps

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3412681318
Short name T14
Test name
Test status
Simulation time 348642540 ps
CPU time 12.32 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218236 kb
Host smart-0d4495c0-4154-4986-a5c0-fb671982d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412681318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3412681318
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1220532118
Short name T19
Test name
Test status
Simulation time 15508855797 ps
CPU time 280.73 seconds
Started May 28 02:50:57 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 250900 kb
Host smart-da0c2cf3-665b-49f9-900a-54d7a6f22eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220532118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1220532118
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2143200110
Short name T91
Test name
Test status
Simulation time 35409021117 ps
CPU time 808.85 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 03:04:59 PM PDT 24
Peak memory 496964 kb
Host smart-2440936a-f983-4b32-bf89-1a24562400d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2143200110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2143200110
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.519551283
Short name T17
Test name
Test status
Simulation time 5457293337 ps
CPU time 23.57 seconds
Started May 28 02:48:59 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 219580 kb
Host smart-a2b5a1b9-f4dc-47bc-9af7-fe36899d0467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519551283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.519551283
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.524828709
Short name T114
Test name
Test status
Simulation time 120779353 ps
CPU time 3.03 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 222280 kb
Host smart-31a975e4-655c-4855-8e3f-9c5ab1555b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524828709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.524828709
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1213620683
Short name T3
Test name
Test status
Simulation time 13706917 ps
CPU time 0.85 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 208608 kb
Host smart-fa2dfbaf-8970-4fa6-a35c-ff3c81de62ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213620683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1213620683
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4033157681
Short name T35
Test name
Test status
Simulation time 649435482 ps
CPU time 13.43 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:07 PM PDT 24
Peak memory 218168 kb
Host smart-7fc36508-0545-4720-8da3-d09e45848c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033157681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4033157681
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3807557398
Short name T149
Test name
Test status
Simulation time 185993890636 ps
CPU time 507.35 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:58:52 PM PDT 24
Peak memory 333052 kb
Host smart-e71bb7be-b28f-4a65-a402-2ad10e7c0240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3807557398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3807557398
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4001258765
Short name T61
Test name
Test status
Simulation time 834391305 ps
CPU time 37.83 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 282184 kb
Host smart-47e0d371-f88d-4ba0-837e-a961de59b5fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001258765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4001258765
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.449880879
Short name T133
Test name
Test status
Simulation time 618954885 ps
CPU time 4.81 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 219036 kb
Host smart-d4b7319b-fe3e-42d0-ac30-e43298d43169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449880
879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.449880879
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3235048057
Short name T21
Test name
Test status
Simulation time 5696767656 ps
CPU time 133 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:52:06 PM PDT 24
Peak memory 276100 kb
Host smart-69de86ea-0d38-4ed4-aa0b-d632cc3559fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235048057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3235048057
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3182398498
Short name T2
Test name
Test status
Simulation time 3101504305 ps
CPU time 8.9 seconds
Started May 28 02:50:32 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 218228 kb
Host smart-47e26923-a1c6-4ba7-bd22-06d1a7b6e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182398498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3182398498
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3401282052
Short name T8
Test name
Test status
Simulation time 1136178979 ps
CPU time 9.58 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 217132 kb
Host smart-598f26a7-28ea-4ee7-8150-b57326423235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401282052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3401282052
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3235985476
Short name T10
Test name
Test status
Simulation time 314693593 ps
CPU time 1 seconds
Started May 28 02:50:26 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 209704 kb
Host smart-69015e38-62d1-49c1-9089-e902cb65c16c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235985476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3235985476
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2889005377
Short name T11
Test name
Test status
Simulation time 767536472 ps
CPU time 11.47 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 218108 kb
Host smart-a9fff39c-be79-4dcc-93fd-bed1b8256415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889005377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
889005377
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2963312907
Short name T197
Test name
Test status
Simulation time 61938145 ps
CPU time 1.09 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:34 PM PDT 24
Peak memory 209552 kb
Host smart-451517d5-d7a2-4e2c-b69d-ae6eb00955ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963312907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2963312907
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.923965740
Short name T165
Test name
Test status
Simulation time 136993784 ps
CPU time 5.17 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:18 PM PDT 24
Peak memory 217640 kb
Host smart-0d7bdfc1-663c-40f4-8610-c54b407a6c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923965740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.923965740
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1374752055
Short name T124
Test name
Test status
Simulation time 78816031 ps
CPU time 3.26 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 222000 kb
Host smart-a9d27939-f009-43c4-a839-811d6a07f102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374752055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1374752055
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.343688049
Short name T135
Test name
Test status
Simulation time 263079151 ps
CPU time 3.36 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 222220 kb
Host smart-2f90e5c5-38ce-415f-b16c-1952ddb1c96f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343688049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.343688049
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1618515666
Short name T52
Test name
Test status
Simulation time 1279099531 ps
CPU time 12.01 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218100 kb
Host smart-5eb38215-7d55-4c91-85f3-5661daa461a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618515666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1618515666
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.59564807
Short name T129
Test name
Test status
Simulation time 130391816 ps
CPU time 3.88 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 217680 kb
Host smart-3c642ce5-5853-4ee8-9f0f-a29adc98a9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59564807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_er
r.59564807
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.213411237
Short name T54
Test name
Test status
Simulation time 1181737946 ps
CPU time 10.46 seconds
Started May 28 02:50:41 PM PDT 24
Finished May 28 02:51:02 PM PDT 24
Peak memory 218184 kb
Host smart-215aac3e-86bf-421a-995a-30eaf7151657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213411237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.213411237
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3067341511
Short name T110
Test name
Test status
Simulation time 1787272135 ps
CPU time 67.25 seconds
Started May 28 02:50:22 PM PDT 24
Finished May 28 02:51:36 PM PDT 24
Peak memory 276088 kb
Host smart-2fc559c9-e8a7-4ac3-8351-ac5b6836d52c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067341511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3067341511
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4129753058
Short name T137
Test name
Test status
Simulation time 138288123 ps
CPU time 3.36 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 222148 kb
Host smart-72896fe7-1917-49b9-bf35-844e2466dda8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129753058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4129753058
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.700501465
Short name T139
Test name
Test status
Simulation time 120833548 ps
CPU time 1.12 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:33 PM PDT 24
Peak memory 209500 kb
Host smart-3ee09e43-2603-4e17-a239-64fc4553e60d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700501465 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.700501465
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2156232957
Short name T15
Test name
Test status
Simulation time 34399149 ps
CPU time 0.97 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 209616 kb
Host smart-0316703e-789a-4aae-a452-13c1f07bc822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156232957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2156232957
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2103619772
Short name T37
Test name
Test status
Simulation time 24711492 ps
CPU time 0.8 seconds
Started May 28 02:49:19 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 209512 kb
Host smart-4a918d28-d6f8-45bb-8071-a2f521020139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103619772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2103619772
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.981650487
Short name T131
Test name
Test status
Simulation time 46011257 ps
CPU time 2.38 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 222108 kb
Host smart-83688d8f-8aa5-47fd-bfc9-8bb6da34d384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981650487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.981650487
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1085487266
Short name T63
Test name
Test status
Simulation time 378537699 ps
CPU time 8.99 seconds
Started May 28 02:48:57 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 218024 kb
Host smart-aaa70068-0ba0-4579-9be2-c2227fc96e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085487266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1085487266
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2692123911
Short name T208
Test name
Test status
Simulation time 49660833 ps
CPU time 0.8 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 209512 kb
Host smart-eabfece2-be6d-427f-897b-352a4747f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692123911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2692123911
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.437009998
Short name T211
Test name
Test status
Simulation time 21881982 ps
CPU time 0.82 seconds
Started May 28 02:49:08 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 209564 kb
Host smart-c60f0cf0-f521-4641-82ae-9b36565bbe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437009998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.437009998
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1970771034
Short name T210
Test name
Test status
Simulation time 47819666 ps
CPU time 0.83 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:21 PM PDT 24
Peak memory 209520 kb
Host smart-ac5eee39-acff-4698-9275-c02a89a42a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970771034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1970771034
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1506267857
Short name T209
Test name
Test status
Simulation time 36878793 ps
CPU time 0.92 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 209580 kb
Host smart-36fdcb6a-84ba-4110-8023-e680f0bdf60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506267857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1506267857
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4294132720
Short name T20
Test name
Test status
Simulation time 1844172785 ps
CPU time 65.14 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 272652 kb
Host smart-e7c328d2-c94e-4ce5-8003-11b60a160371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294132720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4294132720
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.319345989
Short name T141
Test name
Test status
Simulation time 247090458 ps
CPU time 1.54 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:33 PM PDT 24
Peak memory 218800 kb
Host smart-68459827-b4ec-4fe8-ba24-8b182abe4f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319345
989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.319345989
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4260819128
Short name T901
Test name
Test status
Simulation time 37376837 ps
CPU time 2.21 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:33 PM PDT 24
Peak memory 218836 kb
Host smart-d6849363-17f7-40fb-beeb-4685983d2dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260819128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4260819128
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2781421089
Short name T117
Test name
Test status
Simulation time 366405431 ps
CPU time 3.9 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 217680 kb
Host smart-ce7c01fd-a55f-4f0b-80d7-f1a6075da79b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781421089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2781421089
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.844420116
Short name T138
Test name
Test status
Simulation time 89889934 ps
CPU time 2.19 seconds
Started May 28 01:42:45 PM PDT 24
Finished May 28 01:42:48 PM PDT 24
Peak memory 217768 kb
Host smart-9d162ede-e09b-44cc-a96c-6571e0560cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844420116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.844420116
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2370388334
Short name T121
Test name
Test status
Simulation time 185664139 ps
CPU time 2.6 seconds
Started May 28 01:43:28 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 222048 kb
Host smart-acde71b0-7b60-4f5c-b89a-3b7880176f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370388334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2370388334
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.388042456
Short name T128
Test name
Test status
Simulation time 166711241 ps
CPU time 2.28 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 217680 kb
Host smart-4641e7af-e0b0-422e-bdea-178993f087db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388042456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.388042456
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2066840064
Short name T1
Test name
Test status
Simulation time 1092534855 ps
CPU time 25.39 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 251040 kb
Host smart-5b627a2a-f117-46ac-abd6-83ee58035fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066840064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2066840064
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3470101911
Short name T25
Test name
Test status
Simulation time 908551364 ps
CPU time 11.62 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 218096 kb
Host smart-c4610c76-6829-47d4-a599-3572d9e94c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470101911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3470101911
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1917008045
Short name T869
Test name
Test status
Simulation time 79447645 ps
CPU time 1.25 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 209460 kb
Host smart-07361b62-6b62-4162-bf98-5b1f1625c292
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917008045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1917008045
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.918042781
Short name T870
Test name
Test status
Simulation time 37379673 ps
CPU time 0.89 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:33 PM PDT 24
Peak memory 209720 kb
Host smart-fd2bd769-7fdb-4a99-a510-617e76b30628
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918042781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.918042781
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.37303190
Short name T937
Test name
Test status
Simulation time 29685451 ps
CPU time 1.67 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 219784 kb
Host smart-97f79967-0eb0-4f37-9969-a93b8673c1f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37303190 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.37303190
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3968449822
Short name T193
Test name
Test status
Simulation time 14851523 ps
CPU time 1.02 seconds
Started May 28 01:42:36 PM PDT 24
Finished May 28 01:42:39 PM PDT 24
Peak memory 209308 kb
Host smart-de1b86f0-6afa-4eb1-b147-e420afd1c011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968449822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3968449822
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1135403898
Short name T871
Test name
Test status
Simulation time 32825969 ps
CPU time 1.48 seconds
Started May 28 01:42:30 PM PDT 24
Finished May 28 01:42:32 PM PDT 24
Peak memory 208044 kb
Host smart-857315b0-e80e-42a5-acb1-23b03c8b4f7a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135403898 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1135403898
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.988941445
Short name T123
Test name
Test status
Simulation time 1133900557 ps
CPU time 4.82 seconds
Started May 28 01:42:26 PM PDT 24
Finished May 28 01:42:33 PM PDT 24
Peak memory 208564 kb
Host smart-17dd9276-cc76-42fd-94a7-b9c9269c958f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988941445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.988941445
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.758243507
Short name T881
Test name
Test status
Simulation time 876636565 ps
CPU time 17.82 seconds
Started May 28 01:42:20 PM PDT 24
Finished May 28 01:42:45 PM PDT 24
Peak memory 208564 kb
Host smart-817fdf02-9531-4a7b-9f21-f57bf8f1462f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758243507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.758243507
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4186591369
Short name T889
Test name
Test status
Simulation time 259052491 ps
CPU time 1.41 seconds
Started May 28 01:42:20 PM PDT 24
Finished May 28 01:42:28 PM PDT 24
Peak memory 210756 kb
Host smart-ddc6b800-8834-44ce-9e95-f922ad48d373
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186591369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4186591369
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1336868154
Short name T945
Test name
Test status
Simulation time 466126261 ps
CPU time 2.09 seconds
Started May 28 01:42:35 PM PDT 24
Finished May 28 01:42:39 PM PDT 24
Peak memory 221372 kb
Host smart-2df7f22e-5726-4903-a8ac-0c36b0ec72a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133686
8154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1336868154
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.542688165
Short name T888
Test name
Test status
Simulation time 369494158 ps
CPU time 2.54 seconds
Started May 28 01:42:25 PM PDT 24
Finished May 28 01:42:31 PM PDT 24
Peak memory 209380 kb
Host smart-fd609718-e50f-4bba-b015-c55d01640c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542688165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.542688165
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1524216463
Short name T979
Test name
Test status
Simulation time 25206059 ps
CPU time 1.12 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:34 PM PDT 24
Peak memory 209436 kb
Host smart-97003129-116d-4985-ab2a-d4e378184bb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524216463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1524216463
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2864441730
Short name T113
Test name
Test status
Simulation time 99842477 ps
CPU time 1.95 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 217708 kb
Host smart-c49b09d3-6087-4b59-8145-e214650c96cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864441730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2864441730
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1078867475
Short name T916
Test name
Test status
Simulation time 16540079 ps
CPU time 1.2 seconds
Started May 28 01:42:48 PM PDT 24
Finished May 28 01:42:50 PM PDT 24
Peak memory 209476 kb
Host smart-3407658e-115a-45ed-a895-aca6fcc216ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078867475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1078867475
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2095957863
Short name T926
Test name
Test status
Simulation time 42304379 ps
CPU time 1.79 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 209412 kb
Host smart-38b6d73f-6256-4a27-9816-976316178fe1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095957863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2095957863
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1295427059
Short name T973
Test name
Test status
Simulation time 16329540 ps
CPU time 0.92 seconds
Started May 28 01:42:37 PM PDT 24
Finished May 28 01:42:39 PM PDT 24
Peak memory 209840 kb
Host smart-40eb072e-978e-441b-a400-8f8a590b97bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295427059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1295427059
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3017522856
Short name T910
Test name
Test status
Simulation time 89350301 ps
CPU time 1.06 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:35 PM PDT 24
Peak memory 217720 kb
Host smart-916dd9f0-1c5d-4437-98d6-b40edf5a04e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017522856 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3017522856
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.313297866
Short name T872
Test name
Test status
Simulation time 12778747 ps
CPU time 0.83 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:35 PM PDT 24
Peak memory 209296 kb
Host smart-ae355b9c-c732-4732-9023-4b26daf4815e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313297866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.313297866
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.78816876
Short name T951
Test name
Test status
Simulation time 43100931 ps
CPU time 1.58 seconds
Started May 28 01:42:47 PM PDT 24
Finished May 28 01:42:50 PM PDT 24
Peak memory 207972 kb
Host smart-53efdaf9-d7be-41c8-8e17-085997309162
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78816876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_alert_test.78816876
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2927417733
Short name T966
Test name
Test status
Simulation time 2593076487 ps
CPU time 5.11 seconds
Started May 28 01:42:36 PM PDT 24
Finished May 28 01:42:43 PM PDT 24
Peak memory 209460 kb
Host smart-4bfd1796-330b-41ce-aa90-504d12f11248
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927417733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2927417733
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1876653109
Short name T960
Test name
Test status
Simulation time 1828798146 ps
CPU time 11.2 seconds
Started May 28 01:42:36 PM PDT 24
Finished May 28 01:42:49 PM PDT 24
Peak memory 209068 kb
Host smart-3c04c469-99e8-4927-95d2-a39dfc8fc4a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876653109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1876653109
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3056091937
Short name T931
Test name
Test status
Simulation time 538310163 ps
CPU time 3.81 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 211028 kb
Host smart-9886245e-ff05-4b7b-a3f7-9a4fc1d441eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056091937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3056091937
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3856578575
Short name T941
Test name
Test status
Simulation time 128683574 ps
CPU time 1.48 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 209408 kb
Host smart-48b6227e-dc52-4d2a-8514-da6755e38ba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856578575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3856578575
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1656406294
Short name T934
Test name
Test status
Simulation time 287209047 ps
CPU time 1.57 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 209476 kb
Host smart-3e85fbfa-a196-45ca-82ce-8c8ee7b8eb2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656406294 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1656406294
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4094726114
Short name T959
Test name
Test status
Simulation time 92562048 ps
CPU time 2 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:35 PM PDT 24
Peak memory 217684 kb
Host smart-39ee0288-6a87-4d4f-8690-db587979a3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094726114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4094726114
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3212398125
Short name T112
Test name
Test status
Simulation time 206670926 ps
CPU time 2.3 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 217656 kb
Host smart-c8875a05-5e86-4037-978f-a6f271df3973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212398125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3212398125
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.353846273
Short name T962
Test name
Test status
Simulation time 59340616 ps
CPU time 1.61 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 217820 kb
Host smart-3cbb0775-2513-4378-90e1-3ca0ade75b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353846273 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.353846273
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3848377489
Short name T940
Test name
Test status
Simulation time 39616951 ps
CPU time 1.12 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 217336 kb
Host smart-cbb4ae16-76a6-4ee8-8f2f-d7634516ad31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848377489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3848377489
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3379583878
Short name T877
Test name
Test status
Simulation time 113478040 ps
CPU time 1.81 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 209548 kb
Host smart-a79d9dec-2503-4754-9f4f-b9642c861fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379583878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3379583878
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1721337668
Short name T987
Test name
Test status
Simulation time 125253237 ps
CPU time 2.23 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217828 kb
Host smart-d2390734-8265-4918-8f9d-387e23618a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721337668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1721337668
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1690408644
Short name T163
Test name
Test status
Simulation time 188094659 ps
CPU time 1.14 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 218900 kb
Host smart-486fd6ee-9f26-4709-a631-dc848ae89584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690408644 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1690408644
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2401495355
Short name T194
Test name
Test status
Simulation time 14160026 ps
CPU time 1.03 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 209492 kb
Host smart-30e172ba-c66b-4047-8e71-e5223c7e2785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401495355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2401495355
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1727768572
Short name T203
Test name
Test status
Simulation time 38662008 ps
CPU time 1.93 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 211788 kb
Host smart-a279755a-98b7-4361-8c75-4656b59e732f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727768572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1727768572
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3493458009
Short name T984
Test name
Test status
Simulation time 86070712 ps
CPU time 2.52 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 218392 kb
Host smart-08e432b8-e2fb-48d1-87de-dbf8db2ea48e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493458009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3493458009
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1316549999
Short name T892
Test name
Test status
Simulation time 80363351 ps
CPU time 1.06 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 217560 kb
Host smart-2913ad8c-b25d-40c7-a76d-259fb29635c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316549999 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1316549999
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2651061925
Short name T198
Test name
Test status
Simulation time 13781487 ps
CPU time 0.9 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 209464 kb
Host smart-cc4ce498-f593-4675-a3a3-4ec49396b846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651061925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2651061925
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3204676361
Short name T204
Test name
Test status
Simulation time 21111586 ps
CPU time 1.52 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 211560 kb
Host smart-01368407-ad59-4616-8efb-86ba4a47d3ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204676361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3204676361
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2757308642
Short name T907
Test name
Test status
Simulation time 81405416 ps
CPU time 2.45 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 217716 kb
Host smart-b560d20d-834d-4d0d-b51f-49edebae5a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757308642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2757308642
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2665393274
Short name T890
Test name
Test status
Simulation time 39472576 ps
CPU time 0.96 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 217744 kb
Host smart-307fe08b-1b9b-4a3f-8ce0-b7d8854a848b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665393274 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2665393274
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.981865395
Short name T975
Test name
Test status
Simulation time 51689308 ps
CPU time 0.99 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 209404 kb
Host smart-25262234-96d2-46dd-86f9-c9ecc5463736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981865395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.981865395
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3592748035
Short name T938
Test name
Test status
Simulation time 50134754 ps
CPU time 0.99 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 209448 kb
Host smart-2b873468-32e6-45b6-b8ed-cd5095c124ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592748035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3592748035
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3238389959
Short name T166
Test name
Test status
Simulation time 37094246 ps
CPU time 1.21 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217712 kb
Host smart-f78ebaed-abcf-4bc0-88e8-645f9709bec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238389959 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3238389959
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.765940403
Short name T164
Test name
Test status
Simulation time 17511714 ps
CPU time 1.12 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 209480 kb
Host smart-8fcacda3-8b69-4b52-8337-fe45931839ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765940403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.765940403
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4280439961
Short name T949
Test name
Test status
Simulation time 27858943 ps
CPU time 1.43 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 209540 kb
Host smart-2854a101-2e22-4fcb-966f-427d4445ddfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280439961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4280439961
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1057376081
Short name T950
Test name
Test status
Simulation time 351250140 ps
CPU time 4.44 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:17 PM PDT 24
Peak memory 217748 kb
Host smart-b7e70634-18e2-433e-930d-f80c0feb768a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057376081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1057376081
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3994925032
Short name T212
Test name
Test status
Simulation time 160961863 ps
CPU time 1.79 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 222032 kb
Host smart-3ffd9563-1caa-4539-b524-e4743cf351e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994925032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3994925032
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4127103832
Short name T981
Test name
Test status
Simulation time 17962043 ps
CPU time 1.51 seconds
Started May 28 01:43:11 PM PDT 24
Finished May 28 01:43:16 PM PDT 24
Peak memory 219104 kb
Host smart-4e851d50-7336-4a02-b6c7-e0df4434ae68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127103832 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4127103832
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.15398963
Short name T199
Test name
Test status
Simulation time 14214976 ps
CPU time 1.02 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 209480 kb
Host smart-685f65e2-2602-491d-b6bb-27c1616de39b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15398963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.15398963
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2231509997
Short name T882
Test name
Test status
Simulation time 28217663 ps
CPU time 1.14 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 209472 kb
Host smart-a577639f-7c8e-41ce-9897-63bccc2dfdf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231509997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2231509997
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.487994926
Short name T946
Test name
Test status
Simulation time 85325239 ps
CPU time 2.17 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 217744 kb
Host smart-70da4e83-269a-4a86-ace8-0014b74a2d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487994926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.487994926
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2414572450
Short name T893
Test name
Test status
Simulation time 42027576 ps
CPU time 1.08 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 218852 kb
Host smart-866f4803-ea6e-48dd-a11c-4486f6a22937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414572450 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2414572450
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3431286295
Short name T905
Test name
Test status
Simulation time 56747616 ps
CPU time 1.03 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 209396 kb
Host smart-e310398e-3884-44c0-b25e-9a70e3911506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431286295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3431286295
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1521305792
Short name T942
Test name
Test status
Simulation time 48993577 ps
CPU time 1.42 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 209476 kb
Host smart-90f4c616-d089-4486-b41a-ed3ebae5f88b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521305792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1521305792
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.818336268
Short name T120
Test name
Test status
Simulation time 49510389 ps
CPU time 2.26 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217732 kb
Host smart-3463bf1e-9a8e-4a31-99f2-ec4e4cb0f5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818336268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.818336268
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.794382606
Short name T919
Test name
Test status
Simulation time 111728325 ps
CPU time 2.06 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 221832 kb
Host smart-f9863b57-2704-4f1c-974f-edf8e76f5519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794382606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.794382606
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2182659807
Short name T933
Test name
Test status
Simulation time 93450906 ps
CPU time 1.19 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:06 PM PDT 24
Peak memory 217808 kb
Host smart-86c7c641-6fd6-40af-8235-afe4ee00e32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182659807 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2182659807
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4093692776
Short name T908
Test name
Test status
Simulation time 39645605 ps
CPU time 0.91 seconds
Started May 28 01:43:08 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 209480 kb
Host smart-02fe3718-187b-4967-924c-10a4c864969d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093692776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4093692776
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2047532418
Short name T122
Test name
Test status
Simulation time 16536038 ps
CPU time 1.1 seconds
Started May 28 01:43:02 PM PDT 24
Finished May 28 01:43:04 PM PDT 24
Peak memory 209520 kb
Host smart-2f8184a0-c55a-4208-8499-f5115ffc72cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047532418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2047532418
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.292056854
Short name T911
Test name
Test status
Simulation time 279366555 ps
CPU time 2.44 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 217720 kb
Host smart-e3369399-eb46-4596-8719-5806a686ea87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292056854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.292056854
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1939786314
Short name T993
Test name
Test status
Simulation time 597763943 ps
CPU time 1.83 seconds
Started May 28 01:42:59 PM PDT 24
Finished May 28 01:43:02 PM PDT 24
Peak memory 222072 kb
Host smart-67158527-28c3-4244-8ba3-e5b4842a5576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939786314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1939786314
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3323884034
Short name T930
Test name
Test status
Simulation time 68973465 ps
CPU time 1.16 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:18 PM PDT 24
Peak memory 217716 kb
Host smart-d4fdbc73-e3dc-4d16-a5c8-6cd03c9f2139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323884034 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3323884034
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2419219275
Short name T196
Test name
Test status
Simulation time 13724952 ps
CPU time 1.13 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:18 PM PDT 24
Peak memory 209464 kb
Host smart-e0104aca-5190-4dcb-a6f6-3717b98aefe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419219275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2419219275
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3995859755
Short name T886
Test name
Test status
Simulation time 24954337 ps
CPU time 1.4 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:21 PM PDT 24
Peak memory 209536 kb
Host smart-f4035386-e5e4-4743-9b8d-17961633259f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995859755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3995859755
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3400794932
Short name T119
Test name
Test status
Simulation time 174324875 ps
CPU time 2.68 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217940 kb
Host smart-60069048-5857-4b6c-9bac-d081d9c3d79e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400794932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3400794932
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3300824921
Short name T136
Test name
Test status
Simulation time 1236746014 ps
CPU time 3.07 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 222452 kb
Host smart-0bf26f95-8520-4ddf-9c01-5e5333afc7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300824921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3300824921
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2577425449
Short name T127
Test name
Test status
Simulation time 52159559 ps
CPU time 1.85 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:20 PM PDT 24
Peak memory 223460 kb
Host smart-770a0f8e-3b6b-4e14-bb40-e979896004cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577425449 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2577425449
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.692811348
Short name T162
Test name
Test status
Simulation time 15147257 ps
CPU time 0.85 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 209476 kb
Host smart-0315b721-abc9-4e68-8231-50e339338735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692811348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.692811348
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2619630371
Short name T955
Test name
Test status
Simulation time 72727309 ps
CPU time 1.38 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:19 PM PDT 24
Peak memory 209584 kb
Host smart-a3ea2879-9e71-46c4-b10a-e461c2ea7c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619630371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2619630371
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4007711659
Short name T115
Test name
Test status
Simulation time 25580335 ps
CPU time 1.77 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:20 PM PDT 24
Peak memory 217824 kb
Host smart-abf7a358-09cc-4cd1-87cd-3a1f88b28625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007711659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4007711659
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2645884005
Short name T126
Test name
Test status
Simulation time 76874607 ps
CPU time 3.45 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 217680 kb
Host smart-ee75361d-53b5-471d-80fd-7606c76ac607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645884005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2645884005
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4206910999
Short name T895
Test name
Test status
Simulation time 367520120 ps
CPU time 1.22 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:34 PM PDT 24
Peak memory 209332 kb
Host smart-21677aea-78a2-450e-8dab-b0e1c8155ec8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206910999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.4206910999
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1256173145
Short name T961
Test name
Test status
Simulation time 28451385 ps
CPU time 1.96 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:38 PM PDT 24
Peak memory 209452 kb
Host smart-55f15965-4d66-4874-ba08-e7f2cdebba27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256173145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1256173145
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.39334255
Short name T914
Test name
Test status
Simulation time 30236451 ps
CPU time 0.98 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 210372 kb
Host smart-ecbb285d-5dbe-4adf-b14a-42430c9ab376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39334255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset.39334255
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.965826184
Short name T956
Test name
Test status
Simulation time 81311824 ps
CPU time 1.77 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:38 PM PDT 24
Peak memory 219256 kb
Host smart-86fb4282-4d83-4bed-82a5-c06de00c6560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965826184 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.965826184
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2673112138
Short name T190
Test name
Test status
Simulation time 41478215 ps
CPU time 0.78 seconds
Started May 28 01:42:35 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 209328 kb
Host smart-aa66bfe8-c3cc-4200-b8b8-de4ccabf72e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673112138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2673112138
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.242333266
Short name T977
Test name
Test status
Simulation time 744368567 ps
CPU time 3.14 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 209148 kb
Host smart-8164f39e-126b-49a2-94b3-05b351b1a0aa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242333266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.242333266
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3894944032
Short name T900
Test name
Test status
Simulation time 696355916 ps
CPU time 5.83 seconds
Started May 28 01:42:31 PM PDT 24
Finished May 28 01:42:38 PM PDT 24
Peak memory 208596 kb
Host smart-f7c71526-1a61-4dd2-9e1c-c8204e7519d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894944032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3894944032
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2655052417
Short name T992
Test name
Test status
Simulation time 2461928624 ps
CPU time 7.37 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:41 PM PDT 24
Peak memory 208640 kb
Host smart-47fde961-8374-4ca0-9f83-019eaca5fb9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655052417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2655052417
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3251053483
Short name T972
Test name
Test status
Simulation time 719675683 ps
CPU time 1.62 seconds
Started May 28 01:42:47 PM PDT 24
Finished May 28 01:42:50 PM PDT 24
Peak memory 210968 kb
Host smart-d883ad57-4a3f-4798-b9f7-a234fea1155f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251053483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3251053483
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.788421109
Short name T142
Test name
Test status
Simulation time 170822263 ps
CPU time 1.59 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 218040 kb
Host smart-6a7c3d02-f852-4b47-b5c5-3ba97c011cad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788421
109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.788421109
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1739772956
Short name T935
Test name
Test status
Simulation time 54608292 ps
CPU time 1.21 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:35 PM PDT 24
Peak memory 209480 kb
Host smart-2b3ca293-80f7-4fee-9db2-89d08c82b689
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739772956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1739772956
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3249867485
Short name T896
Test name
Test status
Simulation time 16435589 ps
CPU time 0.99 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 209456 kb
Host smart-6269b290-d8ba-441f-b528-adb2e31e46b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249867485 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3249867485
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3047109931
Short name T963
Test name
Test status
Simulation time 189321457 ps
CPU time 1.84 seconds
Started May 28 01:42:44 PM PDT 24
Finished May 28 01:42:47 PM PDT 24
Peak memory 211424 kb
Host smart-4462b5aa-c9f0-44dd-90ea-fa428956b481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047109931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3047109931
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.616356200
Short name T997
Test name
Test status
Simulation time 200128082 ps
CPU time 2.37 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:37 PM PDT 24
Peak memory 217716 kb
Host smart-49078b0b-c4e2-41fd-ae0e-96705349b2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616356200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.616356200
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2066748931
Short name T191
Test name
Test status
Simulation time 28301983 ps
CPU time 1.06 seconds
Started May 28 01:46:00 PM PDT 24
Finished May 28 01:46:04 PM PDT 24
Peak memory 209460 kb
Host smart-b6ccb008-9137-4286-a396-351146240503
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066748931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2066748931
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.443534580
Short name T948
Test name
Test status
Simulation time 264884596 ps
CPU time 1.73 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:25 PM PDT 24
Peak memory 209456 kb
Host smart-d47344cd-ab08-439a-a4ce-b094df393332
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443534580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.443534580
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2757510953
Short name T874
Test name
Test status
Simulation time 20432172 ps
CPU time 1.23 seconds
Started May 28 01:44:02 PM PDT 24
Finished May 28 01:44:04 PM PDT 24
Peak memory 209440 kb
Host smart-003aabe9-174b-4aae-8814-3bfa6af961cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757510953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2757510953
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3726538990
Short name T118
Test name
Test status
Simulation time 32523902 ps
CPU time 2.51 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:31 PM PDT 24
Peak memory 223580 kb
Host smart-9466564d-b34f-4e6a-a432-b6ff42eaca3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726538990 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3726538990
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1718838317
Short name T899
Test name
Test status
Simulation time 11953189 ps
CPU time 0.99 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 209116 kb
Host smart-14ddb8e9-0f70-417b-97a3-46e0cb6f926c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718838317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1718838317
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3311570998
Short name T878
Test name
Test status
Simulation time 90018846 ps
CPU time 1.15 seconds
Started May 28 01:42:32 PM PDT 24
Finished May 28 01:42:35 PM PDT 24
Peak memory 209336 kb
Host smart-24b9f102-f1f0-4d36-b0ce-168e717f859d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311570998 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3311570998
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1438002046
Short name T897
Test name
Test status
Simulation time 291709442 ps
CPU time 3.42 seconds
Started May 28 01:42:35 PM PDT 24
Finished May 28 01:42:40 PM PDT 24
Peak memory 208588 kb
Host smart-d0808e5e-dd3b-4fab-95ee-84ab611cff41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438002046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1438002046
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3075912739
Short name T918
Test name
Test status
Simulation time 810463000 ps
CPU time 9.11 seconds
Started May 28 01:42:36 PM PDT 24
Finished May 28 01:42:47 PM PDT 24
Peak memory 208408 kb
Host smart-768234b9-d7a8-4ce1-b295-3819bd0c7624
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075912739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3075912739
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2633012786
Short name T144
Test name
Test status
Simulation time 90973222 ps
CPU time 1.66 seconds
Started May 28 01:42:44 PM PDT 24
Finished May 28 01:42:46 PM PDT 24
Peak memory 210904 kb
Host smart-9bba9c28-4390-401b-8296-9827c2ee5537
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633012786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2633012786
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3374740107
Short name T970
Test name
Test status
Simulation time 187213344 ps
CPU time 2.9 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:38 PM PDT 24
Peak memory 217716 kb
Host smart-008773d8-700d-4019-a74b-b1c5cdc5a0c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337474
0107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3374740107
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3614801704
Short name T880
Test name
Test status
Simulation time 104549436 ps
CPU time 1.18 seconds
Started May 28 01:42:48 PM PDT 24
Finished May 28 01:42:50 PM PDT 24
Peak memory 209340 kb
Host smart-d430f4c2-6688-4a63-9e0e-79d13b7690af
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614801704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3614801704
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.445035437
Short name T884
Test name
Test status
Simulation time 19957572 ps
CPU time 1.4 seconds
Started May 28 01:42:34 PM PDT 24
Finished May 28 01:42:38 PM PDT 24
Peak memory 217680 kb
Host smart-30c7cef1-3e30-43d1-8f7e-174771c5b8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445035437 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.445035437
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3125990741
Short name T200
Test name
Test status
Simulation time 68252334 ps
CPU time 1.75 seconds
Started May 28 01:46:01 PM PDT 24
Finished May 28 01:46:08 PM PDT 24
Peak memory 209524 kb
Host smart-10daa5fc-fe78-4cf4-9db6-232e90dd4d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125990741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3125990741
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3677904477
Short name T978
Test name
Test status
Simulation time 547199755 ps
CPU time 3.44 seconds
Started May 28 01:42:33 PM PDT 24
Finished May 28 01:42:39 PM PDT 24
Peak memory 217716 kb
Host smart-8de1fc44-c340-459b-be34-041a9a2975ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677904477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3677904477
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.609307779
Short name T130
Test name
Test status
Simulation time 151454463 ps
CPU time 1.89 seconds
Started May 28 01:44:00 PM PDT 24
Finished May 28 01:44:02 PM PDT 24
Peak memory 222056 kb
Host smart-7ef60eb3-2e36-4e6f-b6e9-4625f951b834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609307779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.609307779
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1568056284
Short name T952
Test name
Test status
Simulation time 328970536 ps
CPU time 1.54 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 209540 kb
Host smart-d61b8dce-7b5a-42a1-bd66-a1bb70ee47f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568056284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1568056284
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1611558053
Short name T873
Test name
Test status
Simulation time 133286187 ps
CPU time 1.74 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 209464 kb
Host smart-b80e9ee7-fa11-4b07-840b-76108c80e8bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611558053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1611558053
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3768100408
Short name T989
Test name
Test status
Simulation time 22218026 ps
CPU time 1.09 seconds
Started May 28 01:44:11 PM PDT 24
Finished May 28 01:44:12 PM PDT 24
Peak memory 218012 kb
Host smart-39a0987e-3969-43b0-b5eb-391fb6bf29a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768100408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3768100408
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.713804310
Short name T985
Test name
Test status
Simulation time 24622090 ps
CPU time 1.49 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 217728 kb
Host smart-63454931-3580-41a1-ba9f-0ce2501b8b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713804310 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.713804310
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.77757275
Short name T936
Test name
Test status
Simulation time 23662182 ps
CPU time 1.07 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 208972 kb
Host smart-af5655eb-70f3-4847-93bd-2db78d87e3b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77757275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.77757275
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2293148948
Short name T145
Test name
Test status
Simulation time 335730690 ps
CPU time 1.39 seconds
Started May 28 01:46:08 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 207984 kb
Host smart-ae28b708-e698-44b1-8293-18c701fccd76
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293148948 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2293148948
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.301809595
Short name T958
Test name
Test status
Simulation time 496597143 ps
CPU time 12.43 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 209184 kb
Host smart-6e11d97b-72f5-466d-be8b-49e91f1d5320
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301809595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.301809595
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1566727993
Short name T887
Test name
Test status
Simulation time 1342560034 ps
CPU time 15.47 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:44:14 PM PDT 24
Peak memory 209180 kb
Host smart-69556660-6461-473b-bdb7-be0e8ba58045
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566727993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1566727993
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3910431032
Short name T996
Test name
Test status
Simulation time 294496223 ps
CPU time 2.42 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 210904 kb
Host smart-745bc055-7cce-40b7-bb58-80fa74663e48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910431032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3910431032
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3027265992
Short name T927
Test name
Test status
Simulation time 98335270 ps
CPU time 1.12 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:46:14 PM PDT 24
Peak memory 209372 kb
Host smart-d4e46ee5-c970-4b74-937b-b84f8b5100d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027265992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3027265992
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2990181933
Short name T205
Test name
Test status
Simulation time 39391311 ps
CPU time 1.37 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 209468 kb
Host smart-c6f00a9b-3799-4dfe-9f66-76228571e0b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990181933 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2990181933
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3097903595
Short name T965
Test name
Test status
Simulation time 51737247 ps
CPU time 1.08 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:45:36 PM PDT 24
Peak memory 209484 kb
Host smart-43d9481a-4ad7-4d8b-b925-8177ffcbe9b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097903595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3097903595
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2517932902
Short name T883
Test name
Test status
Simulation time 510076017 ps
CPU time 3.31 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 217808 kb
Host smart-d58056a9-3890-45d9-be60-a87179bd0fce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517932902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2517932902
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4268492904
Short name T953
Test name
Test status
Simulation time 45649097 ps
CPU time 1.43 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 218680 kb
Host smart-c9628ef3-3888-42ae-8ad3-d459ed8a9cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268492904 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4268492904
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1588592
Short name T192
Test name
Test status
Simulation time 19596169 ps
CPU time 0.96 seconds
Started May 28 01:44:00 PM PDT 24
Finished May 28 01:44:02 PM PDT 24
Peak memory 209224 kb
Host smart-dd413f38-cb94-4b74-8b19-dc799e868bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1588592
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2665211002
Short name T983
Test name
Test status
Simulation time 94278384 ps
CPU time 0.96 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 209344 kb
Host smart-b35942e6-22ec-4333-b1fe-935671b61275
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665211002 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2665211002
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2544670635
Short name T143
Test name
Test status
Simulation time 2310018699 ps
CPU time 3.1 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 209208 kb
Host smart-0137c70b-909d-4fb7-a667-25993c1c10de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544670635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2544670635
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1078411752
Short name T904
Test name
Test status
Simulation time 8651036292 ps
CPU time 18.51 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:37 PM PDT 24
Peak memory 209384 kb
Host smart-6aebedb4-742e-48b7-9bec-a7f02b8b210e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078411752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1078411752
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3457781102
Short name T967
Test name
Test status
Simulation time 131814011 ps
CPU time 2.57 seconds
Started May 28 01:44:01 PM PDT 24
Finished May 28 01:44:05 PM PDT 24
Peak memory 210832 kb
Host smart-2bc4026d-2b45-4f97-81ab-2acdeb0ba2fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457781102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3457781102
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2637478442
Short name T140
Test name
Test status
Simulation time 584426013 ps
CPU time 4.3 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 219376 kb
Host smart-a8bd265b-c287-41d5-8b62-e6627985e004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263747
8442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2637478442
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2619436189
Short name T920
Test name
Test status
Simulation time 203771259 ps
CPU time 1.67 seconds
Started May 28 01:44:02 PM PDT 24
Finished May 28 01:44:04 PM PDT 24
Peak memory 209388 kb
Host smart-9a2b6f50-a15c-42c1-8de3-c302fbef6c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619436189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2619436189
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1704152196
Short name T201
Test name
Test status
Simulation time 19392429 ps
CPU time 0.97 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 209172 kb
Host smart-91bb9102-e079-4972-9b76-8806c6cd062c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704152196 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1704152196
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1637277576
Short name T994
Test name
Test status
Simulation time 170015090 ps
CPU time 1.99 seconds
Started May 28 01:45:01 PM PDT 24
Finished May 28 01:45:04 PM PDT 24
Peak memory 211640 kb
Host smart-88987570-5458-4a4f-8734-c909e1a5008f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637277576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1637277576
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3543163921
Short name T894
Test name
Test status
Simulation time 33183678 ps
CPU time 2.1 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 218772 kb
Host smart-587532ce-53d5-4277-9efe-e66f43d81bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543163921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3543163921
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.684397142
Short name T929
Test name
Test status
Simulation time 77400567 ps
CPU time 1.32 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 218464 kb
Host smart-c6a5d64b-7982-4531-b28a-df12fa7c290d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684397142 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.684397142
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.664060075
Short name T876
Test name
Test status
Simulation time 16294611 ps
CPU time 0.94 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 209452 kb
Host smart-cf1ab57e-0d18-4189-aebc-22761bf8d412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664060075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.664060075
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2697386848
Short name T922
Test name
Test status
Simulation time 41899266 ps
CPU time 1.07 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 209356 kb
Host smart-57ca26a6-6651-49da-87c4-7bfba26d7e4f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697386848 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2697386848
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2094989468
Short name T932
Test name
Test status
Simulation time 369223985 ps
CPU time 3.01 seconds
Started May 28 01:44:00 PM PDT 24
Finished May 28 01:44:04 PM PDT 24
Peak memory 208560 kb
Host smart-d6406308-8d64-4a33-9509-88a03fcad3d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094989468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2094989468
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3319820411
Short name T982
Test name
Test status
Simulation time 1347257447 ps
CPU time 18.09 seconds
Started May 28 01:46:02 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 209216 kb
Host smart-3f4d3799-0fe7-4966-bd77-536e81331aa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319820411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3319820411
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1986070206
Short name T995
Test name
Test status
Simulation time 726444573 ps
CPU time 2.22 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 211064 kb
Host smart-8bd829db-b064-407b-82a9-603eeb20728a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986070206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1986070206
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3680788050
Short name T906
Test name
Test status
Simulation time 106860356 ps
CPU time 2.33 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:07 PM PDT 24
Peak memory 219056 kb
Host smart-e80d3f82-49e6-4d4d-8eb3-fc9e7ca5589c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368078
8050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3680788050
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1033305591
Short name T969
Test name
Test status
Simulation time 155196809 ps
CPU time 1.36 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:35 PM PDT 24
Peak memory 209364 kb
Host smart-e5ce6b2e-61c4-44d9-9de9-081668b4ada0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033305591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1033305591
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3587206686
Short name T912
Test name
Test status
Simulation time 36302948 ps
CPU time 1.36 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 211560 kb
Host smart-101f65df-164f-4294-89b1-a61944e599f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587206686 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3587206686
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1064920894
Short name T902
Test name
Test status
Simulation time 50482975 ps
CPU time 1.57 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:06 PM PDT 24
Peak memory 211592 kb
Host smart-c80e696c-29e1-4ce6-a75e-25fbfcc86546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064920894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1064920894
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2841709916
Short name T980
Test name
Test status
Simulation time 48936770 ps
CPU time 3.12 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 218756 kb
Host smart-0a2c91a7-b225-4897-a049-e950ad968cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841709916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2841709916
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3496374171
Short name T134
Test name
Test status
Simulation time 152466989 ps
CPU time 2.26 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217696 kb
Host smart-ea2b9561-3f52-4559-9538-2a420f526eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496374171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3496374171
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.365920870
Short name T947
Test name
Test status
Simulation time 19727336 ps
CPU time 1.2 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 219348 kb
Host smart-dd5607e5-cef7-4d13-bf26-031718bc72da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365920870 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.365920870
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3542486592
Short name T195
Test name
Test status
Simulation time 38617013 ps
CPU time 0.98 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 209264 kb
Host smart-e9664344-f1a9-450a-8afd-c090380de7e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542486592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3542486592
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.425449445
Short name T964
Test name
Test status
Simulation time 262312436 ps
CPU time 2.32 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:09 PM PDT 24
Peak memory 209312 kb
Host smart-80ec8b24-f940-49bd-bfce-53d323a86117
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425449445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.425449445
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2772045726
Short name T885
Test name
Test status
Simulation time 2398327718 ps
CPU time 10.28 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:19 PM PDT 24
Peak memory 209456 kb
Host smart-24888b70-1afd-4473-a541-9854a326d8f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772045726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2772045726
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2111336900
Short name T988
Test name
Test status
Simulation time 4050229623 ps
CPU time 20.97 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:31 PM PDT 24
Peak memory 209388 kb
Host smart-c9844baa-60c6-49c9-85c6-4893cca01ea8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111336900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2111336900
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.521022604
Short name T974
Test name
Test status
Simulation time 517535123 ps
CPU time 1.81 seconds
Started May 28 01:43:03 PM PDT 24
Finished May 28 01:43:06 PM PDT 24
Peak memory 210948 kb
Host smart-bf9fa88f-af5f-4459-8d4c-7540d06e17f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521022604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.521022604
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143859428
Short name T939
Test name
Test status
Simulation time 260226133 ps
CPU time 4.08 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 219324 kb
Host smart-9f88b8f9-4ee4-4a6f-8eca-4cb5b8d76948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114385
9428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143859428
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.115902601
Short name T879
Test name
Test status
Simulation time 1129311524 ps
CPU time 1.21 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 209380 kb
Host smart-b9716e92-7229-41db-b9eb-64c77cad7c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115902601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.115902601
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.936289338
Short name T202
Test name
Test status
Simulation time 247794452 ps
CPU time 1.19 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 209248 kb
Host smart-103a6e66-b6b8-4065-95eb-87737a6bc11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936289338 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.936289338
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3644739204
Short name T898
Test name
Test status
Simulation time 33014963 ps
CPU time 1.2 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 211380 kb
Host smart-41e8b586-080d-48c1-8f6c-751c12b704fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644739204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3644739204
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1474684820
Short name T954
Test name
Test status
Simulation time 143703225 ps
CPU time 2.43 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:14 PM PDT 24
Peak memory 217720 kb
Host smart-90fb8d9d-9b16-43dd-842f-9388e5c3eb88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474684820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1474684820
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1236514252
Short name T125
Test name
Test status
Simulation time 234688177 ps
CPU time 2.01 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 212608 kb
Host smart-34eb9081-57c0-4984-b099-c1b498073de5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236514252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1236514252
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4195765857
Short name T915
Test name
Test status
Simulation time 72403338 ps
CPU time 1.01 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 218864 kb
Host smart-2c21899b-b7ec-4266-8615-67846ee5436f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195765857 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4195765857
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3289996130
Short name T971
Test name
Test status
Simulation time 15388673 ps
CPU time 1.06 seconds
Started May 28 01:43:03 PM PDT 24
Finished May 28 01:43:05 PM PDT 24
Peak memory 209392 kb
Host smart-5fab0ad0-42fb-4d0d-97ca-1f204d84f17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289996130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3289996130
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.202893436
Short name T891
Test name
Test status
Simulation time 56188332 ps
CPU time 1.3 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 207968 kb
Host smart-70b58e91-2f3a-4d52-a7b8-e72d1370d1e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202893436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.202893436
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3834838088
Short name T913
Test name
Test status
Simulation time 256924576 ps
CPU time 6.39 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:16 PM PDT 24
Peak memory 209196 kb
Host smart-5f7dc39c-1f62-489a-b80f-d1e90725b0b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834838088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3834838088
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3728403146
Short name T991
Test name
Test status
Simulation time 478596241 ps
CPU time 5.55 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 209184 kb
Host smart-73fbf997-7638-47c6-a3ec-a4a99c15b216
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728403146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3728403146
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2041891642
Short name T968
Test name
Test status
Simulation time 115447153 ps
CPU time 2.1 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:08 PM PDT 24
Peak memory 210864 kb
Host smart-eea09d72-74da-4cf2-8dc1-3401acf66514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041891642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2041891642
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3153432072
Short name T986
Test name
Test status
Simulation time 126152144 ps
CPU time 3.36 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:16 PM PDT 24
Peak memory 217536 kb
Host smart-978ef579-3857-4536-9b01-5bef180215df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315343
2072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3153432072
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3564273996
Short name T925
Test name
Test status
Simulation time 335398525 ps
CPU time 2.68 seconds
Started May 28 01:43:03 PM PDT 24
Finished May 28 01:43:07 PM PDT 24
Peak memory 209376 kb
Host smart-54e11033-d8cb-4aea-9890-c2bc4154f18a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564273996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3564273996
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3676135954
Short name T923
Test name
Test status
Simulation time 49603719 ps
CPU time 1.88 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 211428 kb
Host smart-0deb775a-32af-4d75-9935-7f73891c8ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676135954 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3676135954
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4222426216
Short name T976
Test name
Test status
Simulation time 41676172 ps
CPU time 0.97 seconds
Started May 28 01:43:03 PM PDT 24
Finished May 28 01:43:05 PM PDT 24
Peak memory 209460 kb
Host smart-4c47c717-4718-4ad6-9724-ae7e114af52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222426216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4222426216
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.688451374
Short name T943
Test name
Test status
Simulation time 72318805 ps
CPU time 2.99 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 217760 kb
Host smart-3047e485-c1bd-4209-8576-77d3f54e9d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688451374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.688451374
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1568090408
Short name T909
Test name
Test status
Simulation time 58131086 ps
CPU time 2.18 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:12 PM PDT 24
Peak memory 219824 kb
Host smart-214abb89-7816-4ce7-8a5d-33371693b482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568090408 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1568090408
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1408445774
Short name T875
Test name
Test status
Simulation time 141942354 ps
CPU time 0.85 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:06 PM PDT 24
Peak memory 209392 kb
Host smart-2c1e401d-8f73-458e-b085-27b2f42f585d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408445774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1408445774
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1784875769
Short name T924
Test name
Test status
Simulation time 32584587 ps
CPU time 1.54 seconds
Started May 28 01:43:02 PM PDT 24
Finished May 28 01:43:04 PM PDT 24
Peak memory 208092 kb
Host smart-cd1219cc-23e7-49f4-aeda-5e851571c188
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784875769 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1784875769
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.448163798
Short name T990
Test name
Test status
Simulation time 1115697297 ps
CPU time 3 seconds
Started May 28 01:43:03 PM PDT 24
Finished May 28 01:43:07 PM PDT 24
Peak memory 209176 kb
Host smart-3bc4e22f-8bd2-4230-b364-125d67fa3e27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448163798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.448163798
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2733023863
Short name T921
Test name
Test status
Simulation time 2678992136 ps
CPU time 29.3 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:40 PM PDT 24
Peak memory 209408 kb
Host smart-010df047-5570-40b7-8cb5-184f54d8c82f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733023863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2733023863
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4029719573
Short name T944
Test name
Test status
Simulation time 148064199 ps
CPU time 2.34 seconds
Started May 28 01:43:04 PM PDT 24
Finished May 28 01:43:09 PM PDT 24
Peak memory 210808 kb
Host smart-dc595468-1895-46cf-ba46-815e52ad703e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029719573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.4029719573
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.343346015
Short name T928
Test name
Test status
Simulation time 359007352 ps
CPU time 3.32 seconds
Started May 28 01:43:07 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 217840 kb
Host smart-3f7da253-5f37-4031-b0d7-f5f3c0393aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343346
015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.343346015
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.295151987
Short name T917
Test name
Test status
Simulation time 113317032 ps
CPU time 1.59 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 209344 kb
Host smart-8d0150d2-76da-4828-a1f1-6d6b0d733cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295151987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.295151987
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.98016390
Short name T206
Test name
Test status
Simulation time 53132306 ps
CPU time 1.14 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:11 PM PDT 24
Peak memory 209584 kb
Host smart-6e2444cb-9864-4468-99c9-9aec54fd4c9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98016390 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.98016390
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4289991259
Short name T903
Test name
Test status
Simulation time 29549257 ps
CPU time 1.16 seconds
Started May 28 01:43:05 PM PDT 24
Finished May 28 01:43:10 PM PDT 24
Peak memory 209456 kb
Host smart-819a86d3-79f9-409a-a75f-c44563414577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289991259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4289991259
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1811908260
Short name T957
Test name
Test status
Simulation time 39065498 ps
CPU time 2.32 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:13 PM PDT 24
Peak memory 218812 kb
Host smart-9c83d063-b592-41c1-b8a9-b88eca26f38e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811908260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1811908260
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.840967532
Short name T132
Test name
Test status
Simulation time 128371089 ps
CPU time 4.44 seconds
Started May 28 01:43:06 PM PDT 24
Finished May 28 01:43:15 PM PDT 24
Peak memory 217664 kb
Host smart-aa933b9b-2446-4b3a-9055-bb5667b0b867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840967532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.840967532
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3116448642
Short name T78
Test name
Test status
Simulation time 36384689 ps
CPU time 0.95 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 209648 kb
Host smart-72b73a36-d682-4ebe-beb1-cc562a7a47bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116448642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3116448642
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3230049614
Short name T667
Test name
Test status
Simulation time 24842513 ps
CPU time 0.84 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 209548 kb
Host smart-a8ab3979-230c-4697-8cf4-65d1fc1f63ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230049614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3230049614
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.792131414
Short name T33
Test name
Test status
Simulation time 1058685924 ps
CPU time 4 seconds
Started May 28 02:48:59 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 217044 kb
Host smart-01ade21b-fe91-4f2c-bee0-d30b44f4941d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792131414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.792131414
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3944404544
Short name T864
Test name
Test status
Simulation time 2839510609 ps
CPU time 80.71 seconds
Started May 28 02:48:57 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 219032 kb
Host smart-7c3e7272-fb09-468f-b62a-8ba3958b700c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944404544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3944404544
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2853612745
Short name T862
Test name
Test status
Simulation time 147398449 ps
CPU time 2.72 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:06 PM PDT 24
Peak memory 217336 kb
Host smart-45292296-3800-4c85-a93a-9042d1d4621c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853612745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
853612745
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.338232386
Short name T227
Test name
Test status
Simulation time 635141253 ps
CPU time 5.92 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:10 PM PDT 24
Peak memory 218048 kb
Host smart-9c0f506f-16f5-4c7a-9272-d245c47f3974
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338232386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.338232386
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.887570663
Short name T701
Test name
Test status
Simulation time 1021556310 ps
CPU time 15.39 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 213180 kb
Host smart-148c1d3a-1876-48bc-8134-4a1e53b2f379
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887570663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.887570663
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1153191943
Short name T400
Test name
Test status
Simulation time 111827744 ps
CPU time 2.33 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 213088 kb
Host smart-616715a8-24a5-4fe6-ac4b-834b58a22914
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153191943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1153191943
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1592419200
Short name T641
Test name
Test status
Simulation time 5225379514 ps
CPU time 40.3 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 275648 kb
Host smart-54881145-3940-46db-b49c-2f5013e6b87e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592419200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1592419200
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.43255782
Short name T333
Test name
Test status
Simulation time 269440475 ps
CPU time 13.11 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 250636 kb
Host smart-dfcc5a0d-fb69-4345-9e01-ffbbbeca3f55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43255782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_state_post_trans.43255782
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2228394043
Short name T382
Test name
Test status
Simulation time 53850450 ps
CPU time 2.51 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 218136 kb
Host smart-f6ff8c00-eef8-4eb9-8967-877bdb6feed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228394043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2228394043
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3004956622
Short name T185
Test name
Test status
Simulation time 396671406 ps
CPU time 10.72 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:10 PM PDT 24
Peak memory 214324 kb
Host smart-df6936f7-a029-4c6d-827f-d1729a7fe73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004956622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3004956622
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2217467670
Short name T60
Test name
Test status
Simulation time 420641909 ps
CPU time 24.26 seconds
Started May 28 02:48:58 PM PDT 24
Finished May 28 02:49:31 PM PDT 24
Peak memory 281652 kb
Host smart-ba18fb72-faa1-4933-bb4f-ac81a4f039c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217467670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2217467670
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1687119123
Short name T253
Test name
Test status
Simulation time 708277424 ps
CPU time 10.53 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 218020 kb
Host smart-1ff6846b-d16e-4f4b-bc1a-0c0f881f7720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687119123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1687119123
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1943516946
Short name T618
Test name
Test status
Simulation time 745302417 ps
CPU time 6.29 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:07 PM PDT 24
Peak memory 218056 kb
Host smart-6fb9c836-683e-4378-a1c9-d493399f5f73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943516946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
943516946
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1144104749
Short name T736
Test name
Test status
Simulation time 44948111 ps
CPU time 3.34 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:06 PM PDT 24
Peak memory 213572 kb
Host smart-5f2096b3-0a2b-4fd9-a6ca-981921cc3e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144104749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1144104749
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3962191525
Short name T490
Test name
Test status
Simulation time 192458056 ps
CPU time 18.44 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:20 PM PDT 24
Peak memory 250804 kb
Host smart-cad39aca-f859-4ac0-adc2-dc1e8d610059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962191525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3962191525
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3933653780
Short name T498
Test name
Test status
Simulation time 87778769 ps
CPU time 10.02 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:12 PM PDT 24
Peak memory 250948 kb
Host smart-273a1d79-0530-4f4d-9af1-5ee2cceb6d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933653780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3933653780
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.680618592
Short name T170
Test name
Test status
Simulation time 9659831883 ps
CPU time 312.26 seconds
Started May 28 02:49:00 PM PDT 24
Finished May 28 02:54:22 PM PDT 24
Peak memory 224104 kb
Host smart-edc29f2f-9a39-4434-827e-930ba03cbffa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680618592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.680618592
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3878296662
Short name T548
Test name
Test status
Simulation time 57152528 ps
CPU time 0.9 seconds
Started May 28 02:49:00 PM PDT 24
Finished May 28 02:49:11 PM PDT 24
Peak memory 208640 kb
Host smart-fb8d9265-dc71-46f7-b066-95164888707c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878296662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3878296662
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2737257588
Short name T294
Test name
Test status
Simulation time 57967130 ps
CPU time 1.04 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 209608 kb
Host smart-39492f01-95ed-43aa-a816-06cbfc4e82f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737257588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2737257588
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4075994460
Short name T734
Test name
Test status
Simulation time 3104780981 ps
CPU time 15.31 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 219108 kb
Host smart-89271f63-5d55-4669-a0e3-7f3dfed1ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075994460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4075994460
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.116906304
Short name T806
Test name
Test status
Simulation time 1300135125 ps
CPU time 7.17 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:21 PM PDT 24
Peak memory 209600 kb
Host smart-7ad0b7c9-90fd-4551-9958-f158cacfd53b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116906304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.116906304
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3015478169
Short name T512
Test name
Test status
Simulation time 6492555921 ps
CPU time 46.62 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 218592 kb
Host smart-e2a863db-1e91-4b52-b1d5-4fe2a989aa74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015478169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3015478169
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2859227195
Short name T357
Test name
Test status
Simulation time 457866757 ps
CPU time 11.34 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 217880 kb
Host smart-52b117e2-63da-4ea4-9bbc-be807ba2fe8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859227195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
859227195
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1102530589
Short name T793
Test name
Test status
Simulation time 96927326 ps
CPU time 2.49 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 218072 kb
Host smart-ba0e93f3-91d6-46e0-b1f9-a569128827b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102530589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1102530589
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1348694207
Short name T79
Test name
Test status
Simulation time 13860905962 ps
CPU time 16.49 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:31 PM PDT 24
Peak memory 213912 kb
Host smart-48b4aac8-51c7-4361-b833-a366ec546829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348694207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1348694207
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3303690260
Short name T788
Test name
Test status
Simulation time 3151151166 ps
CPU time 14.05 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 214328 kb
Host smart-d187160e-1942-4fbb-a13c-428c0c3d777e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303690260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3303690260
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.411379889
Short name T244
Test name
Test status
Simulation time 2582622500 ps
CPU time 47.2 seconds
Started May 28 02:49:01 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 275580 kb
Host smart-c1d988dd-5263-458b-be6a-a34def95821b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411379889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.411379889
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.857971465
Short name T241
Test name
Test status
Simulation time 1885142550 ps
CPU time 12.66 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:27 PM PDT 24
Peak memory 250952 kb
Host smart-80cd7985-2c8c-431c-a67d-ac7ce6dcc10c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857971465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.857971465
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2802555564
Short name T16
Test name
Test status
Simulation time 47709830 ps
CPU time 2.74 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 218104 kb
Host smart-34ca8e48-2bae-4ff9-bf28-bfbd78e60a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802555564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2802555564
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.276351744
Short name T842
Test name
Test status
Simulation time 395583612 ps
CPU time 15.86 seconds
Started May 28 02:49:01 PM PDT 24
Finished May 28 02:49:27 PM PDT 24
Peak memory 214648 kb
Host smart-e241a2c8-cae2-41d7-9391-83785cb092ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276351744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.276351744
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2291127053
Short name T94
Test name
Test status
Simulation time 235758282 ps
CPU time 20.99 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 284080 kb
Host smart-c472c7ff-ebe8-4229-ad22-4c8ff1c4162f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291127053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2291127053
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2456804729
Short name T844
Test name
Test status
Simulation time 1503243435 ps
CPU time 9.77 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 219020 kb
Host smart-ea82de3e-e2cd-4fed-bb8e-5ed8a9e79d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456804729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2456804729
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2060892431
Short name T154
Test name
Test status
Simulation time 285442121 ps
CPU time 9.95 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 218048 kb
Host smart-42cc0fb9-2144-46d7-9e08-62fc3e76d72d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060892431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2060892431
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.113225319
Short name T723
Test name
Test status
Simulation time 266715674 ps
CPU time 10.12 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 218028 kb
Host smart-1e32ee6f-cd68-4fe0-922f-6e4c1ee0014b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113225319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.113225319
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3272707396
Short name T470
Test name
Test status
Simulation time 3984886693 ps
CPU time 14.16 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 218296 kb
Host smart-e36ab8ca-0df9-466e-9aef-250708e80265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272707396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3272707396
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2499256574
Short name T766
Test name
Test status
Simulation time 34586686 ps
CPU time 1.5 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 217808 kb
Host smart-823c9f1a-7c74-4670-bed8-c63cffa6a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499256574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2499256574
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2371869586
Short name T108
Test name
Test status
Simulation time 1251946411 ps
CPU time 26.99 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:31 PM PDT 24
Peak memory 250984 kb
Host smart-d5545d65-404f-4b11-993a-a58c079c313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371869586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2371869586
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.693889086
Short name T23
Test name
Test status
Simulation time 105440381 ps
CPU time 2.74 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 222672 kb
Host smart-0f680b82-a206-4b67-a0c7-2bc0c03ef058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693889086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.693889086
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3724620476
Short name T72
Test name
Test status
Simulation time 5851109772 ps
CPU time 197.65 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:52:32 PM PDT 24
Peak memory 283824 kb
Host smart-ec037699-9ac0-43c4-a17a-844323de9025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724620476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3724620476
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1317485897
Short name T786
Test name
Test status
Simulation time 13540736 ps
CPU time 0.82 seconds
Started May 28 02:48:57 PM PDT 24
Finished May 28 02:49:07 PM PDT 24
Peak memory 208436 kb
Host smart-66bcad6e-ebb0-4b0a-86aa-4bfcb8c8af9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317485897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1317485897
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1878302042
Short name T366
Test name
Test status
Simulation time 22143071 ps
CPU time 1.25 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 209644 kb
Host smart-2381f21a-8b9c-45f6-8de3-8a215f2a2e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878302042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1878302042
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3565429375
Short name T34
Test name
Test status
Simulation time 1690716126 ps
CPU time 5.64 seconds
Started May 28 02:49:51 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 209632 kb
Host smart-c3c2fab7-ed7c-460c-876a-87f3a6960084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565429375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3565429375
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3884768916
Short name T785
Test name
Test status
Simulation time 4086513148 ps
CPU time 51.64 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:50:30 PM PDT 24
Peak memory 218376 kb
Host smart-49626c7a-5433-4985-a2a3-b899c460ca3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884768916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3884768916
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1341179300
Short name T811
Test name
Test status
Simulation time 1031762981 ps
CPU time 7.64 seconds
Started May 28 02:49:39 PM PDT 24
Finished May 28 02:49:50 PM PDT 24
Peak memory 218008 kb
Host smart-dfbf4f2b-f78e-413a-8fd1-1a882fe084fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341179300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1341179300
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3033749392
Short name T528
Test name
Test status
Simulation time 4646857131 ps
CPU time 7.62 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:44 PM PDT 24
Peak memory 214360 kb
Host smart-6ddfac8f-1587-473f-b55b-0eb1304601ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033749392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3033749392
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3147072846
Short name T457
Test name
Test status
Simulation time 2731795436 ps
CPU time 61.81 seconds
Started May 28 02:50:11 PM PDT 24
Finished May 28 02:51:14 PM PDT 24
Peak memory 278756 kb
Host smart-5a4854d2-121d-483d-98a5-3bb7b9c30e4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147072846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3147072846
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.426643090
Short name T417
Test name
Test status
Simulation time 990767651 ps
CPU time 5.81 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:44 PM PDT 24
Peak memory 217968 kb
Host smart-0fe7dccd-9f00-454d-b53a-86aa0c659a7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426643090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.426643090
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.138726009
Short name T810
Test name
Test status
Simulation time 59080487 ps
CPU time 2.09 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 218072 kb
Host smart-d8fd7b07-bf0a-4945-ab57-7d4fcd93a9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138726009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.138726009
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.965714381
Short name T233
Test name
Test status
Simulation time 3399476037 ps
CPU time 17.12 seconds
Started May 28 02:49:37 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 226204 kb
Host smart-9c1a7e97-f901-4fec-af3c-9813f06e7fcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965714381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.965714381
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3528065773
Short name T421
Test name
Test status
Simulation time 1066403546 ps
CPU time 11.96 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 218088 kb
Host smart-cdfc8a7c-c559-4b3e-afb2-bd12e3d26ff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528065773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3528065773
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.141477381
Short name T415
Test name
Test status
Simulation time 1934505697 ps
CPU time 9.03 seconds
Started May 28 02:50:09 PM PDT 24
Finished May 28 02:50:19 PM PDT 24
Peak memory 218064 kb
Host smart-90f3f882-06e4-400b-82d3-3113e2eb3561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141477381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.141477381
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2028117705
Short name T514
Test name
Test status
Simulation time 351865614 ps
CPU time 11.78 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218184 kb
Host smart-1d9a1a37-3636-4743-8a32-a1674f6f82af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028117705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2028117705
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.173837023
Short name T542
Test name
Test status
Simulation time 103033847 ps
CPU time 2.25 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:49:43 PM PDT 24
Peak memory 213652 kb
Host smart-c7d56b12-5cc6-470d-9595-43ddcbe8a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173837023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.173837023
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.957616690
Short name T832
Test name
Test status
Simulation time 499368334 ps
CPU time 25.83 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:50:03 PM PDT 24
Peak memory 251044 kb
Host smart-d65afff9-30af-4c18-93dc-cfb44d5d336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957616690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.957616690
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3480621515
Short name T529
Test name
Test status
Simulation time 106038742 ps
CPU time 7.76 seconds
Started May 28 02:49:34 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 250980 kb
Host smart-973f1c17-f4fa-4d6f-8cec-7ca7da85672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480621515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3480621515
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2042442900
Short name T608
Test name
Test status
Simulation time 5064365736 ps
CPU time 161.7 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:52:23 PM PDT 24
Peak memory 271856 kb
Host smart-b6b0cab5-a998-4d7e-bf89-33c2032812e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042442900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2042442900
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3845398621
Short name T617
Test name
Test status
Simulation time 17549070272 ps
CPU time 449.91 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:57:10 PM PDT 24
Peak memory 333136 kb
Host smart-de8fa76b-2ff2-4cc4-879e-629d0e5f7a3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3845398621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3845398621
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1758325145
Short name T47
Test name
Test status
Simulation time 11996772 ps
CPU time 0.99 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 208820 kb
Host smart-647e0e5c-24ea-4d10-9318-b5c750e187dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758325145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1758325145
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.89162173
Short name T754
Test name
Test status
Simulation time 20959509 ps
CPU time 1.18 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 209676 kb
Host smart-8c75a8dc-8e2c-4b71-b965-a9dd6ff56306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89162173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.89162173
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2127151346
Short name T596
Test name
Test status
Simulation time 1691125976 ps
CPU time 13.49 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 217988 kb
Host smart-b5a84308-5446-443d-997b-a842a5948658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127151346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2127151346
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3698467398
Short name T768
Test name
Test status
Simulation time 283529596 ps
CPU time 2.23 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 209596 kb
Host smart-9fe274d2-ee8a-4a1a-81ae-e337f0dd48f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698467398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3698467398
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2826869515
Short name T773
Test name
Test status
Simulation time 1514678225 ps
CPU time 41.94 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 217888 kb
Host smart-569da242-e287-4aa0-b287-519bdd4bada8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826869515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2826869515
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1733935883
Short name T7
Test name
Test status
Simulation time 636805789 ps
CPU time 10.71 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:49:52 PM PDT 24
Peak memory 218040 kb
Host smart-c3c70242-8df7-41c3-89c4-c882e95a1e2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733935883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1733935883
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4096307593
Short name T278
Test name
Test status
Simulation time 183695752 ps
CPU time 1.32 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 212612 kb
Host smart-cdb691e4-62e0-40a5-b889-01850876bf6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096307593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4096307593
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3026945455
Short name T282
Test name
Test status
Simulation time 11412162354 ps
CPU time 52.59 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 283760 kb
Host smart-6b576581-277e-4ada-aba2-fff1ac8f4137
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026945455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3026945455
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3768066918
Short name T152
Test name
Test status
Simulation time 1422312910 ps
CPU time 11.39 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:49 PM PDT 24
Peak memory 250948 kb
Host smart-a3f2db5a-5be1-4b1d-a267-59ef3018b7b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768066918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3768066918
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3510070078
Short name T301
Test name
Test status
Simulation time 65595125 ps
CPU time 3.41 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:49:44 PM PDT 24
Peak memory 217924 kb
Host smart-31ea1ce2-10d2-4634-af41-219425f4adda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510070078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3510070078
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.73438810
Short name T653
Test name
Test status
Simulation time 278798886 ps
CPU time 9.33 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 226008 kb
Host smart-13a4f0a8-e387-4e90-9e5f-5c2990176dba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73438810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.73438810
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2594632636
Short name T661
Test name
Test status
Simulation time 1040293276 ps
CPU time 8.95 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:44 PM PDT 24
Peak memory 218052 kb
Host smart-48ebcd89-56de-4b67-afc5-13668815da26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594632636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2594632636
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.32745149
Short name T787
Test name
Test status
Simulation time 4085666182 ps
CPU time 14.1 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:52 PM PDT 24
Peak memory 218120 kb
Host smart-dabe4762-5d3c-4455-be93-a9914845afbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32745149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.32745149
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1037217995
Short name T213
Test name
Test status
Simulation time 431768337 ps
CPU time 9.36 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 218164 kb
Host smart-9e68de6f-ba1d-41bc-aa7a-d26f16c25093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037217995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1037217995
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.404739762
Short name T104
Test name
Test status
Simulation time 67368141 ps
CPU time 3.48 seconds
Started May 28 02:49:38 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 217792 kb
Host smart-72048b42-a3e5-400b-9df7-c870a3318c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404739762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.404739762
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3517090721
Short name T228
Test name
Test status
Simulation time 168720645 ps
CPU time 22.25 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:15 PM PDT 24
Peak memory 251028 kb
Host smart-b73580be-341c-42aa-83f7-752f2c7dba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517090721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3517090721
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3187199666
Short name T852
Test name
Test status
Simulation time 192761672 ps
CPU time 4.73 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 218016 kb
Host smart-60d8738b-1e0c-4123-9b74-235b3de745cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187199666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3187199666
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3204510009
Short name T570
Test name
Test status
Simulation time 7543058485 ps
CPU time 101.58 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:51:29 PM PDT 24
Peak memory 272204 kb
Host smart-0df30d67-b861-44ab-a2e9-4e038894473d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204510009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3204510009
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1001017106
Short name T49
Test name
Test status
Simulation time 34549758 ps
CPU time 0.99 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:49:52 PM PDT 24
Peak memory 211640 kb
Host smart-eccefc88-90f6-4888-8944-b1a3af989e97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001017106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1001017106
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3590629629
Short name T167
Test name
Test status
Simulation time 100515272 ps
CPU time 1.27 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:49:52 PM PDT 24
Peak memory 209504 kb
Host smart-77d7970f-1543-420f-8bb4-ee5bb4733c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590629629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3590629629
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.733791635
Short name T559
Test name
Test status
Simulation time 1206476384 ps
CPU time 12.07 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 218160 kb
Host smart-fb2c6693-9881-43a1-ae39-c7dfdb1abd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733791635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.733791635
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2419747918
Short name T709
Test name
Test status
Simulation time 157982171 ps
CPU time 4.47 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 209596 kb
Host smart-707c7909-9e6d-437f-ab31-812c1d7972f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419747918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2419747918
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2038007435
Short name T639
Test name
Test status
Simulation time 5466715559 ps
CPU time 28.6 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:19 PM PDT 24
Peak memory 219076 kb
Host smart-c0d930fb-b345-4474-9e41-0175b9f6f6df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038007435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2038007435
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1232157722
Short name T614
Test name
Test status
Simulation time 2182843547 ps
CPU time 29.56 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 218084 kb
Host smart-7aab1f03-30e8-48de-860c-243411e0895d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232157722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1232157722
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1757192802
Short name T388
Test name
Test status
Simulation time 1402809247 ps
CPU time 6.32 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 213788 kb
Host smart-9f869873-1f3d-4b33-88e4-ed2584250cfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757192802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1757192802
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.828114358
Short name T437
Test name
Test status
Simulation time 858927260 ps
CPU time 45.46 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 250964 kb
Host smart-251b59b9-5a5e-42c3-9479-67954ab28103
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828114358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.828114358
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1985917026
Short name T825
Test name
Test status
Simulation time 1176855913 ps
CPU time 10.13 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 250524 kb
Host smart-b29a2db6-b3f2-4f5b-8b67-d6d5487ec116
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985917026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1985917026
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1719517444
Short name T485
Test name
Test status
Simulation time 126188836 ps
CPU time 1.77 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218036 kb
Host smart-4430dfdd-0c13-4e3d-b604-11d8e63c70fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719517444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1719517444
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.667708367
Short name T292
Test name
Test status
Simulation time 856600787 ps
CPU time 24.25 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:14 PM PDT 24
Peak memory 226224 kb
Host smart-3af76904-da99-4745-b4bd-f440c77d5721
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667708367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.667708367
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1793591985
Short name T247
Test name
Test status
Simulation time 243286160 ps
CPU time 11.67 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:03 PM PDT 24
Peak memory 218016 kb
Host smart-4004b1fa-45fd-404d-9386-600f3c555bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793591985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1793591985
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1333443403
Short name T670
Test name
Test status
Simulation time 517593785 ps
CPU time 11.21 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 218120 kb
Host smart-777c3882-736b-4821-ba7a-4e43c742f7f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333443403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1333443403
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.507006279
Short name T456
Test name
Test status
Simulation time 802432785 ps
CPU time 10.28 seconds
Started May 28 02:49:39 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 218152 kb
Host smart-bb63ef65-b825-4f0d-85ac-1118d30172f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507006279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.507006279
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2444293726
Short name T837
Test name
Test status
Simulation time 564149281 ps
CPU time 4.47 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:50 PM PDT 24
Peak memory 218012 kb
Host smart-ae886f87-87f1-48a3-b5e7-671f3c95713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444293726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2444293726
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2576762117
Short name T261
Test name
Test status
Simulation time 354163663 ps
CPU time 37.08 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:50:25 PM PDT 24
Peak memory 250972 kb
Host smart-81680ea9-38e2-4c49-8545-1327982ee012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576762117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2576762117
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3277201369
Short name T391
Test name
Test status
Simulation time 478180032 ps
CPU time 8.32 seconds
Started May 28 02:49:41 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 251020 kb
Host smart-1433912e-1895-47bc-aefb-a0be85462024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277201369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3277201369
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.916414115
Short name T116
Test name
Test status
Simulation time 43217722726 ps
CPU time 1286.4 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 03:11:17 PM PDT 24
Peak memory 292664 kb
Host smart-5785ea8a-a918-4325-9c35-8119c15e0ac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=916414115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.916414115
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3532237856
Short name T510
Test name
Test status
Simulation time 61172818 ps
CPU time 0.79 seconds
Started May 28 02:49:40 PM PDT 24
Finished May 28 02:49:45 PM PDT 24
Peak memory 208708 kb
Host smart-f9e2cc53-5c66-4e05-bd8d-f990774676d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532237856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3532237856
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2304938336
Short name T697
Test name
Test status
Simulation time 245532600 ps
CPU time 0.9 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 209620 kb
Host smart-014a89df-da71-43c7-9aac-1f960577b12d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304938336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2304938336
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1235969196
Short name T745
Test name
Test status
Simulation time 294536891 ps
CPU time 12.79 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 218104 kb
Host smart-55ea7f17-31bc-472f-bcf8-ae92f673e55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235969196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1235969196
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2995206491
Short name T394
Test name
Test status
Simulation time 1347984699 ps
CPU time 11.83 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 209632 kb
Host smart-2b71457a-c87a-4c99-9574-7d58ad6170fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995206491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2995206491
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.580221362
Short name T268
Test name
Test status
Simulation time 4899746149 ps
CPU time 60.75 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 219524 kb
Host smart-0612219a-6a29-4bbe-919e-797899cd6cc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580221362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.580221362
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2150934810
Short name T815
Test name
Test status
Simulation time 346416557 ps
CPU time 10.5 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 218108 kb
Host smart-9bfd609d-a055-43c5-a68e-240a14d0cb78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150934810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2150934810
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.63318547
Short name T744
Test name
Test status
Simulation time 776066098 ps
CPU time 2.65 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 212928 kb
Host smart-2c651ed6-6c4e-4ca4-8556-44347e839fe3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63318547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.63318547
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2115489305
Short name T501
Test name
Test status
Simulation time 6496629833 ps
CPU time 67.36 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:59 PM PDT 24
Peak memory 251068 kb
Host smart-13b9ef75-6cf0-43b9-a53c-2c419669b680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115489305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2115489305
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1488631375
Short name T281
Test name
Test status
Simulation time 547963094 ps
CPU time 13.74 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 250956 kb
Host smart-1ec3112a-8cfb-40af-ae02-622fc95f520a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488631375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1488631375
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3963128750
Short name T405
Test name
Test status
Simulation time 155284526 ps
CPU time 3.12 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:49:55 PM PDT 24
Peak memory 218104 kb
Host smart-9845eda1-6e5a-42e4-af4f-6cc2eec0c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963128750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3963128750
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3172653335
Short name T214
Test name
Test status
Simulation time 1388267332 ps
CPU time 12.95 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 226192 kb
Host smart-b124147e-442c-418d-b99c-00d8ad4e81dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172653335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3172653335
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2534810532
Short name T797
Test name
Test status
Simulation time 582275204 ps
CPU time 12.98 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 218040 kb
Host smart-d43cc0a6-37a6-4959-a1c7-987dc6b2ddbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534810532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2534810532
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.949999399
Short name T482
Test name
Test status
Simulation time 215769924 ps
CPU time 6.33 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 218112 kb
Host smart-ad73a515-84ff-4ad7-88c3-31cc7b6c39e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949999399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.949999399
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3966944394
Short name T707
Test name
Test status
Simulation time 305650964 ps
CPU time 6.76 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 218156 kb
Host smart-840b4938-251c-4cce-82e1-28170dd0eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966944394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3966944394
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2085753881
Short name T582
Test name
Test status
Simulation time 529424358 ps
CPU time 4.15 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 214084 kb
Host smart-549aaee4-8bc4-471d-8887-0bdd688ef8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085753881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2085753881
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.905026777
Short name T553
Test name
Test status
Simulation time 4424584586 ps
CPU time 19.52 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:11 PM PDT 24
Peak memory 251084 kb
Host smart-bc18cb98-73b2-4bd6-a775-852548a0f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905026777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.905026777
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.888362634
Short name T280
Test name
Test status
Simulation time 95327332 ps
CPU time 9.01 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 250956 kb
Host smart-15df048f-3f30-4925-a558-735c772df435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888362634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.888362634
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2540152905
Short name T169
Test name
Test status
Simulation time 66634341682 ps
CPU time 1202.52 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 03:09:54 PM PDT 24
Peak memory 529124 kb
Host smart-d9686c0a-f8da-42ba-b039-ba31beed9241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2540152905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2540152905
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.979417721
Short name T625
Test name
Test status
Simulation time 25218519 ps
CPU time 0.94 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 211576 kb
Host smart-53038246-9d72-4299-8804-2d2ca950c88e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979417721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.979417721
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1169169490
Short name T429
Test name
Test status
Simulation time 71082259 ps
CPU time 0.9 seconds
Started May 28 02:50:10 PM PDT 24
Finished May 28 02:50:12 PM PDT 24
Peak memory 209720 kb
Host smart-8ee6e58b-388c-40fc-b56e-81afec29d2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169169490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1169169490
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.340604381
Short name T523
Test name
Test status
Simulation time 426206829 ps
CPU time 18.14 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:50:12 PM PDT 24
Peak memory 218196 kb
Host smart-5051c040-2923-454b-89f4-0de9e2481efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340604381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.340604381
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3919195853
Short name T352
Test name
Test status
Simulation time 485268866 ps
CPU time 2.31 seconds
Started May 28 02:50:05 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 209928 kb
Host smart-204d8454-36eb-4488-be30-ec3312392429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919195853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3919195853
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.572692039
Short name T177
Test name
Test status
Simulation time 2242045508 ps
CPU time 31.98 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 218132 kb
Host smart-c13c79ab-ecc7-4ed1-9f80-f341fe81a92d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572692039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.572692039
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1418390886
Short name T831
Test name
Test status
Simulation time 1063244175 ps
CPU time 12.09 seconds
Started May 28 02:50:10 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 218064 kb
Host smart-729861db-f4bb-4e59-ba33-6dab50a53536
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418390886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1418390886
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1524358063
Short name T568
Test name
Test status
Simulation time 1744617697 ps
CPU time 10.45 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:03 PM PDT 24
Peak memory 213788 kb
Host smart-293a54ec-c58c-4eff-a6ad-74accbcb337b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524358063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1524358063
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.824824552
Short name T763
Test name
Test status
Simulation time 1880578954 ps
CPU time 75.65 seconds
Started May 28 02:50:08 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 283824 kb
Host smart-60d2f5d4-4b18-4706-acf8-fdb9a1fcfa4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824824552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.824824552
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1881362561
Short name T307
Test name
Test status
Simulation time 692193625 ps
CPU time 16.42 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:50:10 PM PDT 24
Peak memory 250928 kb
Host smart-a67a10ee-fbf8-4bd1-b4cc-ed057f90e3df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881362561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1881362561
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.540392707
Short name T746
Test name
Test status
Simulation time 82120873 ps
CPU time 3.96 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:49:57 PM PDT 24
Peak memory 218100 kb
Host smart-406df0db-5032-4b50-affc-46c03148aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540392707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.540392707
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2467337432
Short name T526
Test name
Test status
Simulation time 289906618 ps
CPU time 9.4 seconds
Started May 28 02:50:05 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 219248 kb
Host smart-c6029849-f83a-477f-8ee8-638ae7911670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467337432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2467337432
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2397926244
Short name T696
Test name
Test status
Simulation time 2920743908 ps
CPU time 16.08 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 218080 kb
Host smart-d5f74605-3971-4841-be2f-ed95831414b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397926244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2397926244
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3810858492
Short name T863
Test name
Test status
Simulation time 1172210424 ps
CPU time 6.9 seconds
Started May 28 02:49:47 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 218084 kb
Host smart-04386d12-a9a9-4594-8898-a3f4b3597bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810858492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3810858492
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.259585664
Short name T751
Test name
Test status
Simulation time 197322790 ps
CPU time 6 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 218232 kb
Host smart-8c9b0c94-bea3-4788-a37a-6ed6f42f9f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259585664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.259585664
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2476521280
Short name T791
Test name
Test status
Simulation time 779083448 ps
CPU time 11.57 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:03 PM PDT 24
Peak memory 214832 kb
Host smart-652b7b24-0147-4d36-bbf8-83cb3bc3892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476521280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2476521280
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3832282013
Short name T432
Test name
Test status
Simulation time 198898433 ps
CPU time 25.14 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:17 PM PDT 24
Peak memory 251016 kb
Host smart-6c808e9c-0c8a-47eb-9c22-e86285571fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832282013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3832282013
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4088521449
Short name T682
Test name
Test status
Simulation time 94439243 ps
CPU time 11.47 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 251020 kb
Host smart-377fb986-97a4-4520-8fa4-a39f3f6bde78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088521449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4088521449
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.653798824
Short name T22
Test name
Test status
Simulation time 8782826416 ps
CPU time 88.07 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 271964 kb
Host smart-dd46af83-a016-4c86-85f2-4d7d0efe84f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653798824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.653798824
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.686692619
Short name T40
Test name
Test status
Simulation time 14808001 ps
CPU time 0.93 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 212672 kb
Host smart-1e0a02bf-167c-4adf-ba2a-034d4dd3874b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686692619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.686692619
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.504207426
Short name T81
Test name
Test status
Simulation time 48912173 ps
CPU time 1.03 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 209700 kb
Host smart-6a2c680d-5bb5-4877-9d42-e774cc956f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504207426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.504207426
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.649348208
Short name T441
Test name
Test status
Simulation time 369533462 ps
CPU time 12.18 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 218084 kb
Host smart-d85d568f-5ae8-4c83-a235-3b3b6a3a925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649348208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.649348208
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2255287043
Short name T849
Test name
Test status
Simulation time 1555198219 ps
CPU time 5.25 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 217200 kb
Host smart-027bf531-ee43-458e-8508-44a7dd35c0e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255287043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2255287043
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1947663959
Short name T829
Test name
Test status
Simulation time 6383123690 ps
CPU time 28.31 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:20 PM PDT 24
Peak memory 218072 kb
Host smart-dba28c2c-07d3-4796-a5d6-72185fae7588
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947663959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1947663959
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1390293429
Short name T459
Test name
Test status
Simulation time 1037355096 ps
CPU time 2.62 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 218040 kb
Host smart-dfc60020-c1cd-4b4e-bdbd-858cc60b622c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390293429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1390293429
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1010895230
Short name T86
Test name
Test status
Simulation time 496631606 ps
CPU time 4.36 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 213492 kb
Host smart-0d37cde5-3791-416d-aa8e-7c91ad448ff5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010895230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1010895230
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2812163993
Short name T531
Test name
Test status
Simulation time 5826761511 ps
CPU time 33.13 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 283724 kb
Host smart-3ba0dd9b-2b94-49f3-ae31-b6515f9157f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812163993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2812163993
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.485583858
Short name T735
Test name
Test status
Simulation time 306887440 ps
CPU time 14.31 seconds
Started May 28 02:49:42 PM PDT 24
Finished May 28 02:50:02 PM PDT 24
Peak memory 250492 kb
Host smart-07a94074-9496-4e58-b1a0-67d018171192
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485583858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.485583858
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2671569371
Short name T271
Test name
Test status
Simulation time 342080524 ps
CPU time 2.95 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 218080 kb
Host smart-f5eca297-3f04-409e-9112-ee308fa2aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671569371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2671569371
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1030348374
Short name T850
Test name
Test status
Simulation time 1627947418 ps
CPU time 13.21 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 226056 kb
Host smart-f1e7b0c5-2b25-4773-9a25-15d1545ae5f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030348374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1030348374
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1930449047
Short name T377
Test name
Test status
Simulation time 495906024 ps
CPU time 14.97 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:50:12 PM PDT 24
Peak memory 218044 kb
Host smart-9fb40d67-1e99-4f8c-bdf2-6cbbdd38fca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930449047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1930449047
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3176155491
Short name T289
Test name
Test status
Simulation time 6120787702 ps
CPU time 13.45 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:12 PM PDT 24
Peak memory 218120 kb
Host smart-aecdf1e4-70e9-416f-99f4-86431f1e06c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176155491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3176155491
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3860047650
Short name T426
Test name
Test status
Simulation time 4127544578 ps
CPU time 14.38 seconds
Started May 28 02:49:43 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 218272 kb
Host smart-6d931c66-ccaa-4ee2-9ecf-3d54d7757c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860047650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3860047650
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1952298170
Short name T355
Test name
Test status
Simulation time 323948940 ps
CPU time 4.91 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 218008 kb
Host smart-8e9ebdc8-564d-42bb-ac8f-ba2065c0fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952298170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1952298170
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1829383144
Short name T410
Test name
Test status
Simulation time 5278813981 ps
CPU time 25.79 seconds
Started May 28 02:49:44 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 251076 kb
Host smart-d3294d5b-c92a-4883-9aa2-e9b4424ff544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829383144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1829383144
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3774726149
Short name T525
Test name
Test status
Simulation time 305941220 ps
CPU time 3.02 seconds
Started May 28 02:49:46 PM PDT 24
Finished May 28 02:49:57 PM PDT 24
Peak memory 226420 kb
Host smart-d8a0ae4c-ee1d-4c78-af29-179d38e70ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774726149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3774726149
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3617088871
Short name T628
Test name
Test status
Simulation time 2089219074 ps
CPU time 39.33 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 234388 kb
Host smart-3d51fbe2-9179-4653-b8ae-f146b5e00b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617088871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3617088871
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.294750872
Short name T517
Test name
Test status
Simulation time 164148400 ps
CPU time 1 seconds
Started May 28 02:50:05 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 211840 kb
Host smart-92615d1b-916d-48f5-aaf1-affcc12c9902
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294750872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.294750872
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2918257288
Short name T532
Test name
Test status
Simulation time 23315672 ps
CPU time 1.28 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 209676 kb
Host smart-3f9d4bf0-9a59-464d-aca7-23f3e8e36557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918257288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2918257288
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4259170599
Short name T44
Test name
Test status
Simulation time 588963207 ps
CPU time 14.6 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 218068 kb
Host smart-8ed6ac42-c059-451b-a303-b15efc8cd5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259170599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4259170599
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.179600158
Short name T859
Test name
Test status
Simulation time 329547572 ps
CPU time 8.39 seconds
Started May 28 02:49:52 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 209612 kb
Host smart-0f437edb-3e4c-4367-a7b0-9c3156621849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179600158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.179600158
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1367789079
Short name T341
Test name
Test status
Simulation time 3751304931 ps
CPU time 28.53 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 218344 kb
Host smart-dab33cbc-056c-450d-9563-19363b016bb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367789079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1367789079
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3641758519
Short name T680
Test name
Test status
Simulation time 7516833840 ps
CPU time 13.53 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:13 PM PDT 24
Peak memory 218096 kb
Host smart-eed5aae5-75b2-4e56-a155-785f43dfda22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641758519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3641758519
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.429201506
Short name T624
Test name
Test status
Simulation time 1555340185 ps
CPU time 8.76 seconds
Started May 28 02:50:02 PM PDT 24
Finished May 28 02:50:13 PM PDT 24
Peak memory 213748 kb
Host smart-1050bece-9a24-469b-8746-f11890c271d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429201506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
429201506
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1789424132
Short name T770
Test name
Test status
Simulation time 1299958530 ps
CPU time 53.91 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:50:51 PM PDT 24
Peak memory 267844 kb
Host smart-cb1976d2-fd52-4dcc-9766-041639db921f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789424132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1789424132
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.666799446
Short name T5
Test name
Test status
Simulation time 529936421 ps
CPU time 22.75 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 250952 kb
Host smart-1308642d-1144-4b80-9e70-52e101847799
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666799446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.666799446
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3996139228
Short name T246
Test name
Test status
Simulation time 95715648 ps
CPU time 1.69 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:02 PM PDT 24
Peak memory 218148 kb
Host smart-9750b1a5-ea78-4042-a707-c3ed623e6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996139228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3996139228
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2312330354
Short name T780
Test name
Test status
Simulation time 229894848 ps
CPU time 12.52 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:50:15 PM PDT 24
Peak memory 218092 kb
Host smart-991871f2-bea5-4b0e-be57-f1ea86f4ab7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312330354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2312330354
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1607535088
Short name T12
Test name
Test status
Simulation time 2461120702 ps
CPU time 9.27 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 218116 kb
Host smart-17eef945-039d-4a31-91e7-0e82006c5272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607535088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1607535088
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4016225693
Short name T321
Test name
Test status
Simulation time 1097902153 ps
CPU time 8.22 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 218048 kb
Host smart-75baf6b3-5476-4b82-8bf6-1d4e62d801c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016225693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4016225693
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1455581150
Short name T373
Test name
Test status
Simulation time 1113457637 ps
CPU time 7.63 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 218248 kb
Host smart-7d709a5c-8cc1-4fd8-ba49-6723f5f382b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455581150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1455581150
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.103043714
Short name T740
Test name
Test status
Simulation time 111186652 ps
CPU time 2.29 seconds
Started May 28 02:50:00 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 214136 kb
Host smart-7c55dc5b-dea5-44db-a482-b91a0143467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103043714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.103043714
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2619067275
Short name T284
Test name
Test status
Simulation time 473532857 ps
CPU time 26.77 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 251024 kb
Host smart-d7399e44-06ce-47bb-9cde-1556c17a09e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619067275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2619067275
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1357192714
Short name T583
Test name
Test status
Simulation time 302100234 ps
CPU time 8.27 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:10 PM PDT 24
Peak memory 251028 kb
Host smart-9ac31961-b14d-4d95-8af8-a3690023da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357192714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1357192714
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2547242473
Short name T645
Test name
Test status
Simulation time 8216490172 ps
CPU time 137.77 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:52:20 PM PDT 24
Peak memory 283800 kb
Host smart-f96a15bc-7039-49e6-b214-374a2a6794c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547242473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2547242473
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4013189611
Short name T399
Test name
Test status
Simulation time 30045884 ps
CPU time 0.8 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:02 PM PDT 24
Peak memory 208680 kb
Host smart-8c3f07dc-64b9-44e4-bc35-ac5e72d0efc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013189611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4013189611
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2467719889
Short name T318
Test name
Test status
Simulation time 95556187 ps
CPU time 1.41 seconds
Started May 28 02:49:59 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 209680 kb
Host smart-9a455e63-a055-4a64-8310-d5c149d2f4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467719889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2467719889
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3119757587
Short name T427
Test name
Test status
Simulation time 1276204933 ps
CPU time 12.37 seconds
Started May 28 02:49:56 PM PDT 24
Finished May 28 02:50:13 PM PDT 24
Peak memory 218080 kb
Host smart-c10b30f0-568d-40ab-8ce4-8c44b690f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119757587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3119757587
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.444683340
Short name T175
Test name
Test status
Simulation time 2962896948 ps
CPU time 17.76 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 209696 kb
Host smart-51029596-aee1-4c43-8c49-6fa3c9acb31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444683340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.444683340
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3873552294
Short name T481
Test name
Test status
Simulation time 8169431975 ps
CPU time 57.39 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:59 PM PDT 24
Peak memory 219072 kb
Host smart-95a66d8e-24ea-48a6-a4f3-13b38380039d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873552294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3873552294
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.859696354
Short name T234
Test name
Test status
Simulation time 989033622 ps
CPU time 5.08 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 218052 kb
Host smart-f0d3578b-31c1-4893-9387-5d5e86abcfe6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859696354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.859696354
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3139236904
Short name T804
Test name
Test status
Simulation time 660279269 ps
CPU time 2.46 seconds
Started May 28 02:49:52 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 213000 kb
Host smart-92366c15-d14c-4f72-a453-5a5d7ceb4d96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139236904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3139236904
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.825845810
Short name T267
Test name
Test status
Simulation time 3359168771 ps
CPU time 73.77 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:51:16 PM PDT 24
Peak memory 278568 kb
Host smart-3bf377dd-46da-4afe-ac79-a72a0459e788
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825845810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.825845810
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3975991343
Short name T18
Test name
Test status
Simulation time 5953246405 ps
CPU time 24.16 seconds
Started May 28 02:49:59 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 250968 kb
Host smart-f2647a42-57bc-4535-93b0-98b1d88a57ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975991343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3975991343
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2380265010
Short name T242
Test name
Test status
Simulation time 231989843 ps
CPU time 3.09 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 218052 kb
Host smart-c90fe971-edbd-4af4-9ad5-225e39c30199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380265010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2380265010
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1595788522
Short name T730
Test name
Test status
Simulation time 1666251476 ps
CPU time 10.61 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 225976 kb
Host smart-846969bf-0cea-46ba-85f2-658895c669a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595788522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1595788522
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1966626081
Short name T342
Test name
Test status
Simulation time 397945662 ps
CPU time 11.54 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:13 PM PDT 24
Peak memory 225744 kb
Host smart-76783a7f-2ef7-4e2b-bbe0-a277dfac763a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966626081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1966626081
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1448369300
Short name T833
Test name
Test status
Simulation time 1126232688 ps
CPU time 10.51 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:50:13 PM PDT 24
Peak memory 218084 kb
Host smart-d0d68d33-33ac-4ea0-b726-4fcae3f056f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448369300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1448369300
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2133637550
Short name T57
Test name
Test status
Simulation time 1718097513 ps
CPU time 10.18 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:10 PM PDT 24
Peak memory 218140 kb
Host smart-e19cdf17-1cdf-4ad0-b76a-1386d2dac633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133637550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2133637550
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.365637202
Short name T524
Test name
Test status
Simulation time 81463115 ps
CPU time 2.62 seconds
Started May 28 02:49:59 PM PDT 24
Finished May 28 02:50:05 PM PDT 24
Peak memory 214148 kb
Host smart-ce37f6c2-a0ad-44a5-91bb-bca7da81b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365637202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.365637202
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3343452475
Short name T840
Test name
Test status
Simulation time 1363277859 ps
CPU time 24.07 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:26 PM PDT 24
Peak memory 251036 kb
Host smart-8ec7e0a1-b9b5-4d48-824c-a26e685ff5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343452475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3343452475
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.99014266
Short name T619
Test name
Test status
Simulation time 367152402 ps
CPU time 9.15 seconds
Started May 28 02:50:10 PM PDT 24
Finished May 28 02:50:20 PM PDT 24
Peak memory 251036 kb
Host smart-c7c2e22e-52f8-4b5b-9e10-a85532555a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99014266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.99014266
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2872283188
Short name T240
Test name
Test status
Simulation time 7031295789 ps
CPU time 70.04 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 277592 kb
Host smart-78e4fbb7-06f4-4f9e-9cd6-bcf7cb2d22dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872283188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2872283188
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4059753192
Short name T450
Test name
Test status
Simulation time 15209389 ps
CPU time 1.16 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 211616 kb
Host smart-a87020a2-7c6e-4854-b4b7-9eac530df6a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059753192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4059753192
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4209941718
Short name T758
Test name
Test status
Simulation time 102163321 ps
CPU time 1.31 seconds
Started May 28 02:49:59 PM PDT 24
Finished May 28 02:50:04 PM PDT 24
Peak memory 209760 kb
Host smart-a52336e8-0dfe-4779-b77c-c36918388e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209941718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4209941718
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2802683673
Short name T472
Test name
Test status
Simulation time 1223773114 ps
CPU time 10 seconds
Started May 28 02:50:02 PM PDT 24
Finished May 28 02:50:14 PM PDT 24
Peak memory 218120 kb
Host smart-d6f58ae4-114c-423f-97f4-0999aa260f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802683673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2802683673
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3622291940
Short name T679
Test name
Test status
Simulation time 639565587 ps
CPU time 2.41 seconds
Started May 28 02:50:02 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 209624 kb
Host smart-fcb9876c-525d-4e97-a6c0-5a1cc591f61e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622291940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3622291940
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.101700580
Short name T665
Test name
Test status
Simulation time 2501768777 ps
CPU time 37.66 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 218628 kb
Host smart-b9bc4c1c-7df5-4de5-a510-21e758426895
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101700580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.101700580
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.838396599
Short name T828
Test name
Test status
Simulation time 809584603 ps
CPU time 3.39 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:50:00 PM PDT 24
Peak memory 218028 kb
Host smart-3a5cd113-9c3b-4199-a093-dcbd159b0043
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838396599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.838396599
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.693788751
Short name T172
Test name
Test status
Simulation time 331738527 ps
CPU time 3.53 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 213332 kb
Host smart-cc45e9eb-c8ea-474c-8e3e-5b9a93ea5f40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693788751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
693788751
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1589602889
Short name T808
Test name
Test status
Simulation time 14859030169 ps
CPU time 84.67 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 269776 kb
Host smart-d3eca83b-62be-42ef-a869-6fd5c9ae70d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589602889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1589602889
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2525324031
Short name T544
Test name
Test status
Simulation time 1482223421 ps
CPU time 12.41 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:50:15 PM PDT 24
Peak memory 222044 kb
Host smart-dda9eb02-991d-4e7a-8d64-c85d937efcc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525324031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2525324031
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2287609152
Short name T594
Test name
Test status
Simulation time 14341602 ps
CPU time 1.39 seconds
Started May 28 02:49:54 PM PDT 24
Finished May 28 02:49:59 PM PDT 24
Peak memory 218100 kb
Host smart-f74ad36e-ae0b-4c76-a147-d5d38669ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287609152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2287609152
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2267683620
Short name T218
Test name
Test status
Simulation time 403520733 ps
CPU time 13.68 seconds
Started May 28 02:50:02 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 219052 kb
Host smart-29916e45-102b-4376-aa5c-dedb4843e5fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267683620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2267683620
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.770117751
Short name T323
Test name
Test status
Simulation time 550102334 ps
CPU time 11.12 seconds
Started May 28 02:49:58 PM PDT 24
Finished May 28 02:50:14 PM PDT 24
Peak memory 218040 kb
Host smart-c1324526-5319-418c-af29-b09abadf39a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770117751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.770117751
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.941104585
Short name T650
Test name
Test status
Simulation time 296256950 ps
CPU time 7.37 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 218100 kb
Host smart-b286bf47-4e9a-4c14-a73e-c103b7d032ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941104585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.941104585
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3286951699
Short name T535
Test name
Test status
Simulation time 696819623 ps
CPU time 12.13 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 217944 kb
Host smart-9605446d-df91-4376-8df3-e1e4fe6e5ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286951699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3286951699
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1353492897
Short name T343
Test name
Test status
Simulation time 90518428 ps
CPU time 1.44 seconds
Started May 28 02:49:55 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 217808 kb
Host smart-09f3c120-738f-44b7-bb72-249b861f1e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353492897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1353492897
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3900497062
Short name T623
Test name
Test status
Simulation time 502197520 ps
CPU time 33.59 seconds
Started May 28 02:49:59 PM PDT 24
Finished May 28 02:50:36 PM PDT 24
Peak memory 250968 kb
Host smart-7d2006db-a92b-4b80-8d7b-c81f8ae765d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900497062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3900497062
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3984740813
Short name T543
Test name
Test status
Simulation time 243503878 ps
CPU time 8.07 seconds
Started May 28 02:49:57 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 250992 kb
Host smart-fcfdee3f-1b92-4875-a010-3d9ffb224415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984740813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3984740813
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2982502511
Short name T712
Test name
Test status
Simulation time 11281071946 ps
CPU time 206.69 seconds
Started May 28 02:50:02 PM PDT 24
Finished May 28 02:53:31 PM PDT 24
Peak memory 251068 kb
Host smart-21d73492-2c67-4fdb-a97f-582a3f6634b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982502511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2982502511
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3521775414
Short name T148
Test name
Test status
Simulation time 16748747012 ps
CPU time 391.34 seconds
Started May 28 02:50:03 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 277656 kb
Host smart-9a012608-8bcb-44a6-9077-b00bcb56a9b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3521775414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3521775414
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2421282105
Short name T530
Test name
Test status
Simulation time 41919520 ps
CPU time 0.85 seconds
Started May 28 02:49:53 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 208816 kb
Host smart-8008c461-8202-4154-a15f-7d3f9a910028
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421282105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2421282105
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2903297278
Short name T796
Test name
Test status
Simulation time 145038098 ps
CPU time 0.94 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 209704 kb
Host smart-18e2c117-c13f-45ec-852e-687f06e0359d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903297278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2903297278
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.434496193
Short name T100
Test name
Test status
Simulation time 360483188 ps
CPU time 13.08 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 218216 kb
Host smart-22f0302e-8dff-4737-90d6-013eef271001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434496193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.434496193
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3277991917
Short name T28
Test name
Test status
Simulation time 1101979500 ps
CPU time 3.67 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 209620 kb
Host smart-4dcaac3b-ebb3-4bc5-bc93-e5b28ea37c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277991917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3277991917
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.4010316996
Short name T309
Test name
Test status
Simulation time 5570473693 ps
CPU time 39.33 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:51:13 PM PDT 24
Peak memory 219248 kb
Host smart-0391cf7d-5417-4c20-88b8-454d3685ec58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010316996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.4010316996
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1142152305
Short name T403
Test name
Test status
Simulation time 151574580 ps
CPU time 5.43 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 218104 kb
Host smart-27f6d678-2d59-48ac-84f5-42d2166c0a25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142152305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1142152305
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3434537398
Short name T823
Test name
Test status
Simulation time 882688355 ps
CPU time 6.67 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:30 PM PDT 24
Peak memory 213492 kb
Host smart-8ddc5457-5b83-4607-bf44-6ae0dee61c6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434537398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3434537398
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2876530015
Short name T538
Test name
Test status
Simulation time 1137984577 ps
CPU time 35.21 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 251020 kb
Host smart-fc898b0e-87d2-4e9a-9246-db196ba89a53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876530015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2876530015
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1202002399
Short name T817
Test name
Test status
Simulation time 368858017 ps
CPU time 11.82 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 218028 kb
Host smart-30ee3971-8c86-409d-b79e-180861e9bdae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202002399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1202002399
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1960402623
Short name T380
Test name
Test status
Simulation time 101151317 ps
CPU time 2.96 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 218148 kb
Host smart-f6d27736-f3be-48a4-9376-744623744af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960402623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1960402623
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1220227745
Short name T774
Test name
Test status
Simulation time 1695574191 ps
CPU time 11.35 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 218108 kb
Host smart-3cd72298-2260-4ff5-b6ef-e930bf64f78a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220227745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1220227745
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4025172340
Short name T698
Test name
Test status
Simulation time 1001927990 ps
CPU time 8.46 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218036 kb
Host smart-5f2a3efb-38f4-43b9-af3f-2fa79dd803ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025172340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4025172340
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2617863764
Short name T263
Test name
Test status
Simulation time 480862871 ps
CPU time 9.74 seconds
Started May 28 02:50:13 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 218124 kb
Host smart-aac01793-15c8-4d57-987d-c6d7e333319d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617863764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2617863764
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2590335178
Short name T626
Test name
Test status
Simulation time 522077320 ps
CPU time 11.62 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:36 PM PDT 24
Peak memory 218096 kb
Host smart-b3c2dddd-f0be-4fd0-be64-f3996522f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590335178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2590335178
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1676306437
Short name T290
Test name
Test status
Simulation time 111168912 ps
CPU time 6.69 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 217904 kb
Host smart-08cf5569-c2a5-4c12-83ba-6c6aa4c33bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676306437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1676306437
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3874897315
Short name T499
Test name
Test status
Simulation time 423653555 ps
CPU time 22.92 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 251016 kb
Host smart-ac194df6-5a45-46c6-9fe8-d62a67457e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874897315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3874897315
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.51246920
Short name T716
Test name
Test status
Simulation time 254513257 ps
CPU time 7.07 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 250504 kb
Host smart-c4a5394b-7fc2-4439-91e7-528d0571c333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51246920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.51246920
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2455569012
Short name T820
Test name
Test status
Simulation time 3328175054 ps
CPU time 50.54 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:51:15 PM PDT 24
Peak memory 248600 kb
Host smart-7620a5fb-b98d-416e-9941-02dda8a37b2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455569012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2455569012
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4220740235
Short name T776
Test name
Test status
Simulation time 74862257 ps
CPU time 0.91 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:17 PM PDT 24
Peak memory 208660 kb
Host smart-3b814cbd-45bb-4b38-b5ee-af04c32d42d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220740235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4220740235
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1147519208
Short name T80
Test name
Test status
Simulation time 20440425 ps
CPU time 0.93 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 209676 kb
Host smart-186d46f0-8ea9-45a0-b547-3ec25ad8d2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147519208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1147519208
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3011118591
Short name T173
Test name
Test status
Simulation time 722296408 ps
CPU time 10.06 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 218092 kb
Host smart-a9623cfc-856c-42eb-a0e6-ac4c7383290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011118591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3011118591
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1457028666
Short name T508
Test name
Test status
Simulation time 242689932 ps
CPU time 6.71 seconds
Started May 28 02:49:03 PM PDT 24
Finished May 28 02:49:20 PM PDT 24
Peak memory 217092 kb
Host smart-04abb0c2-4f42-4342-8f32-cb91ae8a6324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457028666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1457028666
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1909057837
Short name T813
Test name
Test status
Simulation time 1891351402 ps
CPU time 33.69 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 218028 kb
Host smart-4df5bec8-eaa8-4b41-bb93-375746edd279
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909057837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1909057837
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.992788983
Short name T703
Test name
Test status
Simulation time 263102704 ps
CPU time 3.78 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 217220 kb
Host smart-fc2a77db-a37d-41d7-83fe-22f699f65a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992788983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.992788983
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3366293116
Short name T225
Test name
Test status
Simulation time 180954357 ps
CPU time 4.56 seconds
Started May 28 02:49:08 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 217996 kb
Host smart-90029278-ecd0-459e-a471-f73564c73eb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366293116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3366293116
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.501204166
Short name T182
Test name
Test status
Simulation time 674127971 ps
CPU time 20.37 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:35 PM PDT 24
Peak memory 213176 kb
Host smart-da186dae-eae6-4310-93d7-585bfee2bdeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501204166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.501204166
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.920700031
Short name T76
Test name
Test status
Simulation time 831981835 ps
CPU time 11.34 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 213784 kb
Host smart-10ca4f59-0ded-4a06-9a91-f68029101bde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920700031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.920700031
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3595718398
Short name T178
Test name
Test status
Simulation time 6668655780 ps
CPU time 61.95 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 251240 kb
Host smart-53d1e625-2f46-4714-8469-250a8535a3b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595718398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3595718398
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3281520021
Short name T328
Test name
Test status
Simulation time 3834650558 ps
CPU time 29.34 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:43 PM PDT 24
Peak memory 248084 kb
Host smart-71daea1d-9883-46c2-9e55-0a31396adc37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281520021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3281520021
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1475778142
Short name T344
Test name
Test status
Simulation time 56310621 ps
CPU time 2.5 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 218196 kb
Host smart-f44d1927-46fc-44de-bc20-b3c02499ae0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475778142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1475778142
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.4059104099
Short name T685
Test name
Test status
Simulation time 390954993 ps
CPU time 21.94 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 217800 kb
Host smart-581efce3-8813-4703-81d9-c39d3a0f752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059104099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.4059104099
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3681521307
Short name T93
Test name
Test status
Simulation time 1627543248 ps
CPU time 40.18 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 281856 kb
Host smart-cbdf9d0c-f75e-4880-86b5-1a7c7bc3a937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681521307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3681521307
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.160065303
Short name T428
Test name
Test status
Simulation time 298139655 ps
CPU time 9.47 seconds
Started May 28 02:49:03 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 218196 kb
Host smart-8fe0f36c-fbef-4d4d-af70-c5486ca11453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160065303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.160065303
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2801479079
Short name T348
Test name
Test status
Simulation time 1339592189 ps
CPU time 13.99 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 218088 kb
Host smart-f3901b2c-9b01-4724-ab62-e655926a25a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801479079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2801479079
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3729694308
Short name T299
Test name
Test status
Simulation time 364660706 ps
CPU time 8.31 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 217840 kb
Host smart-f385fd91-09e8-49d5-bc0c-78c42310f120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729694308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
729694308
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2041812942
Short name T749
Test name
Test status
Simulation time 595771409 ps
CPU time 10.77 seconds
Started May 28 02:49:03 PM PDT 24
Finished May 28 02:49:23 PM PDT 24
Peak memory 218092 kb
Host smart-ccaa1554-3a15-4ed8-89ac-c973fe90a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041812942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2041812942
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3784244978
Short name T830
Test name
Test status
Simulation time 92065029 ps
CPU time 2.37 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 214364 kb
Host smart-be5f72d6-4c87-478e-b5e5-d4033298d121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784244978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3784244978
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2903672688
Short name T612
Test name
Test status
Simulation time 620295862 ps
CPU time 19.44 seconds
Started May 28 02:49:03 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 251000 kb
Host smart-50268dd1-2c69-4a82-83f6-5af6d9cedc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903672688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2903672688
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3702621611
Short name T631
Test name
Test status
Simulation time 1212729414 ps
CPU time 7.46 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 250504 kb
Host smart-3720f832-b26d-4a14-b2c4-f50bbd090007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702621611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3702621611
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.234051573
Short name T89
Test name
Test status
Simulation time 2913616734 ps
CPU time 64.22 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 217860 kb
Host smart-2f2b40d8-a864-40a9-9780-7f741856ca48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234051573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.234051573
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3990677322
Short name T692
Test name
Test status
Simulation time 15983013 ps
CPU time 0.98 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 212628 kb
Host smart-0ef925a7-5c54-4d5a-a952-59bcba2f0239
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990677322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3990677322
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1300382752
Short name T507
Test name
Test status
Simulation time 154815579 ps
CPU time 0.93 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:26 PM PDT 24
Peak memory 209628 kb
Host smart-d91bb999-cde6-4bf6-a7b5-f87241fb903d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300382752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1300382752
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.763317420
Short name T668
Test name
Test status
Simulation time 1219196592 ps
CPU time 11.44 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 217996 kb
Host smart-149139e0-fb0e-4c77-a23d-a8cfef08d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763317420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.763317420
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1927583378
Short name T30
Test name
Test status
Simulation time 1914031643 ps
CPU time 12.09 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 217100 kb
Host smart-e471dda2-11fa-418d-9d0d-1b5b0da1713a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927583378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1927583378
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.749885839
Short name T367
Test name
Test status
Simulation time 40222113 ps
CPU time 1.54 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 218104 kb
Host smart-c40fcfe7-6c4e-4fa0-b7c0-1b25f3f90cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749885839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.749885839
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3089719423
Short name T607
Test name
Test status
Simulation time 1559495749 ps
CPU time 11.96 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 219104 kb
Host smart-77427c70-f6c1-4474-83a6-b1b592ba7873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089719423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3089719423
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.845645814
Short name T381
Test name
Test status
Simulation time 264568476 ps
CPU time 8.42 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:31 PM PDT 24
Peak memory 218016 kb
Host smart-69ada45b-40c3-4b8a-ac0a-1273997d0cb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845645814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.845645814
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.361867796
Short name T652
Test name
Test status
Simulation time 247810421 ps
CPU time 8.99 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:31 PM PDT 24
Peak memory 218036 kb
Host smart-ecc90a18-2efd-4a1c-a86a-255cb6382554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361867796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.361867796
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.438786241
Short name T272
Test name
Test status
Simulation time 433486312 ps
CPU time 3.82 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 214216 kb
Host smart-b2a0e0aa-bb6b-4575-a9fa-cd58d89f5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438786241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.438786241
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2733627847
Short name T731
Test name
Test status
Simulation time 337351072 ps
CPU time 31.02 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:57 PM PDT 24
Peak memory 251028 kb
Host smart-b7dd6326-bbba-4cf7-8c6e-bae0d1f3c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733627847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2733627847
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.452050512
Short name T710
Test name
Test status
Simulation time 265741702 ps
CPU time 3.31 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 226448 kb
Host smart-f1498abb-6587-46b6-80dc-8ca66d3e765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452050512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.452050512
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3637209370
Short name T557
Test name
Test status
Simulation time 7761908886 ps
CPU time 146.04 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:52:45 PM PDT 24
Peak memory 276764 kb
Host smart-ea9109ae-dc7c-4bdd-b1df-ee05f22d0c09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637209370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3637209370
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.883305752
Short name T438
Test name
Test status
Simulation time 17901864 ps
CPU time 1.02 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:26 PM PDT 24
Peak memory 211596 kb
Host smart-248549c2-7cda-4a22-8e85-dbebad77d1c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883305752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.883305752
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1927613265
Short name T220
Test name
Test status
Simulation time 15190514 ps
CPU time 0.83 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:25 PM PDT 24
Peak memory 209616 kb
Host smart-ed00a673-fce4-4ccd-bb47-72472d650fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927613265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1927613265
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2693746623
Short name T265
Test name
Test status
Simulation time 942384174 ps
CPU time 10.3 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:32 PM PDT 24
Peak memory 218100 kb
Host smart-0bc1eb39-15dd-45fe-949b-072a01a291e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693746623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2693746623
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1254849071
Short name T71
Test name
Test status
Simulation time 282198754 ps
CPU time 1.52 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:22 PM PDT 24
Peak memory 209600 kb
Host smart-5a3a085d-4f09-4350-ad7b-a9f2e60015fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254849071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1254849071
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.55799525
Short name T577
Test name
Test status
Simulation time 236798094 ps
CPU time 2.67 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 217904 kb
Host smart-496e713d-d0e9-489f-b285-399c2223e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55799525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.55799525
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.778717768
Short name T867
Test name
Test status
Simulation time 1673900065 ps
CPU time 12.98 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:31 PM PDT 24
Peak memory 218280 kb
Host smart-6a2479a0-6864-40ea-984a-ffd3f902bb0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778717768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.778717768
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4232664000
Short name T451
Test name
Test status
Simulation time 828745816 ps
CPU time 8.56 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:30 PM PDT 24
Peak memory 218028 kb
Host smart-db2e7a16-806a-42fb-aaee-27348c61195d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232664000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4232664000
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.335878807
Short name T651
Test name
Test status
Simulation time 2109879129 ps
CPU time 9.33 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 217984 kb
Host smart-71ed410e-8edf-4bbd-8b2d-5dc8bea38d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335878807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.335878807
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2567677714
Short name T424
Test name
Test status
Simulation time 236789446 ps
CPU time 8.7 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 218236 kb
Host smart-930788e4-a9fc-4132-bdb3-d7d8cdbaba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567677714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2567677714
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1951607796
Short name T329
Test name
Test status
Simulation time 24734780 ps
CPU time 1.81 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 213660 kb
Host smart-5e1f5b04-ebd8-4458-b67c-3b91984cf7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951607796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1951607796
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2685080602
Short name T176
Test name
Test status
Simulation time 269511485 ps
CPU time 25.52 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:50 PM PDT 24
Peak memory 250972 kb
Host smart-2f290a46-fcb4-4c97-8fd1-c29cf4fafbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685080602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2685080602
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3905528543
Short name T92
Test name
Test status
Simulation time 546171573 ps
CPU time 6.36 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 244220 kb
Host smart-0f959606-a29e-41f8-a224-5cfa9b128442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905528543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3905528543
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3126875136
Short name T824
Test name
Test status
Simulation time 6119185169 ps
CPU time 204.58 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:53:49 PM PDT 24
Peak memory 270816 kb
Host smart-faaeed99-93bb-40a9-b8d8-7ff96b2e1831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126875136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3126875136
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2338713547
Short name T846
Test name
Test status
Simulation time 24961928 ps
CPU time 0.8 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:23 PM PDT 24
Peak memory 208596 kb
Host smart-da3fd709-e22a-4c92-9e40-bb49aea8d601
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338713547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2338713547
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2424765989
Short name T463
Test name
Test status
Simulation time 68876266 ps
CPU time 1.14 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 208608 kb
Host smart-4838c51a-21f5-45b1-8790-5fe9d13766e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424765989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2424765989
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2358523327
Short name T588
Test name
Test status
Simulation time 814708680 ps
CPU time 9.91 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 218156 kb
Host smart-0365732c-0e1b-4441-af33-1261f39f722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358523327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2358523327
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.907193713
Short name T362
Test name
Test status
Simulation time 2325907275 ps
CPU time 5.75 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 209660 kb
Host smart-99d96a55-11c7-4a9b-bb35-b02302f773b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907193713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.907193713
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.4177117590
Short name T658
Test name
Test status
Simulation time 319132982 ps
CPU time 2.98 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 218080 kb
Host smart-5dcc477c-dad6-4c95-aee0-d7fe9ef9fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177117590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.4177117590
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3640749674
Short name T572
Test name
Test status
Simulation time 1055344903 ps
CPU time 16.43 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:38 PM PDT 24
Peak memory 219048 kb
Host smart-4f1dfecd-b895-435b-b210-beef32045a75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640749674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3640749674
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1886075971
Short name T491
Test name
Test status
Simulation time 280474288 ps
CPU time 10.12 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 218104 kb
Host smart-048483a0-0220-40a4-9c19-a94baaf75ccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886075971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1886075971
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.596338144
Short name T473
Test name
Test status
Simulation time 168350040 ps
CPU time 5.76 seconds
Started May 28 02:50:14 PM PDT 24
Finished May 28 02:50:22 PM PDT 24
Peak memory 218064 kb
Host smart-26cb6a99-534c-4061-8286-c3c849a5cad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596338144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.596338144
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2856861038
Short name T58
Test name
Test status
Simulation time 244062611 ps
CPU time 9.36 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 218236 kb
Host smart-8f33bc15-58bf-4225-a598-1e811e161c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856861038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2856861038
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.178353907
Short name T157
Test name
Test status
Simulation time 86805872 ps
CPU time 4.07 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 218272 kb
Host smart-693d426c-8064-48b4-8d48-95748fdfc93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178353907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.178353907
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3103569106
Short name T335
Test name
Test status
Simulation time 396435070 ps
CPU time 33.1 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 250884 kb
Host smart-13f7f9e1-6063-41ef-8a02-a32f318fd613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103569106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3103569106
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2093460381
Short name T422
Test name
Test status
Simulation time 333808452 ps
CPU time 11.8 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 243568 kb
Host smart-b24c298c-4ff1-4963-b917-2f44219ec5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093460381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2093460381
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.64401511
Short name T803
Test name
Test status
Simulation time 4868905193 ps
CPU time 70.91 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:51:38 PM PDT 24
Peak memory 249008 kb
Host smart-97ac1534-52a0-4d19-810c-16708f225065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64401511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.lc_ctrl_stress_all.64401511
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3327780358
Short name T853
Test name
Test status
Simulation time 147602476760 ps
CPU time 1371.81 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 03:13:16 PM PDT 24
Peak memory 487752 kb
Host smart-7f2c6efe-7582-459b-8c1c-5b6bf74abca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3327780358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3327780358
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2274565490
Short name T743
Test name
Test status
Simulation time 14649220 ps
CPU time 0.81 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:20 PM PDT 24
Peak memory 208560 kb
Host smart-193d4c19-16e4-4576-8071-aec3b9b93318
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274565490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2274565490
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.393003419
Short name T221
Test name
Test status
Simulation time 43106283 ps
CPU time 1.04 seconds
Started May 28 02:50:21 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 209664 kb
Host smart-9823f290-a4fd-42a5-ad64-576453ed067a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393003419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.393003419
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1329331665
Short name T471
Test name
Test status
Simulation time 1286032688 ps
CPU time 11.1 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 218176 kb
Host smart-a418481e-a1cd-4e69-9d2f-b026ae39666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329331665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1329331665
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1955710332
Short name T561
Test name
Test status
Simulation time 2854856991 ps
CPU time 3.15 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 209716 kb
Host smart-f9761f2f-d8b6-403c-8a2e-b30392ec8e2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955710332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1955710332
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1086328110
Short name T295
Test name
Test status
Simulation time 226984003 ps
CPU time 2.47 seconds
Started May 28 02:50:22 PM PDT 24
Finished May 28 02:50:31 PM PDT 24
Peak memory 218080 kb
Host smart-0d12a847-0245-497e-8e5b-cad93784eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086328110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1086328110
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2908885333
Short name T354
Test name
Test status
Simulation time 2177029887 ps
CPU time 13.03 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:36 PM PDT 24
Peak memory 226188 kb
Host smart-8a134e9e-4cdb-4c7c-8dd3-e0b2b618f484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908885333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2908885333
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.618264521
Short name T361
Test name
Test status
Simulation time 210547763 ps
CPU time 9.66 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 218040 kb
Host smart-058d0888-e4cc-411c-8b3b-db1f71028dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618264521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.618264521
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1033371627
Short name T229
Test name
Test status
Simulation time 479734821 ps
CPU time 7.59 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218124 kb
Host smart-ff815d47-8ff3-43a7-83e6-75c4c1d764c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033371627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1033371627
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.512933448
Short name T440
Test name
Test status
Simulation time 1306975731 ps
CPU time 11.25 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218236 kb
Host smart-2347cb13-8e7e-4af9-93c7-b380546dd3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512933448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.512933448
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1855614765
Short name T452
Test name
Test status
Simulation time 19073995 ps
CPU time 1.41 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:25 PM PDT 24
Peak memory 217888 kb
Host smart-dfcd2b25-c0cd-4f44-8032-5b519f8fb81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855614765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1855614765
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1574357752
Short name T360
Test name
Test status
Simulation time 749188041 ps
CPU time 21.59 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 249576 kb
Host smart-b7e2c1f0-800b-4bc9-bc42-45e62e4ba0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574357752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1574357752
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1231029751
Short name T581
Test name
Test status
Simulation time 153355710 ps
CPU time 3.12 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:29 PM PDT 24
Peak memory 217912 kb
Host smart-f789c546-2c27-43b9-b76f-c5a610b1e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231029751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1231029751
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3045040460
Short name T654
Test name
Test status
Simulation time 30706203 ps
CPU time 0.76 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:25 PM PDT 24
Peak memory 208536 kb
Host smart-ed12d6ec-a4b0-4abb-83e0-e8ae295c2219
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045040460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3045040460
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2925483558
Short name T534
Test name
Test status
Simulation time 17629430 ps
CPU time 1.13 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 209696 kb
Host smart-6239f8d2-f1b2-45b6-a43e-74dc45355cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925483558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2925483558
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.4231961879
Short name T836
Test name
Test status
Simulation time 388218461 ps
CPU time 10.02 seconds
Started May 28 02:50:22 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 218080 kb
Host smart-40e45c3b-bbd2-4c28-a9cc-db51da8fe282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231961879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.4231961879
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3960972056
Short name T448
Test name
Test status
Simulation time 284557982 ps
CPU time 4.73 seconds
Started May 28 02:50:15 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 209732 kb
Host smart-f10f9038-2825-426e-9470-7ed915bc1a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960972056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3960972056
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1264674410
Short name T750
Test name
Test status
Simulation time 72319699 ps
CPU time 2.92 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:30 PM PDT 24
Peak memory 218084 kb
Host smart-0416df09-c099-4c9e-9c3a-d91bcc371621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264674410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1264674410
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2891289281
Short name T590
Test name
Test status
Simulation time 3330488509 ps
CPU time 10.74 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 219404 kb
Host smart-81808316-fe05-4774-bbd0-bab6f25f654a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891289281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2891289281
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3181404081
Short name T671
Test name
Test status
Simulation time 886172014 ps
CPU time 10.43 seconds
Started May 28 02:50:22 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 218020 kb
Host smart-7fd7b46f-f2e8-4cc3-82aa-46d733567e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181404081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3181404081
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3097227349
Short name T726
Test name
Test status
Simulation time 244924963 ps
CPU time 7.45 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218064 kb
Host smart-1279deae-35eb-4a27-8b7e-a5c6232913ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097227349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3097227349
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3311692385
Short name T392
Test name
Test status
Simulation time 4963979812 ps
CPU time 11.82 seconds
Started May 28 02:50:18 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 218184 kb
Host smart-887cdf32-003d-4ed1-ab4e-2dedded9f83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311692385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3311692385
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.212964227
Short name T298
Test name
Test status
Simulation time 111133824 ps
CPU time 2.49 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 214000 kb
Host smart-c69825dc-a2a3-40b2-9c9b-9b089cee84d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212964227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.212964227
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1198655799
Short name T587
Test name
Test status
Simulation time 649670869 ps
CPU time 24.57 seconds
Started May 28 02:50:21 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 251124 kb
Host smart-5da9e0d3-0023-4f22-b2ae-d140609f6b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198655799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1198655799
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1183971004
Short name T237
Test name
Test status
Simulation time 57884855 ps
CPU time 10.07 seconds
Started May 28 02:50:16 PM PDT 24
Finished May 28 02:50:33 PM PDT 24
Peak memory 251024 kb
Host smart-6c4dd778-6c75-49d0-8406-46d88f023968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183971004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1183971004
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3328131053
Short name T254
Test name
Test status
Simulation time 9141117443 ps
CPU time 54.12 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:51:18 PM PDT 24
Peak memory 276516 kb
Host smart-02ee2877-6eda-47ba-bbb6-15ac954f069e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328131053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3328131053
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3995065751
Short name T445
Test name
Test status
Simulation time 12351824 ps
CPU time 1.09 seconds
Started May 28 02:50:19 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 211724 kb
Host smart-9fb24a3b-dc64-4d6e-b126-a44de177e798
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995065751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3995065751
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2239081507
Short name T695
Test name
Test status
Simulation time 51150003 ps
CPU time 0.95 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 209684 kb
Host smart-7409b98e-121b-4443-9a93-e9467608fd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239081507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2239081507
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1667041508
Short name T317
Test name
Test status
Simulation time 1135637765 ps
CPU time 12.4 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:46 PM PDT 24
Peak memory 218096 kb
Host smart-c06009cd-2be8-49e9-a906-1379f6f8076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667041508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1667041508
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2910438495
Short name T396
Test name
Test status
Simulation time 328210011 ps
CPU time 4.32 seconds
Started May 28 02:50:32 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 217032 kb
Host smart-89f7a2a0-a946-491e-8fe5-e68b45cb5606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910438495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2910438495
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.695154828
Short name T606
Test name
Test status
Simulation time 216867480 ps
CPU time 2.56 seconds
Started May 28 02:50:27 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 218200 kb
Host smart-479e144d-f5c6-4dcb-baac-8e2474d4de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695154828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.695154828
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1630550207
Short name T717
Test name
Test status
Simulation time 1007387099 ps
CPU time 15.23 seconds
Started May 28 02:50:27 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 219032 kb
Host smart-eb3b8068-037a-45dd-a3f1-28b3a15e05e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630550207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1630550207
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2010250360
Short name T336
Test name
Test status
Simulation time 278508603 ps
CPU time 11.32 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 218048 kb
Host smart-6712b1bb-47b5-4304-9db4-e165a46ee9c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010250360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2010250360
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.19422424
Short name T339
Test name
Test status
Simulation time 239276767 ps
CPU time 9.38 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:42 PM PDT 24
Peak memory 218024 kb
Host smart-5c491e69-4fff-4dd8-acb2-86c986fa1e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19422424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.19422424
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1722894808
Short name T105
Test name
Test status
Simulation time 1615819622 ps
CPU time 10.74 seconds
Started May 28 02:50:29 PM PDT 24
Finished May 28 02:50:46 PM PDT 24
Peak memory 218216 kb
Host smart-7104dda5-e234-4de9-ab17-2e15860aa546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722894808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1722894808
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3221384900
Short name T537
Test name
Test status
Simulation time 639895231 ps
CPU time 5.07 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:32 PM PDT 24
Peak memory 217792 kb
Host smart-c65fe7a0-701a-470e-986a-dd0abc5175cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221384900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3221384900
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1730221587
Short name T729
Test name
Test status
Simulation time 367079356 ps
CPU time 29.37 seconds
Started May 28 02:50:20 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 251036 kb
Host smart-fc4d3686-7661-4738-ad06-5a5becb4bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730221587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1730221587
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.574930406
Short name T500
Test name
Test status
Simulation time 243707639 ps
CPU time 3.44 seconds
Started May 28 02:50:17 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 218076 kb
Host smart-737945c8-3c91-4694-9127-9888fe2a43d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574930406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.574930406
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1720073961
Short name T676
Test name
Test status
Simulation time 17909475723 ps
CPU time 549.81 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:59:50 PM PDT 24
Peak memory 283844 kb
Host smart-ff4b0ec0-e82d-4e14-976d-c22eb1421a67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720073961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1720073961
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3433991966
Short name T455
Test name
Test status
Simulation time 385623265 ps
CPU time 11.4 seconds
Started May 28 02:50:34 PM PDT 24
Finished May 28 02:50:53 PM PDT 24
Peak memory 218080 kb
Host smart-ad0ff6a1-cb52-43ec-9851-c0dc72736261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433991966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3433991966
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1053951666
Short name T554
Test name
Test status
Simulation time 4393867829 ps
CPU time 3.99 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 209660 kb
Host smart-6d2fa7d5-abed-45b7-bb10-e9aa6471791d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053951666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1053951666
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2211092820
Short name T219
Test name
Test status
Simulation time 97428498 ps
CPU time 2.28 seconds
Started May 28 02:50:27 PM PDT 24
Finished May 28 02:50:34 PM PDT 24
Peak memory 218080 kb
Host smart-39b24e46-059f-4745-a1c7-19a6f78f794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211092820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2211092820
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.309823314
Short name T790
Test name
Test status
Simulation time 695646652 ps
CPU time 14.17 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 226200 kb
Host smart-b66a6133-5db8-4c9b-9e1b-f888f1a22df0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309823314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.309823314
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1771271889
Short name T45
Test name
Test status
Simulation time 1280776474 ps
CPU time 9.15 seconds
Started May 28 02:50:29 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 218048 kb
Host smart-98405e21-46d2-41ab-b2fb-13450f42c926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771271889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1771271889
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1600996991
Short name T302
Test name
Test status
Simulation time 2374405635 ps
CPU time 9.59 seconds
Started May 28 02:50:26 PM PDT 24
Finished May 28 02:50:42 PM PDT 24
Peak memory 218120 kb
Host smart-947a3e3d-ff25-43a3-be1a-d81acbf011a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600996991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1600996991
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2472194739
Short name T549
Test name
Test status
Simulation time 1887454767 ps
CPU time 7.85 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:50 PM PDT 24
Peak memory 218160 kb
Host smart-ca94981c-1283-4c48-9b59-f9156bc8fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472194739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2472194739
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4208601437
Short name T454
Test name
Test status
Simulation time 62360189 ps
CPU time 3.22 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 214496 kb
Host smart-786761fa-5a15-4427-b1a9-7feb9920d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208601437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4208601437
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2027818893
Short name T689
Test name
Test status
Simulation time 235557645 ps
CPU time 22.58 seconds
Started May 28 02:50:30 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 251056 kb
Host smart-d96f5740-d18a-4750-bd0a-ca63c938c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027818893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2027818893
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3175186477
Short name T611
Test name
Test status
Simulation time 191498531 ps
CPU time 3.92 seconds
Started May 28 02:50:29 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 226444 kb
Host smart-042714ec-2a86-4f61-ab51-198b686e283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175186477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3175186477
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.886301152
Short name T861
Test name
Test status
Simulation time 16904043524 ps
CPU time 184.51 seconds
Started May 28 02:50:26 PM PDT 24
Finished May 28 02:53:36 PM PDT 24
Peak memory 251056 kb
Host smart-78e3e8f8-05e4-43e8-b253-2db247f29a9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886301152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.886301152
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2844206963
Short name T574
Test name
Test status
Simulation time 14751927 ps
CPU time 1.21 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 211696 kb
Host smart-a082fdf8-fb8f-435c-9c68-0c8d45932572
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844206963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2844206963
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2603507924
Short name T812
Test name
Test status
Simulation time 62317544 ps
CPU time 1.12 seconds
Started May 28 02:50:30 PM PDT 24
Finished May 28 02:50:38 PM PDT 24
Peak memory 209624 kb
Host smart-d8eed17c-a673-4f5d-a895-82907586b432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603507924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2603507924
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.14612537
Short name T401
Test name
Test status
Simulation time 3457865476 ps
CPU time 28.15 seconds
Started May 28 02:50:32 PM PDT 24
Finished May 28 02:51:07 PM PDT 24
Peak memory 219112 kb
Host smart-de2fc0d2-6c89-4136-b197-03367f8e7a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14612537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.14612537
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1622218172
Short name T187
Test name
Test status
Simulation time 3674184249 ps
CPU time 4.67 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 209688 kb
Host smart-73800afb-4349-4693-a307-9f651d5b8c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622218172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1622218172
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3062151387
Short name T315
Test name
Test status
Simulation time 107731396 ps
CPU time 1.93 seconds
Started May 28 02:50:34 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 218104 kb
Host smart-0a4f2d6f-50d5-4e95-80d4-fef6a551a4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062151387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3062151387
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2786640318
Short name T777
Test name
Test status
Simulation time 1682213629 ps
CPU time 10.34 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:51 PM PDT 24
Peak memory 226216 kb
Host smart-d8069031-395e-411d-9d0e-90567bb7a08d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786640318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2786640318
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2632192947
Short name T637
Test name
Test status
Simulation time 656216042 ps
CPU time 9.42 seconds
Started May 28 02:50:30 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 218112 kb
Host smart-3811bece-7439-477b-bf77-d1ea14aaf901
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632192947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2632192947
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3588387738
Short name T288
Test name
Test status
Simulation time 477632925 ps
CPU time 8.61 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:46 PM PDT 24
Peak memory 218096 kb
Host smart-95d95c6f-9e02-45f8-8657-be6aba8c3367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588387738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3588387738
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4142063543
Short name T569
Test name
Test status
Simulation time 321112021 ps
CPU time 13.18 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:51:01 PM PDT 24
Peak memory 218156 kb
Host smart-2a8f3801-2fdb-4a37-9c6f-421e46b8ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142063543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4142063543
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2950342976
Short name T629
Test name
Test status
Simulation time 79806290 ps
CPU time 1.92 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 213968 kb
Host smart-de186d87-8c41-42d9-93ce-463040676882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950342976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2950342976
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2585755576
Short name T483
Test name
Test status
Simulation time 967145199 ps
CPU time 22.52 seconds
Started May 28 02:50:30 PM PDT 24
Finished May 28 02:50:59 PM PDT 24
Peak memory 250916 kb
Host smart-40a841db-7ba1-4ee7-887c-39d0fec606dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585755576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2585755576
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4240626489
Short name T287
Test name
Test status
Simulation time 61780907 ps
CPU time 3.54 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 218000 kb
Host smart-5ce5f781-16c8-4346-a6b7-dff3746bc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240626489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4240626489
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.898321649
Short name T493
Test name
Test status
Simulation time 16112793233 ps
CPU time 103.58 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:52:23 PM PDT 24
Peak memory 223532 kb
Host smart-4d0a3db3-8252-4063-b482-6dc1e97b6242
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898321649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.898321649
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1763107509
Short name T97
Test name
Test status
Simulation time 12506952240 ps
CPU time 304.16 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 226368 kb
Host smart-95add90b-5fbb-42c3-a598-a9d534d00164
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1763107509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1763107509
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1634010566
Short name T732
Test name
Test status
Simulation time 32625003 ps
CPU time 1.09 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:38 PM PDT 24
Peak memory 211616 kb
Host smart-d0dee7ef-dbf9-428f-b96f-b2c75d880bd2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634010566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1634010566
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2749146553
Short name T334
Test name
Test status
Simulation time 44601344 ps
CPU time 1.02 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 209692 kb
Host smart-1006475c-f4b2-4f35-9267-718bce522c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749146553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2749146553
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.537386023
Short name T359
Test name
Test status
Simulation time 6632950481 ps
CPU time 21.38 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 218136 kb
Host smart-5912deee-800f-4f2c-9adf-3de79e6ea4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537386023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.537386023
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2155353113
Short name T497
Test name
Test status
Simulation time 127069387 ps
CPU time 2.31 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 216976 kb
Host smart-43661420-451f-4757-93b1-2e7c2557ec88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155353113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2155353113
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.649373107
Short name T632
Test name
Test status
Simulation time 134784952 ps
CPU time 2.58 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:41 PM PDT 24
Peak memory 218088 kb
Host smart-3e2a62bc-cbad-46ea-b12d-0adb5dd2765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649373107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.649373107
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2633642410
Short name T409
Test name
Test status
Simulation time 219986932 ps
CPU time 11.86 seconds
Started May 28 02:50:32 PM PDT 24
Finished May 28 02:50:51 PM PDT 24
Peak memory 218028 kb
Host smart-b9218f65-2dfb-4640-b440-3827c13f93b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633642410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2633642410
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.841652932
Short name T564
Test name
Test status
Simulation time 452388181 ps
CPU time 16.33 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:57 PM PDT 24
Peak memory 218016 kb
Host smart-f4515b66-8b3c-47ea-82ca-c4cf56755543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841652932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.841652932
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1327288177
Short name T68
Test name
Test status
Simulation time 1087093673 ps
CPU time 7.94 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 218036 kb
Host smart-6de99a16-5c7f-4416-8541-949d637e37da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327288177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1327288177
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.942165758
Short name T356
Test name
Test status
Simulation time 245842156 ps
CPU time 10.04 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 218148 kb
Host smart-17cecbae-3b09-40e0-9d23-f52007e4dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942165758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.942165758
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.203759808
Short name T721
Test name
Test status
Simulation time 69172026 ps
CPU time 2.32 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 214296 kb
Host smart-ef39ed3d-1b5c-4225-b388-92c2bc4c8bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203759808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.203759808
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3079462766
Short name T264
Test name
Test status
Simulation time 292969699 ps
CPU time 30.88 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 251032 kb
Host smart-a6528a23-271c-4914-8c09-b9bd45086363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079462766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3079462766
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.432445724
Short name T800
Test name
Test status
Simulation time 68442777 ps
CPU time 7.93 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:50 PM PDT 24
Peak memory 250964 kb
Host smart-ca77f15e-c23b-40ca-b7af-52b80e5e1ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432445724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.432445724
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2869960240
Short name T566
Test name
Test status
Simulation time 937230634 ps
CPU time 27.59 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:51:05 PM PDT 24
Peak memory 225512 kb
Host smart-7b4cee3a-8427-4400-ba0a-e90ecb93836c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869960240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2869960240
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3439799131
Short name T527
Test name
Test status
Simulation time 100374416 ps
CPU time 1.06 seconds
Started May 28 02:50:29 PM PDT 24
Finished May 28 02:50:36 PM PDT 24
Peak memory 211640 kb
Host smart-69fad05e-2ee7-4238-a024-19e8abf2538e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439799131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3439799131
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.630312830
Short name T580
Test name
Test status
Simulation time 60555292 ps
CPU time 0.86 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 209680 kb
Host smart-ce4d32a7-141a-4be9-9bea-c54fc674e603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630312830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.630312830
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1192245265
Short name T256
Test name
Test status
Simulation time 198798697 ps
CPU time 10.96 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 218168 kb
Host smart-8c14d8e7-06fa-453d-b57e-8db16bb033bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192245265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1192245265
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.332821592
Short name T571
Test name
Test status
Simulation time 3661602327 ps
CPU time 4.62 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:53 PM PDT 24
Peak memory 209564 kb
Host smart-d9b412e6-d052-46f4-a9eb-ce921b8e2274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332821592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.332821592
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1704101687
Short name T319
Test name
Test status
Simulation time 28578234 ps
CPU time 1.89 seconds
Started May 28 02:50:34 PM PDT 24
Finished May 28 02:50:43 PM PDT 24
Peak memory 218176 kb
Host smart-a403848a-6e75-4cfa-a03e-a114a84e59d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704101687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1704101687
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2265049101
Short name T847
Test name
Test status
Simulation time 500228739 ps
CPU time 13.48 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 226180 kb
Host smart-acbf9321-f098-4294-aa60-25ac9ea72f69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265049101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2265049101
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2901674066
Short name T603
Test name
Test status
Simulation time 512744330 ps
CPU time 10.29 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:57 PM PDT 24
Peak memory 218044 kb
Host smart-db29058f-7f1f-4e30-9d0a-b913ec80d562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901674066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2901674066
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2554999720
Short name T598
Test name
Test status
Simulation time 1035562366 ps
CPU time 7.34 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 218064 kb
Host smart-849a10a7-7972-413a-b6eb-d84fdaa8e945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554999720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2554999720
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1495531720
Short name T687
Test name
Test status
Simulation time 120779610 ps
CPU time 2.57 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 214440 kb
Host smart-79ae93a6-5168-4195-877d-85d572beda0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495531720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1495531720
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1888978584
Short name T630
Test name
Test status
Simulation time 365047209 ps
CPU time 29.4 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:51:13 PM PDT 24
Peak memory 251040 kb
Host smart-b7fe7265-ea16-46bf-94a1-cf67e541c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888978584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1888978584
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3563241983
Short name T540
Test name
Test status
Simulation time 320813270 ps
CPU time 3.51 seconds
Started May 28 02:50:30 PM PDT 24
Finished May 28 02:50:40 PM PDT 24
Peak memory 222072 kb
Host smart-ce7cc9ad-2c15-4899-acc7-f8460e2ee065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563241983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3563241983
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4069782135
Short name T799
Test name
Test status
Simulation time 20650219969 ps
CPU time 138.89 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:53:06 PM PDT 24
Peak memory 271276 kb
Host smart-abe58cc9-857e-4705-a208-f1051fa1c67b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069782135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4069782135
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.26780127
Short name T147
Test name
Test status
Simulation time 134318780057 ps
CPU time 423.79 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:57:50 PM PDT 24
Peak memory 333116 kb
Host smart-bcf16064-799d-4d77-8898-053f1d1517b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=26780127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.26780127
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1292327403
Short name T285
Test name
Test status
Simulation time 12961854 ps
CPU time 1.05 seconds
Started May 28 02:50:33 PM PDT 24
Finished May 28 02:50:40 PM PDT 24
Peak memory 211716 kb
Host smart-be7ba0da-f3c4-42a4-96cb-99a7644e9307
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292327403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1292327403
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3942019308
Short name T434
Test name
Test status
Simulation time 16521182 ps
CPU time 1 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 209668 kb
Host smart-56f6caf8-67f8-4360-9c93-1b12e48ff986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942019308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3942019308
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3964482074
Short name T462
Test name
Test status
Simulation time 225314479 ps
CPU time 9.64 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 218072 kb
Host smart-18684ac1-d681-49e4-acad-a6c0acec761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964482074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3964482074
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3134171780
Short name T29
Test name
Test status
Simulation time 386898188 ps
CPU time 10.35 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 209632 kb
Host smart-6cc7b915-856f-41e7-99f0-bd3c96dfca0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134171780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3134171780
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1994321022
Short name T51
Test name
Test status
Simulation time 3844995923 ps
CPU time 45.59 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 219176 kb
Host smart-b2652306-012b-4610-bf2b-b50d59f63ae1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994321022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1994321022
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2343549216
Short name T479
Test name
Test status
Simulation time 1249734066 ps
CPU time 12.02 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 217868 kb
Host smart-de9ddcc6-f706-4cff-ae97-72a98fa76b20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343549216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
343549216
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3938058882
Short name T484
Test name
Test status
Simulation time 559657562 ps
CPU time 4.89 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:19 PM PDT 24
Peak memory 218024 kb
Host smart-b5e22c98-5fe6-483e-b551-7b24784b1afb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938058882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3938058882
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3786358735
Short name T385
Test name
Test status
Simulation time 1308965285 ps
CPU time 11.46 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:27 PM PDT 24
Peak memory 213116 kb
Host smart-f0508657-6799-4efb-9e65-7d921779f01d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786358735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3786358735
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3380029670
Short name T250
Test name
Test status
Simulation time 912953398 ps
CPU time 3.62 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:19 PM PDT 24
Peak memory 213348 kb
Host smart-b4d83ce8-10be-4785-95b1-6260ffb36593
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380029670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3380029670
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1269298734
Short name T704
Test name
Test status
Simulation time 4100665151 ps
CPU time 34.58 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 267388 kb
Host smart-f2cf68cb-cb3d-4fdb-96c4-efdae62b4b2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269298734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1269298734
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1956825743
Short name T733
Test name
Test status
Simulation time 335236798 ps
CPU time 14.98 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 247868 kb
Host smart-bf85c8a7-1057-42b0-a56e-af64061c4eaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956825743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1956825743
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1420569420
Short name T638
Test name
Test status
Simulation time 522188517 ps
CPU time 3.18 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 218104 kb
Host smart-23b0e7bb-42c1-4293-810f-5b5a91d82ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420569420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1420569420
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.65486749
Short name T719
Test name
Test status
Simulation time 224309636 ps
CPU time 8.22 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:23 PM PDT 24
Peak memory 222304 kb
Host smart-b04c6a1c-58b8-48b7-8876-5afa1c464a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65486749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.65486749
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1368742833
Short name T851
Test name
Test status
Simulation time 194526654 ps
CPU time 10.62 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 217744 kb
Host smart-62aef8a6-e7a1-4b15-888d-ab89f03f0ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368742833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1368742833
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1271978252
Short name T387
Test name
Test status
Simulation time 1461177378 ps
CPU time 12.83 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 218036 kb
Host smart-732c5179-4f9d-4141-893b-02fb6645fce4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271978252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1271978252
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3303574291
Short name T713
Test name
Test status
Simulation time 270447254 ps
CPU time 10.96 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 218056 kb
Host smart-6ca4ebd6-b089-47de-b3d4-49ee7575ab19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303574291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
303574291
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2540644193
Short name T62
Test name
Test status
Simulation time 3066220293 ps
CPU time 6.89 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 218228 kb
Host smart-5358727f-4941-4760-9486-1a704e32d311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540644193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2540644193
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3767306604
Short name T615
Test name
Test status
Simulation time 32379143 ps
CPU time 1.32 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 213364 kb
Host smart-e71c69d4-5ce9-42b0-a38b-64c36c3070aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767306604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3767306604
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.373154707
Short name T406
Test name
Test status
Simulation time 1055271771 ps
CPU time 27.7 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 251000 kb
Host smart-9fe8fafe-0ae8-4c4f-9a2e-c956c3ba9801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373154707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.373154707
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2796074016
Short name T795
Test name
Test status
Simulation time 102887909 ps
CPU time 8.31 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 250996 kb
Host smart-f00e4950-ffdc-4790-a371-64e5c11060f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796074016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2796074016
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3829801884
Short name T805
Test name
Test status
Simulation time 2726538267 ps
CPU time 92.57 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 279472 kb
Host smart-c0789783-39f7-47d9-acc4-f5a793fe7540
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829801884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3829801884
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3948467419
Short name T297
Test name
Test status
Simulation time 14176523 ps
CPU time 1.13 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 211708 kb
Host smart-d79cb093-d6cf-4856-a905-9012a289725e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948467419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3948467419
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1294660271
Short name T340
Test name
Test status
Simulation time 18829679 ps
CPU time 1.01 seconds
Started May 28 02:50:40 PM PDT 24
Finished May 28 02:50:50 PM PDT 24
Peak memory 209696 kb
Host smart-456b71a2-427c-4241-b32b-ca06a679a2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294660271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1294660271
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2944278850
Short name T408
Test name
Test status
Simulation time 230436019 ps
CPU time 10.7 seconds
Started May 28 02:50:34 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 218084 kb
Host smart-1f24459f-5127-4d74-986a-fb7c98a7f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944278850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2944278850
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2543175164
Short name T720
Test name
Test status
Simulation time 1292499692 ps
CPU time 7.54 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:53 PM PDT 24
Peak memory 209616 kb
Host smart-61832ac6-9259-4705-a9ab-a8c1616796c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543175164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2543175164
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1074369731
Short name T363
Test name
Test status
Simulation time 42944011 ps
CPU time 1.51 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:44 PM PDT 24
Peak memory 218096 kb
Host smart-77edc85b-083f-49ef-9ae4-c85f501ba208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074369731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1074369731
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1626794600
Short name T107
Test name
Test status
Simulation time 2553455029 ps
CPU time 15.88 seconds
Started May 28 02:50:35 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 219112 kb
Host smart-52d7d15e-6bd6-4c99-9b3a-c5e731c8e899
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626794600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1626794600
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.769765897
Short name T474
Test name
Test status
Simulation time 1799010844 ps
CPU time 15.81 seconds
Started May 28 02:50:40 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 218056 kb
Host smart-7a44598f-7026-4cfc-9efe-d72f529f7dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769765897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.769765897
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3600321627
Short name T444
Test name
Test status
Simulation time 4023881456 ps
CPU time 7.01 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 218052 kb
Host smart-cdd8094a-42c7-4c0b-a479-89fca61106ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600321627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3600321627
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3757447958
Short name T312
Test name
Test status
Simulation time 1029146332 ps
CPU time 9.66 seconds
Started May 28 02:50:40 PM PDT 24
Finished May 28 02:50:59 PM PDT 24
Peak memory 218144 kb
Host smart-242c6b80-3b43-477e-867f-7089c066d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757447958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3757447958
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2608129576
Short name T718
Test name
Test status
Simulation time 56234598 ps
CPU time 3.5 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 214880 kb
Host smart-5c9a724e-e27e-4fca-bb45-47354d5d5269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608129576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2608129576
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3484473856
Short name T423
Test name
Test status
Simulation time 955299536 ps
CPU time 30.13 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:51:15 PM PDT 24
Peak memory 251124 kb
Host smart-d257cb26-f527-4dc9-a41a-37fe4403e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484473856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3484473856
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2176423700
Short name T26
Test name
Test status
Simulation time 82215440 ps
CPU time 6.83 seconds
Started May 28 02:50:34 PM PDT 24
Finished May 28 02:50:48 PM PDT 24
Peak memory 251024 kb
Host smart-ed60206a-f20d-426c-a92c-8a90d51b8755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176423700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2176423700
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.435689148
Short name T66
Test name
Test status
Simulation time 1513522753 ps
CPU time 30.16 seconds
Started May 28 02:50:36 PM PDT 24
Finished May 28 02:51:13 PM PDT 24
Peak memory 215396 kb
Host smart-7e810eda-03e2-44c0-928b-f0b04990db59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435689148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.435689148
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.514436545
Short name T857
Test name
Test status
Simulation time 12429264 ps
CPU time 0.81 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:46 PM PDT 24
Peak memory 208788 kb
Host smart-cf271d3c-8437-47f8-9e03-c90fe5f2e2c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514436545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.514436545
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3657306657
Short name T95
Test name
Test status
Simulation time 21853796 ps
CPU time 1.23 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:50 PM PDT 24
Peak memory 209704 kb
Host smart-a8e79b4b-2a8e-4aa0-a009-0966d0124a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657306657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3657306657
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3829169995
Short name T425
Test name
Test status
Simulation time 1597304605 ps
CPU time 16.99 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 218104 kb
Host smart-e7fcddf0-00cf-4c50-a797-173ed3fac2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829169995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3829169995
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3772021478
Short name T494
Test name
Test status
Simulation time 376633509 ps
CPU time 8.69 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 209648 kb
Host smart-fc9c93ce-1546-4a35-87c8-8243575045c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772021478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3772021478
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3003307916
Short name T255
Test name
Test status
Simulation time 131949116 ps
CPU time 3.13 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 218084 kb
Host smart-50580c04-ef57-4b9b-9adf-17bcb18aff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003307916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3003307916
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.500016469
Short name T327
Test name
Test status
Simulation time 283480355 ps
CPU time 12.89 seconds
Started May 28 02:50:37 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 218176 kb
Host smart-41585cdd-315d-459d-abe4-67265640452c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500016469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.500016469
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3534150232
Short name T505
Test name
Test status
Simulation time 307550444 ps
CPU time 11.51 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 218052 kb
Host smart-0e2ca0c8-00eb-4dcc-919b-c1f52217834a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534150232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3534150232
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3423899736
Short name T838
Test name
Test status
Simulation time 307661306 ps
CPU time 7.74 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 218052 kb
Host smart-37c04cea-6fa6-453f-afa9-c99a8682be3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423899736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3423899736
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.267688795
Short name T42
Test name
Test status
Simulation time 331013067 ps
CPU time 7.8 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 218148 kb
Host smart-cfd919a4-cde7-43d2-97a7-c9bf4b02b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267688795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.267688795
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.57708474
Short name T466
Test name
Test status
Simulation time 102541586 ps
CPU time 3.29 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 217816 kb
Host smart-409b09be-841f-4d32-8a55-75914e34e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57708474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.57708474
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3909606894
Short name T412
Test name
Test status
Simulation time 172863038 ps
CPU time 3.08 seconds
Started May 28 02:50:38 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 222564 kb
Host smart-0c8786e5-a6f4-473a-a948-b34cf9c228f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909606894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3909606894
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2851852421
Short name T515
Test name
Test status
Simulation time 14605588499 ps
CPU time 100.67 seconds
Started May 28 02:50:41 PM PDT 24
Finished May 28 02:52:32 PM PDT 24
Peak memory 283836 kb
Host smart-b7d080cb-b217-47b4-8a46-680a90dd97cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851852421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2851852421
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3568879091
Short name T41
Test name
Test status
Simulation time 14982340 ps
CPU time 0.83 seconds
Started May 28 02:50:36 PM PDT 24
Finished May 28 02:50:44 PM PDT 24
Peak memory 208796 kb
Host smart-9f772be0-8fbc-4956-9153-131ed2ed1708
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568879091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3568879091
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3428951942
Short name T351
Test name
Test status
Simulation time 30247153 ps
CPU time 1.14 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 209648 kb
Host smart-b07c011d-dc82-4dd0-b234-5e4404bb5892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428951942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3428951942
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3779062700
Short name T694
Test name
Test status
Simulation time 303309988 ps
CPU time 13.95 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:51:02 PM PDT 24
Peak memory 218100 kb
Host smart-72a0b85d-1053-4c04-a45e-851e75e6e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779062700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3779062700
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.196727560
Short name T779
Test name
Test status
Simulation time 226269312 ps
CPU time 3.25 seconds
Started May 28 02:50:26 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 209696 kb
Host smart-a9ad9bcd-3571-4d96-9e9f-4fd89b72ea49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196727560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.196727560
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1003503117
Short name T761
Test name
Test status
Simulation time 78742021 ps
CPU time 2.44 seconds
Started May 28 02:50:41 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 218204 kb
Host smart-c03dca2a-3114-4d9e-87b1-e9f0f100798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003503117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1003503117
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.336987816
Short name T655
Test name
Test status
Simulation time 606947263 ps
CPU time 10.51 seconds
Started May 28 02:50:28 PM PDT 24
Finished May 28 02:50:44 PM PDT 24
Peak memory 218116 kb
Host smart-d810732c-86cf-4791-af6f-a5eabb9dd62f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336987816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.336987816
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.623881208
Short name T722
Test name
Test status
Simulation time 883788795 ps
CPU time 13.93 seconds
Started May 28 02:50:27 PM PDT 24
Finished May 28 02:50:46 PM PDT 24
Peak memory 226140 kb
Host smart-4d44518f-5673-439b-b527-4fc25d8e82c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623881208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.623881208
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3355792616
Short name T226
Test name
Test status
Simulation time 3279018811 ps
CPU time 8.4 seconds
Started May 28 02:50:31 PM PDT 24
Finished May 28 02:50:45 PM PDT 24
Peak memory 218120 kb
Host smart-b3fbb0dc-f7bb-4be2-8eae-4b07b6932e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355792616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3355792616
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3866062585
Short name T461
Test name
Test status
Simulation time 2110123068 ps
CPU time 10.35 seconds
Started May 28 02:50:26 PM PDT 24
Finished May 28 02:50:42 PM PDT 24
Peak memory 218184 kb
Host smart-86409c0a-376f-4c4e-b272-02dfd73ab5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866062585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3866062585
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4275704499
Short name T332
Test name
Test status
Simulation time 155135969 ps
CPU time 2.55 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:51 PM PDT 24
Peak memory 213608 kb
Host smart-3c3b6fe3-a8d4-4bce-9970-0511de84b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275704499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4275704499
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3651338758
Short name T858
Test name
Test status
Simulation time 272395761 ps
CPU time 30.35 seconds
Started May 28 02:50:40 PM PDT 24
Finished May 28 02:51:20 PM PDT 24
Peak memory 246316 kb
Host smart-4e53a910-0164-4acb-b85d-80a69ce9ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651338758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3651338758
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4057103695
Short name T595
Test name
Test status
Simulation time 941637282 ps
CPU time 6.73 seconds
Started May 28 02:50:41 PM PDT 24
Finished May 28 02:50:57 PM PDT 24
Peak memory 246852 kb
Host smart-6f1c4924-458c-402d-9c7b-f98818133837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057103695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4057103695
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3504335360
Short name T533
Test name
Test status
Simulation time 41857482418 ps
CPU time 428.56 seconds
Started May 28 02:50:40 PM PDT 24
Finished May 28 02:57:58 PM PDT 24
Peak memory 267492 kb
Host smart-234e3c85-e1d1-4612-935d-054d8a470b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504335360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3504335360
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1393261161
Short name T160
Test name
Test status
Simulation time 132081110689 ps
CPU time 979.41 seconds
Started May 28 02:50:42 PM PDT 24
Finished May 28 03:07:12 PM PDT 24
Peak memory 316816 kb
Host smart-bcae6b12-0b40-4977-a384-46448b7dea50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1393261161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1393261161
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3266680842
Short name T759
Test name
Test status
Simulation time 35177802 ps
CPU time 0.85 seconds
Started May 28 02:50:39 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 208608 kb
Host smart-d7169359-2824-4aef-b552-2afe661e7b7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266680842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3266680842
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2634154428
Short name T605
Test name
Test status
Simulation time 51123629 ps
CPU time 0.99 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 209684 kb
Host smart-15824014-3e12-4273-8e1c-fb4981172f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634154428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2634154428
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.420613115
Short name T807
Test name
Test status
Simulation time 1499084905 ps
CPU time 13.74 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:09 PM PDT 24
Peak memory 218092 kb
Host smart-9451f748-fc17-4865-b380-c6c71f7bea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420613115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.420613115
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2288808299
Short name T414
Test name
Test status
Simulation time 436254559 ps
CPU time 3.39 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 209436 kb
Host smart-df5e256d-9663-4d1c-ba6e-b0a80dea571d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288808299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2288808299
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1168914949
Short name T13
Test name
Test status
Simulation time 52907211 ps
CPU time 2.89 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:58 PM PDT 24
Peak memory 218128 kb
Host smart-429ed484-932c-4baa-883b-6dbc91744a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168914949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1168914949
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.219116359
Short name T168
Test name
Test status
Simulation time 328381000 ps
CPU time 13 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 219052 kb
Host smart-757f74e4-8e37-43bb-85db-ca713aa32a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219116359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.219116359
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2159655090
Short name T411
Test name
Test status
Simulation time 246024577 ps
CPU time 8.31 seconds
Started May 28 02:50:47 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 218044 kb
Host smart-84df3037-4cd8-46ef-82c2-bf568c527bef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159655090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2159655090
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2120719022
Short name T565
Test name
Test status
Simulation time 678085807 ps
CPU time 8.28 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:04 PM PDT 24
Peak memory 218092 kb
Host smart-cf99a312-8aa4-4cec-bb97-fde1445aab10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120719022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2120719022
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3402560359
Short name T809
Test name
Test status
Simulation time 43411760 ps
CPU time 1.37 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 213412 kb
Host smart-0679789b-a131-4c1f-8235-a299d65b9eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402560359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3402560359
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2471933905
Short name T767
Test name
Test status
Simulation time 1219286844 ps
CPU time 24.14 seconds
Started May 28 02:50:48 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 251032 kb
Host smart-ef704eb5-1c94-41bd-af52-672dcd12ff40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471933905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2471933905
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2676394778
Short name T345
Test name
Test status
Simulation time 78942854 ps
CPU time 9.9 seconds
Started May 28 02:50:41 PM PDT 24
Finished May 28 02:51:01 PM PDT 24
Peak memory 250964 kb
Host smart-9751e63f-9ba4-4367-828b-cc8b4f021241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676394778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2676394778
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.131751902
Short name T245
Test name
Test status
Simulation time 12753139504 ps
CPU time 47.78 seconds
Started May 28 02:50:42 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 228284 kb
Host smart-bc0c4426-0369-4a39-a570-0add71226047
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131751902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.131751902
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3528490500
Short name T64
Test name
Test status
Simulation time 107044104222 ps
CPU time 626.29 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 03:01:22 PM PDT 24
Peak memory 316780 kb
Host smart-aa74031a-523a-4ed1-9cd5-5af36400bf85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3528490500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3528490500
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2990066896
Short name T753
Test name
Test status
Simulation time 50548051 ps
CPU time 0.92 seconds
Started May 28 02:50:52 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 208832 kb
Host smart-1af246d1-4828-4414-982c-6611a5a926b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990066896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2990066896
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.4254834122
Short name T715
Test name
Test status
Simulation time 16955579 ps
CPU time 1.1 seconds
Started May 28 02:51:30 PM PDT 24
Finished May 28 02:51:53 PM PDT 24
Peak memory 209888 kb
Host smart-505d78b8-02f9-498a-9541-a6f96763e020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254834122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4254834122
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.657612525
Short name T322
Test name
Test status
Simulation time 1304404663 ps
CPU time 12.89 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:07 PM PDT 24
Peak memory 218160 kb
Host smart-0d988d46-4f1c-47d1-9a76-136af61fdfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657612525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.657612525
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1186242109
Short name T186
Test name
Test status
Simulation time 520769813 ps
CPU time 4.25 seconds
Started May 28 02:50:47 PM PDT 24
Finished May 28 02:51:04 PM PDT 24
Peak memory 217200 kb
Host smart-98baa4d7-fc0e-4837-847b-7bc9cb21c3d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186242109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1186242109
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3882491556
Short name T600
Test name
Test status
Simulation time 120956467 ps
CPU time 4.79 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 218144 kb
Host smart-0b8b69cc-3810-4164-a5e3-6b201fad3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882491556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3882491556
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4102343710
Short name T53
Test name
Test status
Simulation time 481186298 ps
CPU time 14.01 seconds
Started May 28 02:50:42 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 226192 kb
Host smart-ca8f6513-e134-41d0-a6f1-8c754e93b4ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102343710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4102343710
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1796960340
Short name T27
Test name
Test status
Simulation time 1107877243 ps
CPU time 12.97 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 218112 kb
Host smart-c74518eb-7c2c-44d1-be78-f02ecdde0eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796960340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1796960340
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.191897658
Short name T371
Test name
Test status
Simulation time 1273356780 ps
CPU time 8.17 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 218132 kb
Host smart-94cfe913-cd11-4459-b29d-1597c1a0899c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191897658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.191897658
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3219364496
Short name T845
Test name
Test status
Simulation time 455664217 ps
CPU time 7.23 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 218012 kb
Host smart-a0744b6d-e462-43f9-9ac8-3fcda3cd4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219364496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3219364496
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3188373048
Short name T259
Test name
Test status
Simulation time 130067539 ps
CPU time 1.48 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 213516 kb
Host smart-43f0c052-fdde-49cf-b6e3-dc97f1058023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188373048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3188373048
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.684754360
Short name T560
Test name
Test status
Simulation time 2521218807 ps
CPU time 23.09 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 246388 kb
Host smart-37f6c137-f72d-4765-a365-142b912fe88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684754360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.684754360
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3912991416
Short name T465
Test name
Test status
Simulation time 132046806 ps
CPU time 6.2 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:02 PM PDT 24
Peak memory 246536 kb
Host smart-763fbbb5-5be1-4545-a65c-163b8b56ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912991416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3912991416
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4192645218
Short name T279
Test name
Test status
Simulation time 4388984205 ps
CPU time 81.01 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:52:25 PM PDT 24
Peak memory 251344 kb
Host smart-7ef1b15b-6ad4-4be5-9835-de04beacf1cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192645218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4192645218
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3396122378
Short name T146
Test name
Test status
Simulation time 110704153169 ps
CPU time 686.44 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 03:02:23 PM PDT 24
Peak memory 372940 kb
Host smart-1b83d69d-08f4-4efe-a486-69384b192353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3396122378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3396122378
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2163020253
Short name T643
Test name
Test status
Simulation time 40897937 ps
CPU time 0.77 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:55 PM PDT 24
Peak memory 208544 kb
Host smart-cee5d16b-e7ad-49d6-bf3c-ddfd552648b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163020253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2163020253
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4020420791
Short name T82
Test name
Test status
Simulation time 28891130 ps
CPU time 0.89 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:09 PM PDT 24
Peak memory 209648 kb
Host smart-2f194c36-f8d6-4c10-925b-f8e28b364724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020420791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4020420791
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2795299114
Short name T6
Test name
Test status
Simulation time 1444233500 ps
CPU time 5.25 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:09 PM PDT 24
Peak memory 217012 kb
Host smart-7cdf341d-d65f-4a03-9d43-49fd27b82b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795299114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2795299114
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1899665207
Short name T24
Test name
Test status
Simulation time 216684229 ps
CPU time 2.83 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 218172 kb
Host smart-d0446daf-1d80-4d90-8708-4861bdf77f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899665207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1899665207
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2748857154
Short name T775
Test name
Test status
Simulation time 221549207 ps
CPU time 9.1 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:05 PM PDT 24
Peak memory 219236 kb
Host smart-533abed8-7f6d-432a-870f-711450744612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748857154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2748857154
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2927715028
Short name T293
Test name
Test status
Simulation time 2649875794 ps
CPU time 22.01 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:26 PM PDT 24
Peak memory 218040 kb
Host smart-fda56a48-47cf-4dc4-8388-e56ae7e68ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927715028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2927715028
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2006633203
Short name T251
Test name
Test status
Simulation time 285760336 ps
CPU time 10.76 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 218048 kb
Host smart-c89e336d-ca80-4868-8e8d-4b9c167cfce0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006633203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2006633203
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4285660970
Short name T742
Test name
Test status
Simulation time 1743381560 ps
CPU time 12.18 seconds
Started May 28 02:50:47 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 218200 kb
Host smart-15a16a32-c39a-4a16-bc42-57d75cefcdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285660970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4285660970
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1975739032
Short name T74
Test name
Test status
Simulation time 48345798 ps
CPU time 3.39 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 214760 kb
Host smart-7860efd4-7fcc-4c2f-bfc5-8cc5c11d6c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975739032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1975739032
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4154028320
Short name T762
Test name
Test status
Simulation time 883128436 ps
CPU time 22.56 seconds
Started May 28 02:50:49 PM PDT 24
Finished May 28 02:51:24 PM PDT 24
Peak memory 251032 kb
Host smart-20f391b4-7e64-4092-9bce-3478f6900832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154028320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4154028320
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.795364315
Short name T756
Test name
Test status
Simulation time 207681052 ps
CPU time 7.79 seconds
Started May 28 02:51:31 PM PDT 24
Finished May 28 02:51:59 PM PDT 24
Peak memory 251216 kb
Host smart-7370c527-28f3-43c7-91dc-2d838cb6fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795364315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.795364315
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2855525519
Short name T181
Test name
Test status
Simulation time 124192423419 ps
CPU time 197.79 seconds
Started May 28 02:50:49 PM PDT 24
Finished May 28 02:54:19 PM PDT 24
Peak memory 275876 kb
Host smart-988b5dd5-daea-4b9e-a153-3a50066804cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855525519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2855525519
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.838582043
Short name T419
Test name
Test status
Simulation time 12655352 ps
CPU time 0.93 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:05 PM PDT 24
Peak memory 208700 kb
Host smart-d3e8410d-58e0-42f7-a6fa-0b2d1a07df09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838582043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.838582043
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2774475435
Short name T331
Test name
Test status
Simulation time 16799862 ps
CPU time 1.11 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:54 PM PDT 24
Peak memory 209660 kb
Host smart-c66d9183-f755-487b-a259-497b3b894bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774475435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2774475435
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.43059177
Short name T4
Test name
Test status
Simulation time 409513531 ps
CPU time 14.27 seconds
Started May 28 02:50:47 PM PDT 24
Finished May 28 02:51:14 PM PDT 24
Peak memory 218124 kb
Host smart-624db916-6cc4-41d9-8ea1-142c96e8ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43059177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.43059177
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2018718263
Short name T9
Test name
Test status
Simulation time 394066488 ps
CPU time 5.27 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:09 PM PDT 24
Peak memory 209556 kb
Host smart-59bdc0ec-338e-493f-89cb-37b30f8e4935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018718263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2018718263
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2913000927
Short name T296
Test name
Test status
Simulation time 452468306 ps
CPU time 4.56 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:10 PM PDT 24
Peak memory 218048 kb
Host smart-9e0868c0-f406-4102-b22b-06ac6161ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913000927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2913000927
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2261401389
Short name T506
Test name
Test status
Simulation time 3265304509 ps
CPU time 21.82 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:26 PM PDT 24
Peak memory 226268 kb
Host smart-41fc6620-d123-4298-87d6-587c28d28b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261401389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2261401389
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3687330873
Short name T634
Test name
Test status
Simulation time 570060610 ps
CPU time 12.01 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:16 PM PDT 24
Peak memory 218040 kb
Host smart-dbe9b82b-4646-4ec4-b28d-c69d51c3dec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687330873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3687330873
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.926781262
Short name T848
Test name
Test status
Simulation time 724223154 ps
CPU time 13.73 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:18 PM PDT 24
Peak memory 218128 kb
Host smart-ed57ace3-2d10-4b76-9207-5bc0abc7c6d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926781262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.926781262
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3231991636
Short name T599
Test name
Test status
Simulation time 370112156 ps
CPU time 7.68 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 218164 kb
Host smart-0e1d47df-99ac-4a5f-8dbb-e9aa9eab14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231991636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3231991636
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1026300703
Short name T313
Test name
Test status
Simulation time 1041078030 ps
CPU time 2.58 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:57 PM PDT 24
Peak memory 213728 kb
Host smart-df02dfdd-87ad-470e-8de0-735645fcd8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026300703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1026300703
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3789700968
Short name T375
Test name
Test status
Simulation time 355179208 ps
CPU time 28.5 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 250948 kb
Host smart-348f0f5b-5c1a-47e8-b52c-3277cb32e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789700968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3789700968
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2941811035
Short name T711
Test name
Test status
Simulation time 234266883 ps
CPU time 9.96 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:15 PM PDT 24
Peak memory 251028 kb
Host smart-dd6f7835-0d49-4b8d-bbf9-9e3b302eefc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941811035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2941811035
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.593137350
Short name T792
Test name
Test status
Simulation time 35229263218 ps
CPU time 300.37 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 251088 kb
Host smart-2916c513-398b-4af0-84db-98e94b04421e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593137350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.593137350
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.894611693
Short name T439
Test name
Test status
Simulation time 15577679 ps
CPU time 0.83 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:04 PM PDT 24
Peak memory 208856 kb
Host smart-fecabafa-112f-4f86-8b1a-fe86ef431d5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894611693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.894611693
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.585084576
Short name T393
Test name
Test status
Simulation time 63404896 ps
CPU time 0.86 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:10 PM PDT 24
Peak memory 209572 kb
Host smart-c7144ead-f1d5-40d6-9faf-323de325d01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585084576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.585084576
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1635796791
Short name T657
Test name
Test status
Simulation time 655067137 ps
CPU time 12.41 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 218196 kb
Host smart-369da42f-5884-4b10-be3d-fc81a8b4db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635796791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1635796791
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3382747735
Short name T659
Test name
Test status
Simulation time 765684118 ps
CPU time 5.33 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 209652 kb
Host smart-58ddc945-2423-4453-b61f-ddea88b6a4e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382747735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3382747735
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1256367053
Short name T675
Test name
Test status
Simulation time 515374056 ps
CPU time 3.03 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:07 PM PDT 24
Peak memory 218032 kb
Host smart-ccba40b3-9cf5-4da7-b520-0a35d7e182c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256367053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1256367053
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3415625168
Short name T480
Test name
Test status
Simulation time 8899106401 ps
CPU time 22.48 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 226192 kb
Host smart-4427b38d-1b5e-47c9-9367-25169048508d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415625168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3415625168
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4079803568
Short name T153
Test name
Test status
Simulation time 615537192 ps
CPU time 12.68 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 218020 kb
Host smart-a50cfdc6-8073-4eab-b09c-4abeeb12b81b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079803568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4079803568
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1622515384
Short name T601
Test name
Test status
Simulation time 1334252097 ps
CPU time 13.33 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 218048 kb
Host smart-faf5fa1d-a93e-40a8-92de-05762dd7e44a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622515384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1622515384
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2197667242
Short name T502
Test name
Test status
Simulation time 416289621 ps
CPU time 7.95 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 218232 kb
Host smart-143c8287-b983-46af-b1a1-f5384fe7ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197667242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2197667242
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1247273444
Short name T180
Test name
Test status
Simulation time 64424779 ps
CPU time 2.87 seconds
Started May 28 02:50:49 PM PDT 24
Finished May 28 02:51:05 PM PDT 24
Peak memory 214540 kb
Host smart-dd8825c6-2064-47c2-b5cd-7606d1248a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247273444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1247273444
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3302654538
Short name T752
Test name
Test status
Simulation time 1005229365 ps
CPU time 26.52 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:30 PM PDT 24
Peak memory 247244 kb
Host smart-bf62e1be-dfa1-44cd-8688-7606eb68c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302654538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3302654538
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.468519804
Short name T370
Test name
Test status
Simulation time 72513266 ps
CPU time 3.95 seconds
Started May 28 02:50:50 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 222688 kb
Host smart-fe082a2b-f2ea-49b7-82f9-06a5c24c78f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468519804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.468519804
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2719257273
Short name T184
Test name
Test status
Simulation time 1989798651 ps
CPU time 23.69 seconds
Started May 28 02:50:49 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 226192 kb
Host smart-946934fa-4678-456c-b7cb-615a373b3570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719257273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2719257273
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3517136805
Short name T39
Test name
Test status
Simulation time 15617349 ps
CPU time 0.98 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 208656 kb
Host smart-1ba7f8da-5626-44ae-ae90-f349a374f37c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517136805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3517136805
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.760424669
Short name T798
Test name
Test status
Simulation time 52196081 ps
CPU time 0.95 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:09 PM PDT 24
Peak memory 209684 kb
Host smart-aed37366-d885-4993-89ab-f44d54270fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760424669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.760424669
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.685690326
Short name T724
Test name
Test status
Simulation time 1100279143 ps
CPU time 13.29 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:42 PM PDT 24
Peak memory 218156 kb
Host smart-b88ca6bc-5427-4670-a87d-afb1f5a9cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685690326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.685690326
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.754864824
Short name T475
Test name
Test status
Simulation time 4679868471 ps
CPU time 22.88 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 209680 kb
Host smart-2f8fe546-843f-4f6b-bb67-a94a9621487f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754864824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.754864824
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2791485922
Short name T509
Test name
Test status
Simulation time 65571634 ps
CPU time 2.96 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 217988 kb
Host smart-7254f0b2-1651-4e61-a7c4-5e81e87c8c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791485922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2791485922
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1995448887
Short name T467
Test name
Test status
Simulation time 1166227008 ps
CPU time 13.87 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:31 PM PDT 24
Peak memory 226196 kb
Host smart-af2a3094-7979-4cd6-9bdd-2510a1b7435e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995448887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1995448887
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2711899763
Short name T678
Test name
Test status
Simulation time 1611267212 ps
CPU time 15.43 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 218040 kb
Host smart-75d01655-d290-403f-a2f9-2ad3feac7693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711899763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2711899763
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.502687043
Short name T664
Test name
Test status
Simulation time 5964574193 ps
CPU time 11.18 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 218120 kb
Host smart-1328344b-852a-4883-b5bd-802f7febd1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502687043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.502687043
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3937127747
Short name T495
Test name
Test status
Simulation time 373326852 ps
CPU time 8.55 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 218012 kb
Host smart-53e0ce1f-8c10-453c-875a-62ef855606c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937127747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3937127747
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3320754414
Short name T84
Test name
Test status
Simulation time 19643606 ps
CPU time 1.47 seconds
Started May 28 02:50:51 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 213256 kb
Host smart-13af7190-2d17-4071-bf43-d4a89045fce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320754414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3320754414
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.514567958
Short name T369
Test name
Test status
Simulation time 373084932 ps
CPU time 26.73 seconds
Started May 28 02:50:44 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 251004 kb
Host smart-b6df402c-a6eb-43b3-9d8a-64be98c1f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514567958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.514567958
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3248055068
Short name T171
Test name
Test status
Simulation time 134327098 ps
CPU time 2.94 seconds
Started May 28 02:50:45 PM PDT 24
Finished May 28 02:51:00 PM PDT 24
Peak memory 222388 kb
Host smart-feb0b241-bcd9-4cf4-81a6-9e5c23a3b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248055068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3248055068
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1988713740
Short name T562
Test name
Test status
Simulation time 15899437127 ps
CPU time 104.05 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:52:53 PM PDT 24
Peak memory 251168 kb
Host smart-dcbcb3bc-a41c-44c2-9535-76f5a1f8e04d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988713740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1988713740
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.6635446
Short name T159
Test name
Test status
Simulation time 103367325508 ps
CPU time 1043.77 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 03:08:32 PM PDT 24
Peak memory 373048 kb
Host smart-e8b574e5-eb68-4904-940d-7a4d297f1490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=6635446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.6635446
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2290204129
Short name T575
Test name
Test status
Simulation time 70060102 ps
CPU time 1.18 seconds
Started May 28 02:50:43 PM PDT 24
Finished May 28 02:50:56 PM PDT 24
Peak memory 212868 kb
Host smart-9e1e9d8d-dac1-40e8-92dd-f490cb8a236a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290204129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2290204129
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.408473167
Short name T270
Test name
Test status
Simulation time 93752035 ps
CPU time 0.93 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 209672 kb
Host smart-aa5b8fb4-8658-40b6-b578-bfb7336df206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408473167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.408473167
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3126266987
Short name T56
Test name
Test status
Simulation time 691652554 ps
CPU time 9.26 seconds
Started May 28 02:51:05 PM PDT 24
Finished May 28 02:51:34 PM PDT 24
Peak memory 218100 kb
Host smart-5e6d03ad-3e62-4a57-b428-d1fa1daf5bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126266987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3126266987
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2109623855
Short name T492
Test name
Test status
Simulation time 68122026 ps
CPU time 2.49 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:51:13 PM PDT 24
Peak memory 216980 kb
Host smart-3983debd-9fe1-4202-be3b-d700f16c8d68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109623855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2109623855
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1460394017
Short name T545
Test name
Test status
Simulation time 126727046 ps
CPU time 2.54 seconds
Started May 28 02:51:04 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 218032 kb
Host smart-88128ee6-7e98-4c87-9932-46125dfca15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460394017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1460394017
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.21812582
Short name T556
Test name
Test status
Simulation time 5492528464 ps
CPU time 18.44 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:44 PM PDT 24
Peak memory 219368 kb
Host smart-406aa25e-059f-4a70-9e9e-a514a5afeaf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.21812582
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.861688337
Short name T249
Test name
Test status
Simulation time 636423338 ps
CPU time 14.03 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218000 kb
Host smart-67626427-de0d-42df-a6eb-8c3018380641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861688337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.861688337
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3758241728
Short name T616
Test name
Test status
Simulation time 2044305954 ps
CPU time 11.16 seconds
Started May 28 02:51:01 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 218116 kb
Host smart-d6462118-bdfd-4719-a5af-7541a24542a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758241728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3758241728
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2548374704
Short name T584
Test name
Test status
Simulation time 825995150 ps
CPU time 14.98 seconds
Started May 28 02:51:01 PM PDT 24
Finished May 28 02:51:36 PM PDT 24
Peak memory 218228 kb
Host smart-65d185eb-0b7e-45f4-824c-ff76138bcb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548374704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2548374704
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3866847257
Short name T70
Test name
Test status
Simulation time 43141310 ps
CPU time 3.09 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:51:35 PM PDT 24
Peak memory 214772 kb
Host smart-5608305e-3d6e-46ca-96ab-df8508f8ed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866847257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3866847257
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2930514124
Short name T764
Test name
Test status
Simulation time 1610504690 ps
CPU time 20.34 seconds
Started May 28 02:50:56 PM PDT 24
Finished May 28 02:51:31 PM PDT 24
Peak memory 251036 kb
Host smart-96f79b42-1e53-4d44-b14b-cbd2032e88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930514124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2930514124
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.391288344
Short name T649
Test name
Test status
Simulation time 81360737 ps
CPU time 6.33 seconds
Started May 28 02:51:05 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 250440 kb
Host smart-a844d14a-3cbc-4c78-9842-923029500fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391288344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.391288344
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2069860084
Short name T589
Test name
Test status
Simulation time 135182782054 ps
CPU time 908.83 seconds
Started May 28 02:51:08 PM PDT 24
Finished May 28 03:06:37 PM PDT 24
Peak memory 529828 kb
Host smart-cb7097e4-495e-4864-bf46-400e3b5cd78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2069860084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2069860084
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1696615082
Short name T708
Test name
Test status
Simulation time 38222207 ps
CPU time 0.95 seconds
Started May 28 02:51:07 PM PDT 24
Finished May 28 02:51:28 PM PDT 24
Peak memory 211660 kb
Host smart-1f82cecf-5125-4f25-8b58-402d9a49371d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696615082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1696615082
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2301494071
Short name T843
Test name
Test status
Simulation time 67495643 ps
CPU time 0.88 seconds
Started May 28 02:49:08 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 209680 kb
Host smart-037b7dae-ce41-455d-ab4e-ab16e0202342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301494071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2301494071
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1690089841
Short name T727
Test name
Test status
Simulation time 14407331 ps
CPU time 0.85 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 209540 kb
Host smart-111f2eea-94d5-4813-b951-06df2a7e5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690089841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1690089841
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.689155673
Short name T747
Test name
Test status
Simulation time 2022851824 ps
CPU time 17.6 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:33 PM PDT 24
Peak memory 218096 kb
Host smart-af89a441-8ab3-4fe6-8acb-50a9265bc66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689155673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.689155673
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1763553214
Short name T404
Test name
Test status
Simulation time 4568583969 ps
CPU time 13.94 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:30 PM PDT 24
Peak memory 209656 kb
Host smart-1710efc0-47fc-411f-93ab-14e6d4dcfcb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763553214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1763553214
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2453846704
Short name T158
Test name
Test status
Simulation time 16719711014 ps
CPU time 22.86 seconds
Started May 28 02:49:09 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 218180 kb
Host smart-b3833832-b0f6-4e46-8b82-e27f968255fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453846704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2453846704
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4239124953
Short name T311
Test name
Test status
Simulation time 76702636 ps
CPU time 2.7 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 217868 kb
Host smart-10c5bed5-7f6d-4521-bb38-bbbf69e3251e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239124953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.4
239124953
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4074578968
Short name T436
Test name
Test status
Simulation time 221926665 ps
CPU time 7.19 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:23 PM PDT 24
Peak memory 218044 kb
Host smart-c8201ff5-b768-468c-b1d6-b1935941b4d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074578968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4074578968
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1151688252
Short name T239
Test name
Test status
Simulation time 2855044770 ps
CPU time 19.27 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:33 PM PDT 24
Peak memory 213780 kb
Host smart-99677ccb-8969-4d5f-980a-0d365d1d203a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151688252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1151688252
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2967607890
Short name T420
Test name
Test status
Simulation time 371171570 ps
CPU time 5.81 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:21 PM PDT 24
Peak memory 213900 kb
Host smart-b8aa9845-1afd-44d8-8c1d-af0480b65595
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967607890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2967607890
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3415994338
Short name T839
Test name
Test status
Simulation time 3826733488 ps
CPU time 24.1 seconds
Started May 28 02:49:09 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 251028 kb
Host smart-73557698-51ef-4942-9edf-0127c71557a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415994338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3415994338
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4268048586
Short name T286
Test name
Test status
Simulation time 339870050 ps
CPU time 15.24 seconds
Started May 28 02:49:08 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 250468 kb
Host smart-7547b6b0-0c93-419a-82a4-617ee372c887
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268048586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4268048586
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2680574177
Short name T431
Test name
Test status
Simulation time 107665352 ps
CPU time 2.81 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:19 PM PDT 24
Peak memory 218104 kb
Host smart-020c2c4e-3baa-499e-b555-1a203fa68662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680574177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2680574177
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2505654437
Short name T85
Test name
Test status
Simulation time 292798625 ps
CPU time 12.06 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 217984 kb
Host smart-5c730dbe-cd87-4755-9344-89ddfc6c082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505654437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2505654437
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1379329896
Short name T59
Test name
Test status
Simulation time 536714693 ps
CPU time 26.55 seconds
Started May 28 02:49:04 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 282396 kb
Host smart-9c62f8fa-3bdc-40f4-baee-660460ec2374
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379329896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1379329896
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2728499191
Short name T350
Test name
Test status
Simulation time 165783770 ps
CPU time 8.53 seconds
Started May 28 02:49:08 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 226196 kb
Host smart-a4a24edd-5c40-47b3-98eb-ff0137d79286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728499191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2728499191
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.4216659832
Short name T586
Test name
Test status
Simulation time 727463968 ps
CPU time 11.1 seconds
Started May 28 02:49:09 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 218040 kb
Host smart-d892db6d-2cae-4b87-8f67-beb0f31bbd09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216659832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.4216659832
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3874153054
Short name T765
Test name
Test status
Simulation time 682097608 ps
CPU time 6.16 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 218064 kb
Host smart-f65fb24d-d5e5-4325-9dbe-59a3229064a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874153054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
874153054
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2538667813
Short name T693
Test name
Test status
Simulation time 286599365 ps
CPU time 7.92 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 218224 kb
Host smart-eaaaa4a3-9d5e-4f74-a9d9-b2a04b96a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538667813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2538667813
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1103827872
Short name T748
Test name
Test status
Simulation time 27434549 ps
CPU time 1.33 seconds
Started May 28 02:49:07 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 213512 kb
Host smart-dfa24ffa-e1dc-43d9-8e2d-2f2a8082ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103827872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1103827872
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.403626402
Short name T364
Test name
Test status
Simulation time 795078458 ps
CPU time 27.8 seconds
Started May 28 02:49:01 PM PDT 24
Finished May 28 02:49:39 PM PDT 24
Peak memory 251028 kb
Host smart-742a7c35-cea6-4c6d-88d4-ea7803b2bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403626402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.403626402
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4241157937
Short name T520
Test name
Test status
Simulation time 553336787 ps
CPU time 7.78 seconds
Started May 28 02:49:02 PM PDT 24
Finished May 28 02:49:20 PM PDT 24
Peak memory 247532 kb
Host smart-98821857-df5d-40d7-ac03-a7304329518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241157937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4241157937
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4265436569
Short name T55
Test name
Test status
Simulation time 14854912064 ps
CPU time 292.93 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:54:09 PM PDT 24
Peak memory 279968 kb
Host smart-86740ab5-cc39-4fe8-89c4-55e79f5a2e25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265436569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4265436569
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2901212309
Short name T365
Test name
Test status
Simulation time 16867060 ps
CPU time 1.03 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 211596 kb
Host smart-bd95006e-50dc-498a-a39e-e0ce38e7d1f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901212309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2901212309
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3568146761
Short name T179
Test name
Test status
Simulation time 22598157 ps
CPU time 0.94 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:28 PM PDT 24
Peak memory 209636 kb
Host smart-fc6cf2e3-35a5-4f34-865e-62fec79ecb3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568146761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3568146761
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3612855688
Short name T230
Test name
Test status
Simulation time 365387725 ps
CPU time 16.64 seconds
Started May 28 02:50:57 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 218024 kb
Host smart-a67633f0-350f-4b06-9672-5fa69e284633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612855688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3612855688
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1146280742
Short name T592
Test name
Test status
Simulation time 4899103310 ps
CPU time 8.47 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:17 PM PDT 24
Peak memory 209688 kb
Host smart-d4f1ca85-f9d4-486e-8ed9-9395566d9aa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146280742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1146280742
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1539941446
Short name T551
Test name
Test status
Simulation time 131910263 ps
CPU time 1.95 seconds
Started May 28 02:50:56 PM PDT 24
Finished May 28 02:51:14 PM PDT 24
Peak memory 218084 kb
Host smart-023c19ec-a845-41a0-94eb-18c80d8e7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539941446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1539941446
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.517894756
Short name T418
Test name
Test status
Simulation time 254614555 ps
CPU time 10.82 seconds
Started May 28 02:50:56 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 218084 kb
Host smart-137522c5-4e05-4dc1-b64a-65d4bb1d297e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517894756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.517894756
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2024373573
Short name T243
Test name
Test status
Simulation time 1507276912 ps
CPU time 10.21 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:37 PM PDT 24
Peak memory 218044 kb
Host smart-4660f364-7222-41ae-bfbc-36fe3770a4e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024373573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2024373573
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4141626946
Short name T407
Test name
Test status
Simulation time 801152906 ps
CPU time 16.73 seconds
Started May 28 02:50:56 PM PDT 24
Finished May 28 02:51:30 PM PDT 24
Peak memory 218136 kb
Host smart-6ba09c79-cea5-42a8-96e0-c48bfe3f2528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141626946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4141626946
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3807008143
Short name T635
Test name
Test status
Simulation time 1888167042 ps
CPU time 9.85 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:51:18 PM PDT 24
Peak memory 218140 kb
Host smart-f28d0800-9ce0-4ecd-8a3f-204bd3484a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807008143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3807008143
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1738389203
Short name T856
Test name
Test status
Simulation time 198559313 ps
CPU time 2.76 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 217876 kb
Host smart-677287d6-46bd-444c-a90d-db28cc8d6aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738389203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1738389203
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3979394019
Short name T374
Test name
Test status
Simulation time 1240993021 ps
CPU time 16.4 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 246224 kb
Host smart-48df32cc-a94a-4bc9-99ee-1f75c093d814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979394019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3979394019
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.851017637
Short name T257
Test name
Test status
Simulation time 618252581 ps
CPU time 8.27 seconds
Started May 28 02:50:52 PM PDT 24
Finished May 28 02:51:15 PM PDT 24
Peak memory 251008 kb
Host smart-f3bbbd38-699a-4f74-9abe-429a50d6e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851017637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.851017637
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2094386202
Short name T662
Test name
Test status
Simulation time 3336089329 ps
CPU time 126.22 seconds
Started May 28 02:50:53 PM PDT 24
Finished May 28 02:53:14 PM PDT 24
Peak memory 227472 kb
Host smart-9b22ae70-a37e-4f74-8478-d5bd92c35a47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094386202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2094386202
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2783213230
Short name T487
Test name
Test status
Simulation time 13961016 ps
CPU time 0.99 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 208732 kb
Host smart-3d36a311-82e0-4cb5-ab98-085f7ebcd312
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783213230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2783213230
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.963465206
Short name T386
Test name
Test status
Simulation time 18122088 ps
CPU time 0.87 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 209680 kb
Host smart-5fc5083d-8498-43e7-a641-9d66f54494d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963465206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.963465206
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2951001784
Short name T216
Test name
Test status
Simulation time 542300169 ps
CPU time 10.7 seconds
Started May 28 02:51:01 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 218116 kb
Host smart-1089ffe6-b433-4c4a-912a-a74e4af60b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951001784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2951001784
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.888540122
Short name T660
Test name
Test status
Simulation time 2768982639 ps
CPU time 9.07 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:26 PM PDT 24
Peak memory 209692 kb
Host smart-c48a5b49-895f-4598-a611-d0cd69e2ec39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888540122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.888540122
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1807882028
Short name T446
Test name
Test status
Simulation time 324178154 ps
CPU time 3.08 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:20 PM PDT 24
Peak memory 217952 kb
Host smart-070e2022-9d24-464d-8b8f-6484dd7ce9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807882028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1807882028
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1687178852
Short name T496
Test name
Test status
Simulation time 200609660 ps
CPU time 8.15 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:34 PM PDT 24
Peak memory 226192 kb
Host smart-a0a7876b-dbdf-46c4-b3bf-ab6909952874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687178852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1687178852
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2719089551
Short name T841
Test name
Test status
Simulation time 1693930828 ps
CPU time 10.1 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:37 PM PDT 24
Peak memory 218032 kb
Host smart-3b345554-ef29-4231-acbc-8eb2c2fe6c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719089551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2719089551
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2858293797
Short name T516
Test name
Test status
Simulation time 1755809650 ps
CPU time 13.63 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218036 kb
Host smart-f78b21c5-5618-4e53-a478-b6930bd35461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858293797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2858293797
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3881175007
Short name T702
Test name
Test status
Simulation time 1248895379 ps
CPU time 11.04 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:20 PM PDT 24
Peak memory 218260 kb
Host smart-e8f730a7-c40f-495b-b18f-b93a5bbff566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881175007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3881175007
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3872647925
Short name T73
Test name
Test status
Simulation time 89464037 ps
CPU time 1.38 seconds
Started May 28 02:51:06 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 213492 kb
Host smart-4cff311c-a46e-43ec-ac43-3a9b1e3d9b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872647925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3872647925
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2321724647
Short name T232
Test name
Test status
Simulation time 198646187 ps
CPU time 29.33 seconds
Started May 28 02:50:57 PM PDT 24
Finished May 28 02:51:44 PM PDT 24
Peak memory 251048 kb
Host smart-b70a409a-d094-4787-a560-0f9f19fd6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321724647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2321724647
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4226923470
Short name T36
Test name
Test status
Simulation time 282063530 ps
CPU time 6.77 seconds
Started May 28 02:50:58 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 247108 kb
Host smart-4cfc1efb-9322-43c6-bb2b-a03f9b1442fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226923470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4226923470
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2434761542
Short name T834
Test name
Test status
Simulation time 2623758775 ps
CPU time 91.29 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:52:41 PM PDT 24
Peak memory 249616 kb
Host smart-153feb32-b34b-4df5-ac9c-2b5be3667170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434761542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2434761542
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1802697547
Short name T150
Test name
Test status
Simulation time 87895160060 ps
CPU time 501.87 seconds
Started May 28 02:51:08 PM PDT 24
Finished May 28 02:59:50 PM PDT 24
Peak memory 496936 kb
Host smart-54c8c9a1-c394-427c-9190-87aac65b2013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1802697547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1802697547
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4033912140
Short name T822
Test name
Test status
Simulation time 16081974 ps
CPU time 0.8 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:18 PM PDT 24
Peak memory 207964 kb
Host smart-39f8f6f4-eb72-472f-9d73-be4c465506ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033912140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4033912140
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.282157391
Short name T854
Test name
Test status
Simulation time 73516872 ps
CPU time 1.17 seconds
Started May 28 02:51:02 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 209752 kb
Host smart-68287682-051f-4a84-b0e4-d7f6a7f63791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282157391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.282157391
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.602777855
Short name T330
Test name
Test status
Simulation time 1625295789 ps
CPU time 17.83 seconds
Started May 28 02:51:47 PM PDT 24
Finished May 28 02:52:24 PM PDT 24
Peak memory 218292 kb
Host smart-44127ad7-86bf-470f-a698-a69a3ada7568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602777855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.602777855
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3263389151
Short name T725
Test name
Test status
Simulation time 1509738674 ps
CPU time 6.15 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:35 PM PDT 24
Peak memory 217296 kb
Host smart-bb4642f5-daf4-4e03-a5c6-024e04b524cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263389151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3263389151
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.761004937
Short name T215
Test name
Test status
Simulation time 52199522 ps
CPU time 2.01 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:31 PM PDT 24
Peak memory 218100 kb
Host smart-5dccd52d-e3cd-4872-893d-770790ebd455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761004937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.761004937
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2950980614
Short name T384
Test name
Test status
Simulation time 425777477 ps
CPU time 13.52 seconds
Started May 28 02:51:48 PM PDT 24
Finished May 28 02:52:21 PM PDT 24
Peak memory 226400 kb
Host smart-1a01e22f-c892-49e1-aeb3-2de936007047
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950980614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2950980614
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3201471155
Short name T248
Test name
Test status
Simulation time 886125637 ps
CPU time 15.08 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 218144 kb
Host smart-7425ca1d-75d0-462c-b84a-2e720ab06b34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201471155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3201471155
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2819489190
Short name T476
Test name
Test status
Simulation time 378387635 ps
CPU time 13.58 seconds
Started May 28 02:51:51 PM PDT 24
Finished May 28 02:52:24 PM PDT 24
Peak memory 218320 kb
Host smart-24c4b3b2-693d-4771-b63d-2a22ba88770d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819489190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2819489190
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2209164074
Short name T522
Test name
Test status
Simulation time 480177337 ps
CPU time 7.41 seconds
Started May 28 02:51:07 PM PDT 24
Finished May 28 02:51:35 PM PDT 24
Peak memory 218228 kb
Host smart-37fd576b-2d7d-48c2-987a-0adcde079ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209164074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2209164074
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.4135899842
Short name T868
Test name
Test status
Simulation time 62056182 ps
CPU time 2.64 seconds
Started May 28 02:51:05 PM PDT 24
Finished May 28 02:51:27 PM PDT 24
Peak memory 214200 kb
Host smart-574ce40f-f695-44aa-a228-b50900f103dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135899842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4135899842
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2448448512
Short name T683
Test name
Test status
Simulation time 246681343 ps
CPU time 33.72 seconds
Started May 28 02:51:02 PM PDT 24
Finished May 28 02:51:56 PM PDT 24
Peak memory 247400 kb
Host smart-a2f27e5d-c681-44bb-a04b-12ddf46cad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448448512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2448448512
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2553538932
Short name T464
Test name
Test status
Simulation time 490404819 ps
CPU time 2.74 seconds
Started May 28 02:51:57 PM PDT 24
Finished May 28 02:52:18 PM PDT 24
Peak memory 226636 kb
Host smart-e58508a7-f6bb-4872-9ebd-b21a92183bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553538932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2553538932
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2655236351
Short name T435
Test name
Test status
Simulation time 14892772694 ps
CPU time 83.22 seconds
Started May 28 02:51:07 PM PDT 24
Finished May 28 02:52:50 PM PDT 24
Peak memory 283100 kb
Host smart-4df02675-59a6-40ca-9db1-053bc9cda46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655236351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2655236351
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2362811482
Short name T151
Test name
Test status
Simulation time 12804150673 ps
CPU time 266.55 seconds
Started May 28 02:51:00 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 267352 kb
Host smart-848c41ad-18ea-4ab3-bcb2-027d9716a223
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2362811482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2362811482
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2469973499
Short name T739
Test name
Test status
Simulation time 115112825 ps
CPU time 0.92 seconds
Started May 28 02:50:54 PM PDT 24
Finished May 28 02:51:10 PM PDT 24
Peak memory 211600 kb
Host smart-4a9fa54f-00d5-4ebe-9a08-53cdde9efa99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469973499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2469973499
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1817312835
Short name T458
Test name
Test status
Simulation time 40260929 ps
CPU time 1.01 seconds
Started May 28 02:51:00 PM PDT 24
Finished May 28 02:51:20 PM PDT 24
Peak memory 209704 kb
Host smart-f6a8705c-e991-402f-bdbd-3e6d35399373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817312835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1817312835
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1872766851
Short name T310
Test name
Test status
Simulation time 429737140 ps
CPU time 8.56 seconds
Started May 28 02:51:08 PM PDT 24
Finished May 28 02:51:36 PM PDT 24
Peak memory 218100 kb
Host smart-64ca964c-3076-4a4d-8634-8413e9d34ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872766851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1872766851
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.360263923
Short name T453
Test name
Test status
Simulation time 313643200 ps
CPU time 8.02 seconds
Started May 28 02:50:57 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 216964 kb
Host smart-3acc61e1-addc-48ad-a21e-bd84069c03f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360263923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.360263923
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3091091176
Short name T303
Test name
Test status
Simulation time 151958260 ps
CPU time 2.84 seconds
Started May 28 02:51:02 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 218072 kb
Host smart-96d5a635-2f48-42ac-a435-bf446f62bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091091176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3091091176
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3385146616
Short name T604
Test name
Test status
Simulation time 389621082 ps
CPU time 17.44 seconds
Started May 28 02:50:58 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 226216 kb
Host smart-aeefa1cb-00bc-43a3-b4ca-5a81c0daeaaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385146616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3385146616
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.693700101
Short name T521
Test name
Test status
Simulation time 1460998941 ps
CPU time 10.75 seconds
Started May 28 02:50:57 PM PDT 24
Finished May 28 02:51:25 PM PDT 24
Peak memory 218084 kb
Host smart-a3a5daf2-ca95-4f5b-a03d-f9b956d6ea01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693700101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.693700101
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4166925042
Short name T238
Test name
Test status
Simulation time 937323139 ps
CPU time 15.6 seconds
Started May 28 02:50:58 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 218036 kb
Host smart-48452f6f-1517-4539-ac25-68f42c1eb03c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166925042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4166925042
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1505097835
Short name T269
Test name
Test status
Simulation time 510264428 ps
CPU time 6.68 seconds
Started May 28 02:51:00 PM PDT 24
Finished May 28 02:51:24 PM PDT 24
Peak memory 218076 kb
Host smart-bd812ba7-00c8-40da-a470-86176a15a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505097835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1505097835
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3994788743
Short name T101
Test name
Test status
Simulation time 52294180 ps
CPU time 1.15 seconds
Started May 28 02:51:02 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 213288 kb
Host smart-3a06f51f-7930-4191-afde-f9b897fb1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994788743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3994788743
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1423005381
Short name T98
Test name
Test status
Simulation time 503714330 ps
CPU time 24.95 seconds
Started May 28 02:51:02 PM PDT 24
Finished May 28 02:51:47 PM PDT 24
Peak memory 251096 kb
Host smart-84986ca0-3e98-4cc0-8779-e0a125f2fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423005381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1423005381
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4172505217
Short name T430
Test name
Test status
Simulation time 308162273 ps
CPU time 9.26 seconds
Started May 28 02:50:55 PM PDT 24
Finished May 28 02:51:20 PM PDT 24
Peak memory 247352 kb
Host smart-b6c66672-c8d5-4cc1-a2c1-1f9d5314d867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172505217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4172505217
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3885292157
Short name T602
Test name
Test status
Simulation time 17958020362 ps
CPU time 90.13 seconds
Started May 28 02:51:15 PM PDT 24
Finished May 28 02:53:06 PM PDT 24
Peak memory 220132 kb
Host smart-dc926f45-b0e8-4c41-87a7-409664831cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885292157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3885292157
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2969926838
Short name T48
Test name
Test status
Simulation time 23596479 ps
CPU time 0.83 seconds
Started May 28 02:51:08 PM PDT 24
Finished May 28 02:51:29 PM PDT 24
Peak memory 208588 kb
Host smart-797595ea-edae-4574-b77c-97085a2623ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969926838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2969926838
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1818880400
Short name T460
Test name
Test status
Simulation time 56536210 ps
CPU time 1.2 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 209688 kb
Host smart-0d0d7a4d-bbcb-4054-8729-9ac88d076f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818880400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1818880400
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.175753321
Short name T489
Test name
Test status
Simulation time 317114100 ps
CPU time 10.82 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:28 PM PDT 24
Peak memory 218020 kb
Host smart-820ec5e2-4853-4e5e-b60c-8935e0ea742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175753321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.175753321
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.238725182
Short name T32
Test name
Test status
Simulation time 2082687203 ps
CPU time 4.12 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 216960 kb
Host smart-c33c438f-6fcb-4c1f-93a3-f811891b4dae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238725182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.238725182
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.338145737
Short name T677
Test name
Test status
Simulation time 118291393 ps
CPU time 1.71 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:19 PM PDT 24
Peak memory 218072 kb
Host smart-af407091-cad3-4e2b-8dd1-544b1aed1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338145737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.338145737
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2647990103
Short name T781
Test name
Test status
Simulation time 908101033 ps
CPU time 19.4 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:50 PM PDT 24
Peak memory 226200 kb
Host smart-40b9f6a1-c3ad-4474-b4ec-6928e944504c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647990103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2647990103
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1528224536
Short name T106
Test name
Test status
Simulation time 788430729 ps
CPU time 8.88 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218016 kb
Host smart-80cfc202-666a-494b-9e4c-24d82df50d42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528224536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1528224536
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.317501364
Short name T741
Test name
Test status
Simulation time 1151312077 ps
CPU time 8.97 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218052 kb
Host smart-97cae3a9-b86b-4f5c-8a2e-8a0089df65f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317501364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.317501364
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2483194404
Short name T316
Test name
Test status
Simulation time 1836237523 ps
CPU time 10.48 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218236 kb
Host smart-cfe39464-e3a5-4668-ba47-bff134a66b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483194404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2483194404
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2670251535
Short name T621
Test name
Test status
Simulation time 15681315 ps
CPU time 1.32 seconds
Started May 28 02:50:58 PM PDT 24
Finished May 28 02:51:17 PM PDT 24
Peak memory 213340 kb
Host smart-65300982-0656-49ac-9a15-ed7e4ae21d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670251535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2670251535
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.425170996
Short name T816
Test name
Test status
Simulation time 2303652503 ps
CPU time 25.76 seconds
Started May 28 02:51:00 PM PDT 24
Finished May 28 02:51:45 PM PDT 24
Peak memory 250996 kb
Host smart-6e423aa6-c559-4c36-9a04-05fcf80bf907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425170996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.425170996
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2656427761
Short name T622
Test name
Test status
Simulation time 41908642 ps
CPU time 6.01 seconds
Started May 28 02:50:59 PM PDT 24
Finished May 28 02:51:23 PM PDT 24
Peak memory 242828 kb
Host smart-3347af78-cb22-4f50-8078-3d6a0f606b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656427761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2656427761
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2235139441
Short name T585
Test name
Test status
Simulation time 13537377014 ps
CPU time 82.66 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:52:54 PM PDT 24
Peak memory 269172 kb
Host smart-0bcc03da-5bcb-45da-b815-e4370700b415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235139441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2235139441
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3664114142
Short name T640
Test name
Test status
Simulation time 15108808 ps
CPU time 1.04 seconds
Started May 28 02:50:58 PM PDT 24
Finished May 28 02:51:17 PM PDT 24
Peak memory 211564 kb
Host smart-667e6d45-7994-4fb4-b2b3-d2e2b85db87b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664114142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3664114142
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.426763020
Short name T96
Test name
Test status
Simulation time 12283875 ps
CPU time 0.79 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 209612 kb
Host smart-5b53a86f-b1b0-4464-a7f1-7b282fea42e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426763020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.426763020
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.494672138
Short name T539
Test name
Test status
Simulation time 1645089839 ps
CPU time 10.5 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218024 kb
Host smart-b1c9d08c-5443-42be-bb3f-a5d0dcfaa0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494672138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.494672138
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2889957476
Short name T674
Test name
Test status
Simulation time 608718195 ps
CPU time 2.92 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 209632 kb
Host smart-e75c640f-2490-4b59-b34c-232bc0b656db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889957476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2889957476
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1521885138
Short name T252
Test name
Test status
Simulation time 556985779 ps
CPU time 3.24 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 218104 kb
Host smart-5367f037-a9ed-4b96-8db2-0e947ce4dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521885138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1521885138
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3111287882
Short name T593
Test name
Test status
Simulation time 214848977 ps
CPU time 10.92 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:39 PM PDT 24
Peak memory 225964 kb
Host smart-d3c70010-a288-47d9-83fa-0a10083564a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111287882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3111287882
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.133878567
Short name T275
Test name
Test status
Simulation time 1312078810 ps
CPU time 13.97 seconds
Started May 28 02:51:08 PM PDT 24
Finished May 28 02:51:42 PM PDT 24
Peak memory 218036 kb
Host smart-f225be08-3371-415f-87b2-564b1ebb6b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133878567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.133878567
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.624790786
Short name T699
Test name
Test status
Simulation time 1074935695 ps
CPU time 11.46 seconds
Started May 28 02:51:14 PM PDT 24
Finished May 28 02:51:46 PM PDT 24
Peak memory 218152 kb
Host smart-0507d342-3f26-49a3-afe8-42fc87459b6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624790786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.624790786
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3136171202
Short name T398
Test name
Test status
Simulation time 269076998 ps
CPU time 12.74 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:42 PM PDT 24
Peak memory 218212 kb
Host smart-f652831f-2bcd-4d3b-95b9-0cfe0f6cc6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136171202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3136171202
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1356280784
Short name T46
Test name
Test status
Simulation time 35475958 ps
CPU time 2.23 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 217828 kb
Host smart-3363e976-fe17-4f85-b637-80ef2de3c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356280784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1356280784
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4259285544
Short name T183
Test name
Test status
Simulation time 253527338 ps
CPU time 23.98 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:52 PM PDT 24
Peak memory 250908 kb
Host smart-06529f2b-c8f9-4dee-98cd-ff4a2ddc6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259285544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4259285544
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.582146589
Short name T155
Test name
Test status
Simulation time 73111887 ps
CPU time 7.92 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:38 PM PDT 24
Peak memory 251108 kb
Host smart-a6f8f3a4-79fe-4ed0-a013-11ef60765c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582146589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.582146589
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2127761384
Short name T772
Test name
Test status
Simulation time 2395684299 ps
CPU time 43.19 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:52:12 PM PDT 24
Peak memory 251064 kb
Host smart-a5206e80-8e5f-4c3c-95ac-7aec2775b9a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127761384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2127761384
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2982848366
Short name T511
Test name
Test status
Simulation time 52344243 ps
CPU time 0.96 seconds
Started May 28 02:51:09 PM PDT 24
Finished May 28 02:51:30 PM PDT 24
Peak memory 211604 kb
Host smart-1aae5c31-20d2-432b-a08d-3fa33c74e089
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982848366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2982848366
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1794997616
Short name T326
Test name
Test status
Simulation time 35444186 ps
CPU time 1.13 seconds
Started May 28 02:51:20 PM PDT 24
Finished May 28 02:51:41 PM PDT 24
Peak memory 209696 kb
Host smart-a48a3d0c-0782-4ea1-972e-c07369fd56e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794997616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1794997616
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3364164192
Short name T383
Test name
Test status
Simulation time 1719271041 ps
CPU time 12.35 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:44 PM PDT 24
Peak memory 218100 kb
Host smart-a7bcad9d-a73e-4412-81c2-82c2db6fa886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364164192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3364164192
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1575735124
Short name T700
Test name
Test status
Simulation time 179768651 ps
CPU time 1.28 seconds
Started May 28 02:51:14 PM PDT 24
Finished May 28 02:51:36 PM PDT 24
Peak memory 209620 kb
Host smart-edf942db-d04f-4b0a-81f7-e52034da5978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575735124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1575735124
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3448977615
Short name T235
Test name
Test status
Simulation time 199221685 ps
CPU time 2.94 seconds
Started May 28 02:51:14 PM PDT 24
Finished May 28 02:51:37 PM PDT 24
Peak memory 218168 kb
Host smart-aa9970ae-b579-498f-a410-d6e554544433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448977615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3448977615
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2346675
Short name T449
Test name
Test status
Simulation time 1251200427 ps
CPU time 11.79 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:43 PM PDT 24
Peak memory 225876 kb
Host smart-6560c6bc-f3b1-487c-96d2-ce62188cfaa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2346675
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.455620051
Short name T518
Test name
Test status
Simulation time 1497649548 ps
CPU time 15.42 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:46 PM PDT 24
Peak memory 218116 kb
Host smart-3444d6a7-accb-477c-af72-c01af2b79236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455620051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.455620051
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.369791436
Short name T684
Test name
Test status
Simulation time 1030071958 ps
CPU time 7.43 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 218124 kb
Host smart-f90c01e1-0c02-424f-b92c-4b5ea8eae052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369791436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.369791436
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4004960856
Short name T337
Test name
Test status
Simulation time 458882193 ps
CPU time 15.98 seconds
Started May 28 02:51:14 PM PDT 24
Finished May 28 02:51:50 PM PDT 24
Peak memory 218192 kb
Host smart-e11a56d5-4bd6-4a4e-8a83-f7126973c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004960856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4004960856
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.949653500
Short name T488
Test name
Test status
Simulation time 291742647 ps
CPU time 3.72 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:35 PM PDT 24
Peak memory 217812 kb
Host smart-9a89d1c9-4134-4945-b62e-80c74e22a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949653500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.949653500
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4183398049
Short name T390
Test name
Test status
Simulation time 691636587 ps
CPU time 22.94 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:55 PM PDT 24
Peak memory 251028 kb
Host smart-2de476f3-6ebf-452c-9b8d-99f1daa7b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183398049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4183398049
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3174566598
Short name T555
Test name
Test status
Simulation time 265480224 ps
CPU time 7.8 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:39 PM PDT 24
Peak memory 251016 kb
Host smart-f002907e-ff46-4e98-89c5-63e89c8b0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174566598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3174566598
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2762869872
Short name T656
Test name
Test status
Simulation time 1079884734 ps
CPU time 41.22 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:52:14 PM PDT 24
Peak memory 250952 kb
Host smart-9f30b14d-a361-4d37-9fb3-3ac737501967
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762869872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2762869872
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3731111849
Short name T576
Test name
Test status
Simulation time 51814540 ps
CPU time 0.91 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 211628 kb
Host smart-1e025b6f-ee02-4f2b-8d6f-fabef1f6f42e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731111849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3731111849
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.554619281
Short name T669
Test name
Test status
Simulation time 14162660 ps
CPU time 1.07 seconds
Started May 28 02:51:16 PM PDT 24
Finished May 28 02:51:39 PM PDT 24
Peak memory 209588 kb
Host smart-29f6f06b-de48-4e39-bec0-6b446c7b4cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554619281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.554619281
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.273533077
Short name T519
Test name
Test status
Simulation time 409009309 ps
CPU time 11.88 seconds
Started May 28 02:51:14 PM PDT 24
Finished May 28 02:51:46 PM PDT 24
Peak memory 218116 kb
Host smart-47ff7c63-c604-4378-9c97-b83f0f74d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273533077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.273533077
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2440536467
Short name T443
Test name
Test status
Simulation time 388793287 ps
CPU time 10.05 seconds
Started May 28 02:51:18 PM PDT 24
Finished May 28 02:51:49 PM PDT 24
Peak memory 209412 kb
Host smart-a5b2099c-9a38-46a1-8ad8-1c1e9fbfb504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440536467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2440536467
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1967051988
Short name T783
Test name
Test status
Simulation time 225342970 ps
CPU time 3.12 seconds
Started May 28 02:51:18 PM PDT 24
Finished May 28 02:51:42 PM PDT 24
Peak memory 217856 kb
Host smart-1692e71c-149d-4241-91ee-8ceb0f1b6ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967051988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1967051988
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1348335317
Short name T802
Test name
Test status
Simulation time 1179626168 ps
CPU time 13.2 seconds
Started May 28 02:51:15 PM PDT 24
Finished May 28 02:51:49 PM PDT 24
Peak memory 218288 kb
Host smart-591704d6-2f0c-46fe-8269-8b3935d6eabd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348335317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1348335317
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1617366585
Short name T274
Test name
Test status
Simulation time 1386321107 ps
CPU time 11.23 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:51:44 PM PDT 24
Peak memory 218112 kb
Host smart-124c0365-1fe5-4c93-98f3-3716118b1c1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617366585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1617366585
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2981570490
Short name T217
Test name
Test status
Simulation time 198455517 ps
CPU time 5.75 seconds
Started May 28 02:51:16 PM PDT 24
Finished May 28 02:51:44 PM PDT 24
Peak memory 218076 kb
Host smart-bea4b863-8c59-45c6-a3a2-f3ed112bf6cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981570490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2981570490
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1432750917
Short name T690
Test name
Test status
Simulation time 1224198567 ps
CPU time 11.36 seconds
Started May 28 02:51:16 PM PDT 24
Finished May 28 02:51:49 PM PDT 24
Peak memory 218160 kb
Host smart-ea2a8a73-42ef-4a6f-9a5c-77c1e6ff6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432750917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1432750917
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2311071667
Short name T338
Test name
Test status
Simulation time 75963743 ps
CPU time 2.63 seconds
Started May 28 02:51:11 PM PDT 24
Finished May 28 02:51:34 PM PDT 24
Peak memory 214268 kb
Host smart-6904bb27-20dc-4aa4-9bd4-a2ed03fca051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311071667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2311071667
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3821908756
Short name T821
Test name
Test status
Simulation time 271031705 ps
CPU time 21.77 seconds
Started May 28 02:51:18 PM PDT 24
Finished May 28 02:52:00 PM PDT 24
Peak memory 247628 kb
Host smart-759f3204-7041-455c-ada7-b154ee49c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821908756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3821908756
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4107240761
Short name T536
Test name
Test status
Simulation time 90644543 ps
CPU time 8.04 seconds
Started May 28 02:51:10 PM PDT 24
Finished May 28 02:51:38 PM PDT 24
Peak memory 251028 kb
Host smart-6e0c47a7-50e9-470c-92d8-f0d3d1438f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107240761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4107240761
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.515658409
Short name T346
Test name
Test status
Simulation time 22086873816 ps
CPU time 109.61 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:53:22 PM PDT 24
Peak memory 283864 kb
Host smart-b05ce6c2-3362-456b-825a-f149cbf8d741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515658409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.515658409
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2836075872
Short name T433
Test name
Test status
Simulation time 17334913 ps
CPU time 1.01 seconds
Started May 28 02:51:20 PM PDT 24
Finished May 28 02:51:41 PM PDT 24
Peak memory 211608 kb
Host smart-2553ecc8-c330-49d5-9ec2-102dac75e82f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836075872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2836075872
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2572653642
Short name T578
Test name
Test status
Simulation time 25499962 ps
CPU time 1.33 seconds
Started May 28 02:51:28 PM PDT 24
Finished May 28 02:51:51 PM PDT 24
Peak memory 209660 kb
Host smart-67ff427d-009d-4dfe-bb6c-acb0b4dc9a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572653642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2572653642
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3118082219
Short name T395
Test name
Test status
Simulation time 314555276 ps
CPU time 10.93 seconds
Started May 28 02:51:25 PM PDT 24
Finished May 28 02:51:57 PM PDT 24
Peak memory 218100 kb
Host smart-43aac09c-5862-4553-ae57-d8bb04e5c60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118082219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3118082219
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1372645488
Short name T579
Test name
Test status
Simulation time 2801772618 ps
CPU time 7.28 seconds
Started May 28 02:51:27 PM PDT 24
Finished May 28 02:51:55 PM PDT 24
Peak memory 217428 kb
Host smart-8fdd6994-8512-4bb4-b5dd-37a51b681158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372645488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1372645488
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3238648878
Short name T504
Test name
Test status
Simulation time 204761241 ps
CPU time 2.29 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:51:49 PM PDT 24
Peak memory 218100 kb
Host smart-c72d16cc-398b-4652-b424-73c9f52d42a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238648878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3238648878
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1341491668
Short name T865
Test name
Test status
Simulation time 1104225299 ps
CPU time 11.73 seconds
Started May 28 02:51:28 PM PDT 24
Finished May 28 02:52:02 PM PDT 24
Peak memory 218284 kb
Host smart-1cb81cfa-1e1c-408d-9b6f-20bbc17246db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341491668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1341491668
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.477553216
Short name T306
Test name
Test status
Simulation time 425412169 ps
CPU time 16.76 seconds
Started May 28 02:51:24 PM PDT 24
Finished May 28 02:52:02 PM PDT 24
Peak memory 218112 kb
Host smart-d51707fc-4eee-417d-bdda-be009a61e5ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477553216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.477553216
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3654616043
Short name T304
Test name
Test status
Simulation time 259362490 ps
CPU time 7.4 seconds
Started May 28 02:51:32 PM PDT 24
Finished May 28 02:52:00 PM PDT 24
Peak memory 218104 kb
Host smart-8ad09a9b-92a1-4098-808e-970df20d22d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654616043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3654616043
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.111860409
Short name T277
Test name
Test status
Simulation time 1930668411 ps
CPU time 11.95 seconds
Started May 28 02:51:27 PM PDT 24
Finished May 28 02:52:00 PM PDT 24
Peak memory 218176 kb
Host smart-b029f5b9-3dad-40ba-ba37-c4ae396027e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111860409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.111860409
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.282234120
Short name T283
Test name
Test status
Simulation time 78622407 ps
CPU time 1.75 seconds
Started May 28 02:51:15 PM PDT 24
Finished May 28 02:51:38 PM PDT 24
Peak memory 213748 kb
Host smart-30f9accf-4e6a-4924-b11f-a90d915ae7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282234120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.282234120
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3357543064
Short name T688
Test name
Test status
Simulation time 1832663430 ps
CPU time 28.88 seconds
Started May 28 02:51:16 PM PDT 24
Finished May 28 02:52:07 PM PDT 24
Peak memory 250972 kb
Host smart-a989fc0c-6cc5-471a-8569-272d6bddff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357543064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3357543064
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.113741483
Short name T673
Test name
Test status
Simulation time 62601308 ps
CPU time 7.04 seconds
Started May 28 02:51:16 PM PDT 24
Finished May 28 02:51:45 PM PDT 24
Peak memory 250464 kb
Host smart-1387a65b-f942-4bac-afa4-ed6c31bc3838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113741483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.113741483
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1913394558
Short name T552
Test name
Test status
Simulation time 8206021574 ps
CPU time 230.32 seconds
Started May 28 02:51:27 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 226228 kb
Host smart-0d9964bf-993d-489e-8fa1-ab3f309f06ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913394558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1913394558
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3300542294
Short name T379
Test name
Test status
Simulation time 10980708 ps
CPU time 0.86 seconds
Started May 28 02:51:12 PM PDT 24
Finished May 28 02:51:33 PM PDT 24
Peak memory 208572 kb
Host smart-0f54c94a-835a-4e3f-bf94-95b6daf3db7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300542294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3300542294
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3774122661
Short name T835
Test name
Test status
Simulation time 15969882 ps
CPU time 0.92 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:51:48 PM PDT 24
Peak memory 209680 kb
Host smart-aa83026b-d1d4-4cc6-9b29-c5acb19a01e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774122661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3774122661
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3175003920
Short name T550
Test name
Test status
Simulation time 3148396440 ps
CPU time 12.14 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:52:00 PM PDT 24
Peak memory 219112 kb
Host smart-bdc97aa8-084e-4b65-b9e0-92b1b72ce6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175003920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3175003920
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1017250187
Short name T31
Test name
Test status
Simulation time 628409049 ps
CPU time 9.15 seconds
Started May 28 02:51:41 PM PDT 24
Finished May 28 02:52:11 PM PDT 24
Peak memory 216964 kb
Host smart-a9480143-e296-460c-9200-618fbfc5ae0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017250187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1017250187
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3520221780
Short name T300
Test name
Test status
Simulation time 336904507 ps
CPU time 5.31 seconds
Started May 28 02:51:41 PM PDT 24
Finished May 28 02:52:08 PM PDT 24
Peak memory 217860 kb
Host smart-952e634a-ff66-4fec-8a89-05e96d663529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520221780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3520221780
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4017372329
Short name T609
Test name
Test status
Simulation time 2252305013 ps
CPU time 16.29 seconds
Started May 28 02:51:25 PM PDT 24
Finished May 28 02:52:02 PM PDT 24
Peak memory 226260 kb
Host smart-6166d7d7-481c-456c-bf43-88722a14111b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017372329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4017372329
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1261177800
Short name T262
Test name
Test status
Simulation time 571968319 ps
CPU time 13.07 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:52:00 PM PDT 24
Peak memory 218040 kb
Host smart-e0c39ced-e680-4889-a8e8-cc79c321bc17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261177800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1261177800
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2532693657
Short name T714
Test name
Test status
Simulation time 923065827 ps
CPU time 8.73 seconds
Started May 28 02:51:27 PM PDT 24
Finished May 28 02:51:56 PM PDT 24
Peak memory 218012 kb
Host smart-bd0c7486-a61d-4ace-a628-d89df600c8dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532693657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2532693657
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.194036391
Short name T784
Test name
Test status
Simulation time 337906578 ps
CPU time 9.7 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:51:56 PM PDT 24
Peak memory 218172 kb
Host smart-7b482a4f-1051-4b14-b752-2a9264970d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194036391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.194036391
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2854454779
Short name T620
Test name
Test status
Simulation time 12653455 ps
CPU time 1.16 seconds
Started May 28 02:51:25 PM PDT 24
Finished May 28 02:51:48 PM PDT 24
Peak memory 213376 kb
Host smart-f85bff10-b260-4429-afda-3ccaa61e9d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854454779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2854454779
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.765103914
Short name T258
Test name
Test status
Simulation time 319969890 ps
CPU time 27.31 seconds
Started May 28 02:51:27 PM PDT 24
Finished May 28 02:52:16 PM PDT 24
Peak memory 245764 kb
Host smart-750d13ab-f4b0-46ac-8daf-7d9824f708e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765103914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.765103914
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1884060578
Short name T266
Test name
Test status
Simulation time 46595390 ps
CPU time 5.71 seconds
Started May 28 02:51:25 PM PDT 24
Finished May 28 02:51:52 PM PDT 24
Peak memory 244572 kb
Host smart-da525c8b-4a5f-443f-81b2-a03f5198686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884060578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1884060578
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2665192513
Short name T636
Test name
Test status
Simulation time 66983050 ps
CPU time 1.08 seconds
Started May 28 02:51:26 PM PDT 24
Finished May 28 02:51:49 PM PDT 24
Peak memory 212700 kb
Host smart-a9e6bff1-b30d-48b7-aa13-bd423cc9ae11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665192513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2665192513
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.12885466
Short name T789
Test name
Test status
Simulation time 42013562 ps
CPU time 0.92 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:21 PM PDT 24
Peak memory 209620 kb
Host smart-12e4645b-5d63-4ce8-8af8-4117acbd593f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12885466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.12885466
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1453536411
Short name T207
Test name
Test status
Simulation time 23817940 ps
CPU time 1 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 209616 kb
Host smart-f341d28a-fe97-4d8a-8ec3-40971abf683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453536411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1453536411
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3195495124
Short name T349
Test name
Test status
Simulation time 2798538660 ps
CPU time 13.07 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 218224 kb
Host smart-29c9f63b-e5af-4a6a-adc1-890bd556a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195495124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3195495124
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3343832550
Short name T818
Test name
Test status
Simulation time 1093448889 ps
CPU time 3.78 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 216964 kb
Host smart-7e7c16ad-0bff-490d-8a4d-010c465456c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343832550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3343832550
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.765829976
Short name T397
Test name
Test status
Simulation time 2370101611 ps
CPU time 36.37 seconds
Started May 28 02:49:17 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 218172 kb
Host smart-df609aac-e732-42b9-95e0-af873fb01b90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765829976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.765829976
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2298886793
Short name T447
Test name
Test status
Simulation time 9952903391 ps
CPU time 22.3 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:45 PM PDT 24
Peak memory 217956 kb
Host smart-28d2ee0d-f2c8-4038-bc4a-a848d255a652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298886793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
298886793
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3505948501
Short name T591
Test name
Test status
Simulation time 400862340 ps
CPU time 5.51 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 218044 kb
Host smart-4f6b8698-96bd-411d-af8c-5cf3459257d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505948501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3505948501
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.311293844
Short name T413
Test name
Test status
Simulation time 2573629468 ps
CPU time 35.2 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 213800 kb
Host smart-d3ea8063-7697-4757-83ad-14985a7ed1ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311293844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.311293844
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2810254718
Short name T468
Test name
Test status
Simulation time 2691357836 ps
CPU time 3.87 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 213744 kb
Host smart-0dc3bd89-393f-4c6e-8474-bb2a23874a60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810254718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2810254718
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2278957233
Short name T738
Test name
Test status
Simulation time 5384434286 ps
CPU time 34.53 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:55 PM PDT 24
Peak memory 251104 kb
Host smart-9736a6ed-74d6-479c-b528-41be45b4c4a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278957233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2278957233
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.258857283
Short name T705
Test name
Test status
Simulation time 2301761095 ps
CPU time 13.77 seconds
Started May 28 02:49:14 PM PDT 24
Finished May 28 02:49:34 PM PDT 24
Peak memory 251016 kb
Host smart-38c986ae-3c0e-424e-adca-71b6c2f0c52c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258857283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.258857283
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.763910780
Short name T320
Test name
Test status
Simulation time 111843084 ps
CPU time 2.87 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 218096 kb
Host smart-b7901cfe-8420-4457-8640-01397bbaa5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763910780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.763910780
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3633039102
Short name T189
Test name
Test status
Simulation time 726339641 ps
CPU time 13.82 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 217820 kb
Host smart-478d6b16-98ef-4f87-a1ac-3024b566b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633039102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3633039102
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1024626547
Short name T291
Test name
Test status
Simulation time 418834459 ps
CPU time 14.84 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 226144 kb
Host smart-24f77f94-1207-42ef-9f1e-618da40c456b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024626547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1024626547
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.94326475
Short name T65
Test name
Test status
Simulation time 790344248 ps
CPU time 8.41 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 218008 kb
Host smart-5dffa1a9-0e35-4f25-be35-4d4e65791a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94326475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.94326475
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1625834005
Short name T686
Test name
Test status
Simulation time 761397830 ps
CPU time 13.73 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:34 PM PDT 24
Peak memory 218088 kb
Host smart-de3f4f4a-56b1-42db-b228-18b9d03a4749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625834005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1625834005
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.652264120
Short name T236
Test name
Test status
Simulation time 27597314 ps
CPU time 1.72 seconds
Started May 28 02:49:09 PM PDT 24
Finished May 28 02:49:19 PM PDT 24
Peak memory 214012 kb
Host smart-3358ec6e-2f21-481d-a0f4-18cb5e110185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652264120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.652264120
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.237965283
Short name T99
Test name
Test status
Simulation time 326071046 ps
CPU time 27.88 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:43 PM PDT 24
Peak memory 251032 kb
Host smart-3273532f-7edd-4a1e-8b43-52d146264339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237965283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.237965283
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2718541807
Short name T757
Test name
Test status
Simulation time 152273257 ps
CPU time 6.35 seconds
Started May 28 02:49:06 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 242852 kb
Host smart-9bb6464c-5e90-4b92-af31-c2a1bb27eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718541807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2718541807
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2074880329
Short name T755
Test name
Test status
Simulation time 14249795942 ps
CPU time 126 seconds
Started May 28 02:49:23 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 267448 kb
Host smart-3324e964-d1b4-4d56-baed-626f14093ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074880329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2074880329
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4248929823
Short name T111
Test name
Test status
Simulation time 89391645970 ps
CPU time 343.88 seconds
Started May 28 02:49:22 PM PDT 24
Finished May 28 02:55:09 PM PDT 24
Peak memory 328004 kb
Host smart-707ce85a-4641-477e-9b93-8a16151a6929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4248929823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.4248929823
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1806664950
Short name T728
Test name
Test status
Simulation time 82450321 ps
CPU time 1.26 seconds
Started May 28 02:49:24 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 209756 kb
Host smart-3bba8344-84d1-4c8d-9208-af896145af9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806664950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1806664950
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1950074491
Short name T43
Test name
Test status
Simulation time 207915146 ps
CPU time 7.98 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:30 PM PDT 24
Peak memory 218092 kb
Host smart-0192dcc1-4703-4eb1-92f7-e2a7c235b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950074491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1950074491
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1614924885
Short name T325
Test name
Test status
Simulation time 28357112071 ps
CPU time 46.95 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:50:10 PM PDT 24
Peak memory 217956 kb
Host smart-59256e51-c796-42e7-b886-8a01e97ee8a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614924885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1614924885
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1420052350
Short name T627
Test name
Test status
Simulation time 1773722046 ps
CPU time 4.31 seconds
Started May 28 02:49:17 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 209672 kb
Host smart-fa14ad20-e3b3-4bf7-a7d5-d9008613f5a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420052350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
420052350
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4153680273
Short name T666
Test name
Test status
Simulation time 383994463 ps
CPU time 6.16 seconds
Started May 28 02:49:28 PM PDT 24
Finished May 28 02:49:39 PM PDT 24
Peak memory 218088 kb
Host smart-b5e8f30b-4318-4f03-8a72-a97e58757f62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153680273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4153680273
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.869829255
Short name T376
Test name
Test status
Simulation time 2367695495 ps
CPU time 15.92 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 213304 kb
Host smart-1e62c59e-9a7f-48fb-bc65-805722ff3278
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869829255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.869829255
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.874340246
Short name T75
Test name
Test status
Simulation time 269752712 ps
CPU time 7.59 seconds
Started May 28 02:49:17 PM PDT 24
Finished May 28 02:49:30 PM PDT 24
Peak memory 213552 kb
Host smart-6d49f0c9-a4fa-47ed-a599-fd19a9223cc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874340246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.874340246
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2036141865
Short name T276
Test name
Test status
Simulation time 6849062296 ps
CPU time 41.67 seconds
Started May 28 02:49:26 PM PDT 24
Finished May 28 02:50:11 PM PDT 24
Peak memory 257672 kb
Host smart-d3f8c99d-6d02-40c9-b430-6d059d0cc0ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036141865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2036141865
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.249703261
Short name T442
Test name
Test status
Simulation time 1401778289 ps
CPU time 23.95 seconds
Started May 28 02:49:15 PM PDT 24
Finished May 28 02:49:45 PM PDT 24
Peak memory 247580 kb
Host smart-8f3f34c3-8e21-4fcb-9c0e-ed12c285d9fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249703261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.249703261
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.229536751
Short name T223
Test name
Test status
Simulation time 102077694 ps
CPU time 2.03 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 218012 kb
Host smart-ecaab361-087c-4523-90d7-a8501d841ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229536751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.229536751
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.649375970
Short name T706
Test name
Test status
Simulation time 7789961076 ps
CPU time 14.65 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:38 PM PDT 24
Peak memory 217884 kb
Host smart-c1a5f441-a2b7-43ae-8847-fd40732f7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649375970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.649375970
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.408050181
Short name T646
Test name
Test status
Simulation time 310375107 ps
CPU time 9.13 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:32 PM PDT 24
Peak memory 226176 kb
Host smart-22e3bf67-b1d1-4ba6-a81e-e266b5f13dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408050181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.408050181
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.564934207
Short name T860
Test name
Test status
Simulation time 469790601 ps
CPU time 17.12 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 218028 kb
Host smart-6c5270b1-515c-4f8c-9d44-ead77a4dacd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564934207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.564934207
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.485243815
Short name T691
Test name
Test status
Simulation time 237624782 ps
CPU time 8.95 seconds
Started May 28 02:49:19 PM PDT 24
Finished May 28 02:49:33 PM PDT 24
Peak memory 218052 kb
Host smart-4f6fc3c2-f99a-48d9-95c5-c5a60b796a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485243815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.485243815
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.608981736
Short name T771
Test name
Test status
Simulation time 303052315 ps
CPU time 13.42 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:38 PM PDT 24
Peak memory 225964 kb
Host smart-6d01fdb0-903c-4fd0-974e-49ace967da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608981736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.608981736
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1998533566
Short name T103
Test name
Test status
Simulation time 156763768 ps
CPU time 1.46 seconds
Started May 28 02:49:23 PM PDT 24
Finished May 28 02:49:27 PM PDT 24
Peak memory 213620 kb
Host smart-7c3b2892-bdb2-4c80-9c37-2e828ff5348d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998533566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1998533566
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2682970468
Short name T353
Test name
Test status
Simulation time 567118410 ps
CPU time 26.36 seconds
Started May 28 02:49:23 PM PDT 24
Finished May 28 02:49:53 PM PDT 24
Peak memory 251008 kb
Host smart-ce2de34b-4d65-4948-941b-9424f4dfe736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682970468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2682970468
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3426182405
Short name T273
Test name
Test status
Simulation time 140390982 ps
CPU time 3.17 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:24 PM PDT 24
Peak memory 226376 kb
Host smart-fa8db6e9-9065-4b2b-b0a4-efd7cf9dc219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426182405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3426182405
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.559076802
Short name T769
Test name
Test status
Simulation time 2767373925 ps
CPU time 107.48 seconds
Started May 28 02:49:19 PM PDT 24
Finished May 28 02:51:11 PM PDT 24
Peak memory 273876 kb
Host smart-d660e703-f073-4b23-bae2-a4d42abf88f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559076802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.559076802
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.507589094
Short name T469
Test name
Test status
Simulation time 16415956 ps
CPU time 0.84 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 208568 kb
Host smart-77dcab37-3ee8-4546-b9fb-aef09a858742
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507589094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.507589094
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.431456785
Short name T77
Test name
Test status
Simulation time 19941562 ps
CPU time 0.93 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 209688 kb
Host smart-9060103b-2376-4ec2-84a8-d418732d1067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431456785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.431456785
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3783030061
Short name T305
Test name
Test status
Simulation time 1194647277 ps
CPU time 12.56 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 218044 kb
Host smart-b4982138-e80a-4188-92a4-7035de92214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783030061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3783030061
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1817832475
Short name T633
Test name
Test status
Simulation time 274333077 ps
CPU time 2.09 seconds
Started May 28 02:49:20 PM PDT 24
Finished May 28 02:49:27 PM PDT 24
Peak memory 216968 kb
Host smart-b41b2c4b-fa72-420e-8709-d346ec9fe537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817832475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1817832475
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2130363667
Short name T782
Test name
Test status
Simulation time 8602738328 ps
CPU time 34.46 seconds
Started May 28 02:49:45 PM PDT 24
Finished May 28 02:50:27 PM PDT 24
Peak memory 219068 kb
Host smart-5de0dff2-4674-4292-b572-4185a9edd803
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130363667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2130363667
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3876783496
Short name T477
Test name
Test status
Simulation time 464508448 ps
CPU time 3.68 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 217352 kb
Host smart-d28887bc-6844-4964-bab9-1a5b52fa627f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876783496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
876783496
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1217900899
Short name T389
Test name
Test status
Simulation time 320016945 ps
CPU time 10.37 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 218108 kb
Host smart-c0fea75c-70cb-4997-a2f7-a9a7323303fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217900899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1217900899
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3520686235
Short name T541
Test name
Test status
Simulation time 1032014149 ps
CPU time 32.36 seconds
Started May 28 02:49:47 PM PDT 24
Finished May 28 02:50:26 PM PDT 24
Peak memory 213468 kb
Host smart-af7c93c6-4572-4543-945a-18741797ad13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520686235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3520686235
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1046333379
Short name T83
Test name
Test status
Simulation time 1117027184 ps
CPU time 3.4 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 213392 kb
Host smart-558b38c8-174f-4e99-8da8-6f176fd0b96a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046333379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1046333379
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3121360996
Short name T308
Test name
Test status
Simulation time 1168265899 ps
CPU time 55.63 seconds
Started May 28 02:49:20 PM PDT 24
Finished May 28 02:50:20 PM PDT 24
Peak memory 250956 kb
Host smart-cfe89196-c2db-4df1-9ce2-51d9eb29b401
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121360996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3121360996
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3623502590
Short name T610
Test name
Test status
Simulation time 1911204500 ps
CPU time 19.18 seconds
Started May 28 02:49:22 PM PDT 24
Finished May 28 02:49:45 PM PDT 24
Peak memory 250944 kb
Host smart-5bb7a714-3cb1-4bf6-a4ff-9e0d7ab905b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623502590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3623502590
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3657458994
Short name T819
Test name
Test status
Simulation time 649059629 ps
CPU time 6.33 seconds
Started May 28 02:49:25 PM PDT 24
Finished May 28 02:49:34 PM PDT 24
Peak memory 218056 kb
Host smart-149595ed-01e2-47b1-8107-7eb61bbe8571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657458994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3657458994
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1774086526
Short name T88
Test name
Test status
Simulation time 387552334 ps
CPU time 4.9 seconds
Started May 28 02:49:20 PM PDT 24
Finished May 28 02:49:30 PM PDT 24
Peak memory 217952 kb
Host smart-a8b52249-b19a-4e96-8b80-3499aabe1ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774086526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1774086526
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.19892445
Short name T737
Test name
Test status
Simulation time 260252967 ps
CPU time 12.29 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 225640 kb
Host smart-18c0840d-3b43-4428-8ce3-48669b436688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.19892445
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1128480238
Short name T760
Test name
Test status
Simulation time 2538457591 ps
CPU time 8.8 seconds
Started May 28 02:49:28 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 218084 kb
Host smart-8a354357-ebe6-4e5e-b7bc-5de52f0fd00e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128480238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1128480238
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1331125341
Short name T378
Test name
Test status
Simulation time 1646053357 ps
CPU time 9.14 seconds
Started May 28 02:49:16 PM PDT 24
Finished May 28 02:49:30 PM PDT 24
Peak memory 218052 kb
Host smart-a483b189-29f7-4147-8343-e1e918cee123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331125341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
331125341
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.320554579
Short name T826
Test name
Test status
Simulation time 1245760475 ps
CPU time 9.88 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:33 PM PDT 24
Peak memory 218228 kb
Host smart-e8ebba82-c8fa-4a86-b0e7-e5180cd7ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320554579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.320554579
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2625023208
Short name T87
Test name
Test status
Simulation time 235064477 ps
CPU time 3.05 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 217908 kb
Host smart-4426ee69-67be-4580-856f-f48ae0642c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625023208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2625023208
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.678326242
Short name T486
Test name
Test status
Simulation time 799792242 ps
CPU time 20.82 seconds
Started May 28 02:49:17 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 251084 kb
Host smart-b2e1c15a-f8ad-4441-99a9-c11fecf8f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678326242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.678326242
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1189253236
Short name T347
Test name
Test status
Simulation time 57918175 ps
CPU time 6.85 seconds
Started May 28 02:49:18 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 250616 kb
Host smart-e4640ac2-2dd6-49c0-96a0-b96bba3885c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189253236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1189253236
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1521599044
Short name T794
Test name
Test status
Simulation time 13248943374 ps
CPU time 401.01 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 271120 kb
Host smart-25187d22-49b5-4a26-8825-d62dc37abe9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521599044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1521599044
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1149709743
Short name T801
Test name
Test status
Simulation time 13996910 ps
CPU time 0.92 seconds
Started May 28 02:49:21 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 211576 kb
Host smart-186e3c18-0b8c-44d4-9149-ff3703c4b79f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149709743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1149709743
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2065607387
Short name T224
Test name
Test status
Simulation time 33386070 ps
CPU time 1.26 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 209340 kb
Host smart-0247de5e-c248-4151-bf4c-09a09da55358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065607387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2065607387
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1090252752
Short name T644
Test name
Test status
Simulation time 14136191 ps
CPU time 0.99 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 209608 kb
Host smart-a019c81c-acfe-4c6a-9ec0-f41ca1caca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090252752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1090252752
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3925380114
Short name T368
Test name
Test status
Simulation time 224665297 ps
CPU time 10.48 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218072 kb
Host smart-8e83eb7b-3a04-4c66-aaf8-2a353e58a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925380114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3925380114
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1739550966
Short name T563
Test name
Test status
Simulation time 501547697 ps
CPU time 12.49 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:47 PM PDT 24
Peak memory 217268 kb
Host smart-7bbc0b2d-9e1e-4694-83b5-1097a1506a64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739550966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1739550966
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3824281270
Short name T567
Test name
Test status
Simulation time 1886473063 ps
CPU time 29.62 seconds
Started May 28 02:49:28 PM PDT 24
Finished May 28 02:50:02 PM PDT 24
Peak memory 218056 kb
Host smart-f74823a4-8dfd-4303-9918-e145b52e3694
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824281270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3824281270
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2522959125
Short name T613
Test name
Test status
Simulation time 2265370263 ps
CPU time 5.36 seconds
Started May 28 02:49:27 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 217152 kb
Host smart-e5ad522d-8502-47c9-b800-efdb729e863f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522959125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
522959125
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3071941227
Short name T102
Test name
Test status
Simulation time 53195917 ps
CPU time 1.89 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 218020 kb
Host smart-42e12244-1658-4599-8ba5-f4ef0d28ea43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071941227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3071941227
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.230848462
Short name T231
Test name
Test status
Simulation time 3974684546 ps
CPU time 24.27 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 213764 kb
Host smart-dc178b3e-9a17-48b5-93db-4edbe9a2629f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230848462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.230848462
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3555519876
Short name T416
Test name
Test status
Simulation time 322209358 ps
CPU time 5.16 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:39 PM PDT 24
Peak memory 213548 kb
Host smart-3a4a0b00-97f7-419a-a8d2-3d60a6969a30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555519876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3555519876
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2609531448
Short name T324
Test name
Test status
Simulation time 1695585633 ps
CPU time 43.37 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 268624 kb
Host smart-3bcebc81-90b8-4030-ba24-cff27533d2d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609531448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2609531448
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2603662624
Short name T358
Test name
Test status
Simulation time 1236008588 ps
CPU time 14.59 seconds
Started May 28 02:49:28 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 250488 kb
Host smart-e3f1a99b-5579-4765-9030-1792517f3e07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603662624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2603662624
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4257645966
Short name T260
Test name
Test status
Simulation time 128289027 ps
CPU time 3.66 seconds
Started May 28 02:49:26 PM PDT 24
Finished May 28 02:49:33 PM PDT 24
Peak memory 218028 kb
Host smart-cc46e836-8a07-43b9-9e29-71fbbd92fbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257645966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4257645966
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2286310422
Short name T478
Test name
Test status
Simulation time 766865333 ps
CPU time 10.63 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:49 PM PDT 24
Peak memory 217912 kb
Host smart-8af420b7-f867-439a-ab63-1a77e95002e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286310422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2286310422
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2211151168
Short name T38
Test name
Test status
Simulation time 1455930518 ps
CPU time 12.55 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 226196 kb
Host smart-638bcef2-bdf7-4dcb-aa33-652677f5359c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211151168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2211151168
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2023132774
Short name T672
Test name
Test status
Simulation time 1782424842 ps
CPU time 14.14 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:52 PM PDT 24
Peak memory 218044 kb
Host smart-c8bf6cc2-4de4-475a-9f79-16ae3fbe8cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023132774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2023132774
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3692266959
Short name T778
Test name
Test status
Simulation time 311083606 ps
CPU time 11.9 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218128 kb
Host smart-a9eba36f-6bf3-4c58-a067-c441cb127904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692266959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
692266959
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2668387300
Short name T648
Test name
Test status
Simulation time 183390481 ps
CPU time 8.13 seconds
Started May 28 02:49:37 PM PDT 24
Finished May 28 02:49:50 PM PDT 24
Peak memory 218140 kb
Host smart-e791e2b0-8f73-438c-b5d7-4010e336d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668387300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2668387300
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2834719415
Short name T90
Test name
Test status
Simulation time 165562233 ps
CPU time 3.19 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:38 PM PDT 24
Peak memory 214748 kb
Host smart-0c96048b-5fa3-4f72-a97b-721ccedaef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834719415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2834719415
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3381763347
Short name T109
Test name
Test status
Simulation time 271711907 ps
CPU time 26.17 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:50:03 PM PDT 24
Peak memory 245840 kb
Host smart-252c7fc9-b2c2-410b-a3bc-c9c1f56871df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381763347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3381763347
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2983010253
Short name T222
Test name
Test status
Simulation time 113896265 ps
CPU time 7.2 seconds
Started May 28 02:49:29 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 250940 kb
Host smart-be6a64b2-02a7-4a0b-a9f3-587398b86b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983010253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2983010253
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1092447950
Short name T814
Test name
Test status
Simulation time 17762752035 ps
CPU time 181.59 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:52:40 PM PDT 24
Peak memory 272900 kb
Host smart-766c38c1-52c8-441f-8d1e-62f70e41383f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092447950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1092447950
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2713823502
Short name T827
Test name
Test status
Simulation time 221405794483 ps
CPU time 888 seconds
Started May 28 02:49:27 PM PDT 24
Finished May 28 03:04:19 PM PDT 24
Peak memory 283908 kb
Host smart-d0f6c2e2-ba8a-402e-8b32-38d5e7941f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2713823502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2713823502
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2619152517
Short name T503
Test name
Test status
Simulation time 48319762 ps
CPU time 0.79 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 208552 kb
Host smart-b2b3d2cd-9b1d-451a-9f37-0e10e646f7b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619152517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2619152517
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1495056354
Short name T372
Test name
Test status
Simulation time 23412206 ps
CPU time 0.94 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 209672 kb
Host smart-80681a97-6558-412f-834c-d782fb8dec0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495056354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1495056354
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.796709887
Short name T663
Test name
Test status
Simulation time 1962867748 ps
CPU time 13.97 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:49 PM PDT 24
Peak memory 218000 kb
Host smart-7c369c9d-2b57-4e00-83b4-f31b3cf15937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796709887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.796709887
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.445368196
Short name T188
Test name
Test status
Simulation time 531122336 ps
CPU time 6.48 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 217044 kb
Host smart-8ea259c4-6aab-4753-b37f-ce31e08fb91c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445368196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.445368196
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1856121347
Short name T50
Test name
Test status
Simulation time 11506768543 ps
CPU time 76.87 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:50:52 PM PDT 24
Peak memory 218692 kb
Host smart-826ae415-a6ab-447b-8efe-f2ec7f3b0554
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856121347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1856121347
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1656783083
Short name T314
Test name
Test status
Simulation time 270123321 ps
CPU time 3.67 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:40 PM PDT 24
Peak memory 217264 kb
Host smart-69fa13cf-4c26-407a-a3a3-4e80c599016c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656783083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
656783083
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1611490903
Short name T402
Test name
Test status
Simulation time 816216445 ps
CPU time 13.54 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 218040 kb
Host smart-b1773cdf-e242-43c3-aa7a-fd9fd2942590
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611490903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1611490903
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3822273727
Short name T647
Test name
Test status
Simulation time 2053880608 ps
CPU time 14.38 seconds
Started May 28 02:49:27 PM PDT 24
Finished May 28 02:49:45 PM PDT 24
Peak memory 213256 kb
Host smart-fbe271df-8af6-4716-9642-2b52515bd9cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822273727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3822273727
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2406433001
Short name T513
Test name
Test status
Simulation time 587309548 ps
CPU time 4.68 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 213476 kb
Host smart-f46c1ec1-ed8b-466f-a0b7-84bef84bcb72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406433001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2406433001
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.892875997
Short name T156
Test name
Test status
Simulation time 6573164465 ps
CPU time 61.39 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:50:41 PM PDT 24
Peak memory 267392 kb
Host smart-ec2aa649-4fe6-4733-b133-33b49629dfb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892875997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.892875997
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1041644926
Short name T546
Test name
Test status
Simulation time 1345462630 ps
CPU time 25 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:50:01 PM PDT 24
Peak memory 250956 kb
Host smart-35be44e7-b02b-4e0e-8f7b-106a1728c081
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041644926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1041644926
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2373902064
Short name T573
Test name
Test status
Simulation time 48212052 ps
CPU time 2.17 seconds
Started May 28 02:49:33 PM PDT 24
Finished May 28 02:49:41 PM PDT 24
Peak memory 218200 kb
Host smart-0fe44320-60d2-4035-b024-b596f8df6044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373902064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2373902064
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.181484552
Short name T855
Test name
Test status
Simulation time 321715477 ps
CPU time 17.35 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 217800 kb
Host smart-af107469-f1f3-4a3d-8b7b-e36076b55b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181484552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.181484552
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.777650530
Short name T547
Test name
Test status
Simulation time 932087436 ps
CPU time 12.72 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:48 PM PDT 24
Peak memory 218144 kb
Host smart-601a5f54-23dd-4cdc-a735-3aa617959981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777650530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.777650530
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1446466501
Short name T597
Test name
Test status
Simulation time 1202693889 ps
CPU time 26 seconds
Started May 28 02:49:36 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 218092 kb
Host smart-ce9475d1-cb1a-4856-91ad-d46cf6d0c0f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446466501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1446466501
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.4203953207
Short name T69
Test name
Test status
Simulation time 287452514 ps
CPU time 9.94 seconds
Started May 28 02:49:35 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 218028 kb
Host smart-59776ccd-9c82-4713-a480-75af25707926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203953207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4
203953207
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2611256131
Short name T642
Test name
Test status
Simulation time 430395296 ps
CPU time 8.13 seconds
Started May 28 02:49:30 PM PDT 24
Finished May 28 02:49:44 PM PDT 24
Peak memory 218228 kb
Host smart-50b5d839-f050-4cdf-9907-c14628094eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611256131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2611256131
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2408480630
Short name T681
Test name
Test status
Simulation time 64694289 ps
CPU time 2.64 seconds
Started May 28 02:49:34 PM PDT 24
Finished May 28 02:49:42 PM PDT 24
Peak memory 214588 kb
Host smart-53d13674-c836-40d7-8832-5e3556dc13b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408480630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2408480630
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2110224030
Short name T866
Test name
Test status
Simulation time 823460840 ps
CPU time 27.78 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:50:06 PM PDT 24
Peak memory 251116 kb
Host smart-63007a09-4107-4633-a009-badc9e82080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110224030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2110224030
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1906909985
Short name T174
Test name
Test status
Simulation time 220549640 ps
CPU time 7.17 seconds
Started May 28 02:49:32 PM PDT 24
Finished May 28 02:49:46 PM PDT 24
Peak memory 250680 kb
Host smart-25f95b7f-9013-40c9-be8c-7d85a10aae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906909985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1906909985
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3092013845
Short name T67
Test name
Test status
Simulation time 18556580449 ps
CPU time 189.62 seconds
Started May 28 02:49:28 PM PDT 24
Finished May 28 02:52:42 PM PDT 24
Peak memory 278224 kb
Host smart-07bd3ee2-91a1-4c94-ace7-4721d7603581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092013845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3092013845
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3516394255
Short name T161
Test name
Test status
Simulation time 73649379620 ps
CPU time 607.66 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:59:44 PM PDT 24
Peak memory 283852 kb
Host smart-51d63868-5d80-4fb5-86d2-5b4f7ac0c176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3516394255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3516394255
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1835989112
Short name T558
Test name
Test status
Simulation time 14965200 ps
CPU time 1.12 seconds
Started May 28 02:49:31 PM PDT 24
Finished May 28 02:49:38 PM PDT 24
Peak memory 211704 kb
Host smart-6a1e7edc-29dc-4c4a-bbea-e843170a4b6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835989112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1835989112
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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