Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1365966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1585006

1

T1

13

T2

1152

T3

178

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2610042	1			T1	75		T2	941		T3	225
values[0x0]	170346	1			T1	8		T2	413		T3	41
values[0x1]	170584	1			T1	8		T2	387		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1084602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1866370

1

T1

29

T2

1292

T3

207

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8456	1			T2	10		T14	6		T15	6
valid_sources[0x01]	7915	1			T1	1		T2	5		T3	5
valid_sources[0x02]	7727	1			T2	12		T13	5		T14	4
valid_sources[0x03]	9814	1			T2	9		T14	10		T16	3
valid_sources[0x04]	174417	1			T2	10		T3	43		T14	7
valid_sources[0x05]	8425	1			T2	10		T14	11		T15	8
valid_sources[0x06]	8094	1			T2	8		T14	5		T16	5
valid_sources[0x07]	7934	1			T2	13		T14	4		T17	2
valid_sources[0x08]	7852	1			T2	6		T14	4		T15	1
valid_sources[0x09]	15082	1			T2	5		T13	1		T14	5
valid_sources[0x0a]	7600	1			T2	4		T13	1		T14	6
valid_sources[0x0b]	8360	1			T2	7		T14	3		T15	4
valid_sources[0x0c]	7854	1			T2	7		T13	1		T14	5
valid_sources[0x0d]	7867	1			T2	9		T13	1		T14	3
valid_sources[0x0e]	7958	1			T2	2		T14	4		T16	1
valid_sources[0x0f]	7584	1			T2	8		T13	1		T14	5
valid_sources[0x10]	8030	1			T2	5		T4	3		T13	2
valid_sources[0x11]	8046	1			T2	9		T14	1		T15	5
valid_sources[0x12]	9331	1			T2	6		T14	5		T15	11
valid_sources[0x13]	7928	1			T1	1		T2	11		T14	3
valid_sources[0x14]	8272	1			T2	3		T13	1		T14	2
valid_sources[0x15]	8055	1			T2	13		T14	5		T16	3
valid_sources[0x16]	9306	1			T2	9		T14	4		T16	4
valid_sources[0x17]	8208	1			T1	3		T2	9		T14	4
valid_sources[0x18]	13885	1			T2	3		T13	1		T14	2
valid_sources[0x19]	13064	1			T2	5		T4	2		T13	1
valid_sources[0x1a]	8197	1			T2	12		T3	16		T13	1
valid_sources[0x1b]	7581	1			T2	4		T14	3		T15	3
valid_sources[0x1c]	10324	1			T2	8		T4	1		T13	2
valid_sources[0x1d]	9213	1			T2	14		T14	6		T16	1
valid_sources[0x1e]	7506	1			T2	4		T14	2		T15	4
valid_sources[0x1f]	8590	1			T2	6		T14	2		T15	5
valid_sources[0x20]	8710	1			T2	4		T14	2		T15	5
valid_sources[0x21]	8293	1			T1	1		T2	9		T14	3
valid_sources[0x22]	8691	1			T2	7		T13	2		T14	7
valid_sources[0x23]	10924	1			T2	4		T3	21		T13	2
valid_sources[0x24]	7865	1			T2	6		T13	1		T14	8
valid_sources[0x25]	10542	1			T1	1		T2	5		T13	2
valid_sources[0x26]	9071	1			T1	1		T2	8		T13	2
valid_sources[0x27]	8258	1			T2	11		T14	2		T16	10
valid_sources[0x28]	7940	1			T2	9		T14	4		T15	4
valid_sources[0x29]	9433	1			T2	5		T13	1		T14	6
valid_sources[0x2a]	8178	1			T1	1		T2	5		T13	1
valid_sources[0x2b]	8011	1			T1	1		T2	6		T4	1
valid_sources[0x2c]	8107	1			T2	6		T13	2		T14	3
valid_sources[0x2d]	8001	1			T2	10		T14	5		T15	7
valid_sources[0x2e]	43112	1			T2	8		T13	1		T14	9
valid_sources[0x2f]	8268	1			T2	7		T13	2		T14	2
valid_sources[0x30]	8290	1			T2	7		T13	1		T14	5
valid_sources[0x31]	10295	1			T2	8		T14	3		T15	8
valid_sources[0x32]	14940	1			T2	5		T4	2		T13	1
valid_sources[0x33]	7841	1			T2	6		T14	4		T15	12
valid_sources[0x34]	8051	1			T2	7		T14	4		T15	8
valid_sources[0x35]	8215	1			T2	9		T3	3		T13	1
valid_sources[0x36]	9276	1			T2	5		T14	3		T16	3
valid_sources[0x37]	8506	1			T2	4		T14	3		T15	17
valid_sources[0x38]	38447	1			T2	4		T14	7		T15	1
valid_sources[0x39]	7928	1			T2	6		T4	2		T13	1
valid_sources[0x3a]	11227	1			T2	7		T13	1		T14	3
valid_sources[0x3b]	9444	1			T2	7		T4	2		T14	3
valid_sources[0x3c]	9554	1			T2	8		T4	2		T14	3
valid_sources[0x3d]	8274	1			T2	10		T14	5		T16	2
valid_sources[0x3e]	7645	1			T2	10		T14	4		T15	2
valid_sources[0x3f]	9487	1			T2	9		T14	4		T15	5
valid_sources[0x40]	8055	1			T2	5		T14	3		T16	3
valid_sources[0x41]	8011	1			T1	1		T2	3		T13	1
valid_sources[0x42]	7545	1			T2	7		T4	1		T14	2
valid_sources[0x43]	23666	1			T2	3		T4	2		T14	5
valid_sources[0x44]	8199	1			T2	9		T14	4		T16	6
valid_sources[0x45]	10452	1			T2	6		T14	8		T15	8
valid_sources[0x46]	9276	1			T1	1		T2	3		T14	4
valid_sources[0x47]	8151	1			T1	1		T2	9		T13	1
valid_sources[0x48]	12081	1			T2	1		T13	1		T14	2
valid_sources[0x49]	7816	1			T2	3		T13	1		T14	5
valid_sources[0x4a]	9300	1			T2	7		T3	13		T4	1
valid_sources[0x4b]	13915	1			T2	8		T3	2		T14	4
valid_sources[0x4c]	7930	1			T1	1		T2	7		T13	2
valid_sources[0x4d]	8389	1			T2	9		T14	7		T15	4
valid_sources[0x4e]	8146	1			T2	4		T14	6		T16	1
valid_sources[0x4f]	11820	1			T2	4		T14	4		T16	4
valid_sources[0x50]	9271	1			T2	8		T14	8		T15	1
valid_sources[0x51]	8137	1			T2	9		T13	2		T14	4
valid_sources[0x52]	9350	1			T2	13		T13	1		T14	2
valid_sources[0x53]	8417	1			T1	1		T2	7		T14	4
valid_sources[0x54]	7842	1			T2	15		T13	2		T14	2
valid_sources[0x55]	8014	1			T2	10		T4	1		T14	7
valid_sources[0x56]	8528	1			T2	6		T13	4		T14	4
valid_sources[0x57]	7728	1			T2	6		T14	3		T15	12
valid_sources[0x58]	8166	1			T2	7		T14	5		T16	2
valid_sources[0x59]	8050	1			T2	5		T13	2		T14	4
valid_sources[0x5a]	7772	1			T2	4		T4	2		T14	6
valid_sources[0x5b]	8377	1			T1	2		T2	2		T14	6
valid_sources[0x5c]	8154	1			T2	5		T14	6		T16	6
valid_sources[0x5d]	10072	1			T1	3		T2	3		T14	6
valid_sources[0x5e]	7994	1			T2	5		T4	2		T14	2
valid_sources[0x5f]	7790	1			T2	9		T14	5		T15	1
valid_sources[0x60]	8774	1			T2	12		T14	5		T16	1
valid_sources[0x61]	8024	1			T2	5		T3	4		T13	2
valid_sources[0x62]	8096	1			T2	3		T4	1		T13	1
valid_sources[0x63]	9787	1			T2	7		T13	1		T14	4
valid_sources[0x64]	8647	1			T2	5		T14	7		T15	3
valid_sources[0x65]	8161	1			T1	4		T2	4		T14	4
valid_sources[0x66]	8276	1			T2	8		T4	1		T13	1
valid_sources[0x67]	7948	1			T1	1		T2	5		T4	1
valid_sources[0x68]	9711	1			T2	6		T14	2		T15	10
valid_sources[0x69]	8483	1			T2	4		T13	2		T14	6
valid_sources[0x6a]	8420	1			T2	10		T14	3		T15	8
valid_sources[0x6b]	28851	1			T2	11		T13	3		T14	5
valid_sources[0x6c]	10286	1			T2	6		T14	8		T15	2
valid_sources[0x6d]	8903	1			T2	5		T13	1		T14	4
valid_sources[0x6e]	8395	1			T1	1		T2	10		T14	8
valid_sources[0x6f]	7816	1			T2	3		T4	2		T14	3
valid_sources[0x70]	10022	1			T2	12		T3	10		T13	1
valid_sources[0x71]	7664	1			T2	11		T14	6		T15	8
valid_sources[0x72]	8426	1			T2	4		T13	1		T14	3
valid_sources[0x73]	8575	1			T1	1		T2	8		T14	4
valid_sources[0x74]	9580	1			T2	4		T14	4		T16	5
valid_sources[0x75]	7846	1			T1	2		T2	5		T13	2
valid_sources[0x76]	10445	1			T2	8		T13	2		T14	4
valid_sources[0x77]	7556	1			T2	7		T4	2		T14	3
valid_sources[0x78]	8223	1			T2	7		T16	4		T25	6
valid_sources[0x79]	7912	1			T2	10		T13	2		T14	2
valid_sources[0x7a]	7887	1			T2	4		T3	10		T4	2
valid_sources[0x7b]	8146	1			T2	12		T14	1		T16	1
valid_sources[0x7c]	9057	1			T2	9		T4	1		T14	5
valid_sources[0x7d]	9721	1			T2	4		T14	5		T15	7
valid_sources[0x7e]	8011	1			T2	5		T4	1		T14	9
valid_sources[0x7f]	8096	1			T1	4		T2	9		T14	7
valid_sources[0x80]	7969	1			T2	2		T4	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1290424

1

T1

1

T2

453

T3

99

values[0x0]

all_enables

biggest_size

148075

1

T1

6

T2

368

T3

35

values[0x1]

all_enables

biggest_size

146507

1

T1

6

T2

331

T3

44