Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	97996335	12908	0	0
claim_transition_if_regwen_rd_A	97996335	937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97996335	12908	0	0
T31	50460	0	0	0
T56	0	3	0	0
T62	47266	0	0	0
T100	168780	6	0	0
T101	0	2	0	0
T102	0	14	0	0
T112	0	7	0	0
T160	0	1	0	0
T161	0	6	0	0
T162	0	3	0	0
T163	0	5	0	0
T164	0	3	0	0
T165	8537	0	0	0
T166	6488	0	0	0
T167	29347	0	0	0
T168	4768	0	0	0
T169	25792	0	0	0
T170	26825	0	0	0
T171	2292	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97996335	937	0	0
T33	21523	0	0	0
T101	155111	2	0	0
T104	18800	0	0	0
T105	23587	0	0	0
T106	44419	0	0	0
T107	4912	0	0	0
T108	2220	0	0	0
T109	1532	0	0	0
T110	19846	0	0	0
T111	30616	0	0	0
T125	0	11	0	0
T131	0	1	0	0
T137	0	8	0	0
T164	0	4	0	0
T172	0	25	0	0
T173	0	15	0	0
T174	0	39	0	0
T175	0	7	0	0
T176	0	2	0	0