Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1344356	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1549574

1

T1

1

T2

15

T3

1086

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2574885	1			T1	2		T2	5		T3	1051
values[0x0]	159554	1			T2	4		T3	370		T4	56
values[0x1]	159491	1			T1	1		T2	11		T3	302

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1066752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1827178

1

T1

2

T2

16

T3

1212

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9962	1			T3	8		T11	8		T13	3
valid_sources[0x01]	11866	1			T3	11		T11	5		T13	1
valid_sources[0x02]	8355	1			T11	4		T13	4		T16	7
valid_sources[0x03]	8761	1			T3	4		T11	1		T13	3
valid_sources[0x04]	7977	1			T3	18		T11	2		T14	4
valid_sources[0x05]	10509	1			T3	18		T11	8		T13	1
valid_sources[0x06]	10044	1			T3	3		T11	6		T15	3
valid_sources[0x07]	8009	1			T3	6		T11	4		T13	1
valid_sources[0x08]	13880	1			T3	6		T11	5		T13	2
valid_sources[0x09]	8285	1			T3	6		T11	5		T13	1
valid_sources[0x0a]	8196	1			T3	23		T14	7		T15	1
valid_sources[0x0b]	8490	1			T3	9		T11	7		T15	3
valid_sources[0x0c]	8249	1			T2	1		T3	8		T11	2
valid_sources[0x0d]	7982	1			T3	8		T11	5		T13	4
valid_sources[0x0e]	30153	1			T3	3		T11	3		T14	7
valid_sources[0x0f]	9439	1			T3	6		T11	10		T16	7
valid_sources[0x10]	10189	1			T3	2		T11	1		T16	4
valid_sources[0x11]	8050	1			T3	8		T11	7		T14	4
valid_sources[0x12]	10533	1			T11	4		T13	5		T15	1
valid_sources[0x13]	8644	1			T3	6		T11	8		T13	3
valid_sources[0x14]	7780	1			T3	7		T11	2		T15	2
valid_sources[0x15]	8440	1			T3	4		T11	3		T14	10
valid_sources[0x16]	8361	1			T3	3		T11	6		T14	2
valid_sources[0x17]	9635	1			T3	5		T11	4		T15	1
valid_sources[0x18]	8615	1			T3	10		T11	3		T13	6
valid_sources[0x19]	8999	1			T3	1		T11	1		T15	1
valid_sources[0x1a]	8583	1			T3	5		T11	9		T14	15
valid_sources[0x1b]	9706	1			T2	2		T3	16		T11	5
valid_sources[0x1c]	8839	1			T3	7		T11	3		T14	11
valid_sources[0x1d]	7923	1			T2	1		T3	4		T11	5
valid_sources[0x1e]	11118	1			T2	1		T3	2		T11	2
valid_sources[0x1f]	8429	1			T3	8		T13	5		T14	7
valid_sources[0x20]	13917	1			T3	14		T11	6		T14	16
valid_sources[0x21]	8177	1			T3	9		T11	2		T13	4
valid_sources[0x22]	9125	1			T3	3		T11	9		T16	2
valid_sources[0x23]	7886	1			T3	8		T11	1		T14	1
valid_sources[0x24]	8262	1			T3	17		T14	20		T15	1
valid_sources[0x25]	8537	1			T3	12		T11	3		T14	12
valid_sources[0x26]	9263	1			T3	7		T11	2		T13	6
valid_sources[0x27]	9875	1			T3	5		T11	5		T16	4
valid_sources[0x28]	8536	1			T3	8		T11	2		T15	1
valid_sources[0x29]	9383	1			T3	2		T11	7		T14	5
valid_sources[0x2a]	8952	1			T11	2		T13	6		T16	7
valid_sources[0x2b]	8137	1			T3	6		T13	1		T14	13
valid_sources[0x2c]	22987	1			T3	5		T11	1		T13	2
valid_sources[0x2d]	8210	1			T3	4		T11	5		T14	9
valid_sources[0x2e]	8934	1			T3	13		T11	4		T13	8
valid_sources[0x2f]	10394	1			T11	5		T14	1		T16	7
valid_sources[0x30]	9144	1			T3	6		T11	1		T13	2
valid_sources[0x31]	9414	1			T3	1		T11	10		T15	1
valid_sources[0x32]	11027	1			T3	1		T11	4		T13	4
valid_sources[0x33]	8514	1			T3	12		T14	4		T15	1
valid_sources[0x34]	8529	1			T3	2		T11	14		T13	2
valid_sources[0x35]	8689	1			T3	2		T11	13		T13	10
valid_sources[0x36]	67532	1			T3	7		T11	2		T15	1
valid_sources[0x37]	8679	1			T3	6		T11	1		T14	7
valid_sources[0x38]	8826	1			T3	5		T11	5		T13	1
valid_sources[0x39]	25080	1			T3	19		T11	3		T13	2
valid_sources[0x3a]	8084	1			T3	5		T11	5		T15	2
valid_sources[0x3b]	13193	1			T3	4		T11	4		T14	7
valid_sources[0x3c]	8805	1			T3	3		T11	2		T14	4
valid_sources[0x3d]	16123	1			T3	4		T11	4		T13	1
valid_sources[0x3e]	8005	1			T3	11		T11	1		T14	1
valid_sources[0x3f]	9130	1			T3	1		T11	3		T14	6
valid_sources[0x40]	9620	1			T3	2		T14	2		T16	7
valid_sources[0x41]	9890	1			T3	4		T11	8		T16	7
valid_sources[0x42]	8155	1			T3	8		T11	2		T13	4
valid_sources[0x43]	10503	1			T3	13		T4	887		T11	2
valid_sources[0x44]	9023	1			T3	4		T11	4		T16	7
valid_sources[0x45]	8032	1			T3	2		T11	10		T14	3
valid_sources[0x46]	8418	1			T3	5		T11	2		T13	1
valid_sources[0x47]	9458	1			T3	21		T11	8		T14	6
valid_sources[0x48]	16342	1			T3	4		T14	12		T16	7
valid_sources[0x49]	10812	1			T3	1		T11	4		T13	2
valid_sources[0x4a]	8294	1			T3	5		T11	2		T16	5
valid_sources[0x4b]	11840	1			T3	11		T11	2		T13	1
valid_sources[0x4c]	8077	1			T3	9		T11	10		T14	13
valid_sources[0x4d]	9618	1			T11	7		T15	1		T16	8
valid_sources[0x4e]	8332	1			T3	15		T11	7		T13	1
valid_sources[0x4f]	9470	1			T3	5		T11	6		T14	10
valid_sources[0x50]	8475	1			T3	3		T11	3		T13	1
valid_sources[0x51]	9123	1			T3	2		T11	5		T15	3
valid_sources[0x52]	8174	1			T3	2		T11	4		T13	1
valid_sources[0x53]	8102	1			T3	14		T11	2		T16	2
valid_sources[0x54]	8198	1			T3	4		T11	7		T13	1
valid_sources[0x55]	9990	1			T3	2		T11	2		T14	6
valid_sources[0x56]	8267	1			T3	3		T11	6		T14	12
valid_sources[0x57]	8299	1			T3	1		T11	3		T14	1
valid_sources[0x58]	8419	1			T11	8		T13	9		T14	1
valid_sources[0x59]	8234	1			T3	4		T13	4		T15	3
valid_sources[0x5a]	7599	1			T3	7		T11	4		T13	3
valid_sources[0x5b]	7949	1			T2	2		T11	1		T13	3
valid_sources[0x5c]	8206	1			T3	5		T11	7		T14	6
valid_sources[0x5d]	8887	1			T3	4		T11	7		T13	7
valid_sources[0x5e]	8492	1			T3	1		T11	2		T14	6
valid_sources[0x5f]	10992	1			T3	3		T11	1		T13	15
valid_sources[0x60]	10302	1			T3	17		T11	8		T13	2
valid_sources[0x61]	8263	1			T3	3		T11	9		T13	1
valid_sources[0x62]	8565	1			T3	29		T11	9		T14	3
valid_sources[0x63]	7755	1			T2	1		T3	5		T11	16
valid_sources[0x64]	16238	1			T3	14		T11	2		T13	2
valid_sources[0x65]	7964	1			T3	5		T11	7		T14	2
valid_sources[0x66]	8628	1			T3	6		T11	12		T14	1
valid_sources[0x67]	8198	1			T11	11		T14	6		T16	5
valid_sources[0x68]	9818	1			T3	3		T11	1		T15	2
valid_sources[0x69]	7829	1			T3	8		T11	7		T13	2
valid_sources[0x6a]	8068	1			T3	12		T13	3		T16	5
valid_sources[0x6b]	14881	1			T3	11		T11	9		T13	6
valid_sources[0x6c]	8206	1			T3	1		T11	4		T14	4
valid_sources[0x6d]	10232	1			T3	23		T11	3		T14	12
valid_sources[0x6e]	8270	1			T3	7		T11	6		T15	2
valid_sources[0x6f]	8133	1			T3	9		T11	5		T14	3
valid_sources[0x70]	8379	1			T11	3		T14	3		T16	3
valid_sources[0x71]	7750	1			T3	1		T14	10		T16	8
valid_sources[0x72]	8343	1			T3	3		T11	4		T14	5
valid_sources[0x73]	8473	1			T3	9		T11	1		T14	7
valid_sources[0x74]	8924	1			T3	8		T14	3		T16	6
valid_sources[0x75]	8657	1			T3	10		T11	11		T13	1
valid_sources[0x76]	8872	1			T3	5		T11	7		T14	2
valid_sources[0x77]	8094	1			T3	1		T13	1		T14	1
valid_sources[0x78]	8358	1			T11	1		T13	4		T14	5
valid_sources[0x79]	7605	1			T3	19		T11	2		T14	4
valid_sources[0x7a]	7999	1			T3	6		T11	5		T13	1
valid_sources[0x7b]	16671	1			T3	5		T11	3		T14	7
valid_sources[0x7c]	8175	1			T3	11		T11	6		T14	1
valid_sources[0x7d]	9267	1			T3	18		T11	3		T13	5
valid_sources[0x7e]	8097	1			T2	2		T3	5		T11	3
valid_sources[0x7f]	12137	1			T3	3		T11	10		T16	4
valid_sources[0x80]	23375	1			T3	3		T11	4		T16	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1274457

1

T1

1

T2

2

T3

495

values[0x0]

all_enables

biggest_size

138485

1

T2

4

T3

329

T4

44

values[0x1]

all_enables

biggest_size

136632

1

T2

9

T3

262

T4

56