Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	100246026	14448	0	0
claim_transition_if_regwen_rd_A	100246026	1303	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100246026	14448	0	0
T51	679678	13	0	0
T56	0	2	0	0
T63	353721	7	0	0
T71	3839	0	0	0
T91	224344	8	0	0
T100	0	4	0	0
T142	0	16	0	0
T146	0	2	0	0
T155	21283	0	0	0
T156	2778	0	0	0
T157	29259	0	0	0
T158	1638	0	0	0
T159	38779	0	0	0
T160	49329	0	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100246026	1303	0	0
T40	1086	0	0	0
T44	0	8	0	0
T53	256351	14	0	0
T58	27151	0	0	0
T59	36883	0	0	0
T83	0	13	0	0
T100	0	4	0	0
T106	0	87	0	0
T143	0	4	0	0
T168	0	261	0	0
T177	1303	0	0	0
T180	0	5	0	0
T181	0	2	0	0
T182	0	2	0	0
T183	24217	0	0	0
T184	39865	0	0	0
T185	26688	0	0	0
T186	757	0	0	0
T187	24468	0	0	0