Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1317589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1542133

1

T1

13

T2

2752

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2514920	1			T1	5		T2	4264		T4	470
values[0x0]	171862	1			T1	7		T2	395		T3	20
values[0x1]	172940	1			T1	8		T2	397		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1044692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1815030

1

T1

14

T2

3213

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9429	1			T2	13		T6	32		T14	1
valid_sources[0x01]	10617	1			T12	5		T6	15		T15	1
valid_sources[0x02]	10151	1			T2	10		T6	1		T14	6
valid_sources[0x03]	10027	1			T2	187		T6	9		T14	1
valid_sources[0x04]	9370	1			T2	15		T6	11		T14	3
valid_sources[0x05]	9805	1			T6	15		T14	5		T18	4
valid_sources[0x06]	9581	1			T2	4		T6	1		T14	9
valid_sources[0x07]	11021	1			T2	4		T6	2		T14	2
valid_sources[0x08]	10467	1			T2	13		T15	33		T17	4
valid_sources[0x09]	9663	1			T2	41		T6	7		T14	7
valid_sources[0x0a]	9417	1			T2	9		T6	9		T15	3
valid_sources[0x0b]	10872	1			T2	19		T6	2		T14	4
valid_sources[0x0c]	52026	1			T2	3		T6	31		T14	1
valid_sources[0x0d]	10816	1			T6	17		T15	11		T17	5
valid_sources[0x0e]	17868	1			T6	4		T17	9		T18	5
valid_sources[0x0f]	9507	1			T2	33		T6	5		T17	7
valid_sources[0x10]	11305	1			T2	34		T6	7		T14	4
valid_sources[0x11]	9823	1			T2	33		T6	4		T14	6
valid_sources[0x12]	9568	1			T2	12		T6	14		T17	2
valid_sources[0x13]	9985	1			T2	24		T6	18		T14	3
valid_sources[0x14]	9878	1			T2	13		T6	23		T14	1
valid_sources[0x15]	11109	1			T2	25		T16	107		T17	10
valid_sources[0x16]	11153	1			T2	5		T6	5		T14	7
valid_sources[0x17]	10602	1			T2	1		T6	13		T14	7
valid_sources[0x18]	36683	1			T6	12		T15	47		T17	6
valid_sources[0x19]	9182	1			T2	2		T6	15		T14	7
valid_sources[0x1a]	10093	1			T2	10		T6	39		T14	11
valid_sources[0x1b]	14235	1			T2	36		T6	11		T14	2
valid_sources[0x1c]	10000	1			T2	34		T6	8		T15	1
valid_sources[0x1d]	9590	1			T2	11		T6	8		T14	1
valid_sources[0x1e]	9452	1			T2	12		T6	16		T14	5
valid_sources[0x1f]	9637	1			T2	45		T6	25		T14	13
valid_sources[0x20]	9564	1			T2	5		T6	11		T14	2
valid_sources[0x21]	9238	1			T2	10		T6	5		T14	2
valid_sources[0x22]	9515	1			T2	9		T12	4		T6	2
valid_sources[0x23]	10829	1			T1	1		T2	23		T12	2
valid_sources[0x24]	9850	1			T2	56		T6	6		T15	29
valid_sources[0x25]	10889	1			T2	21		T12	1		T6	8
valid_sources[0x26]	10061	1			T2	3		T12	1		T14	13
valid_sources[0x27]	9379	1			T2	18		T6	8		T14	1
valid_sources[0x28]	9961	1			T2	11		T6	18		T14	15
valid_sources[0x29]	9797	1			T2	5		T6	15		T14	17
valid_sources[0x2a]	9595	1			T2	31		T6	5		T14	4
valid_sources[0x2b]	9604	1			T1	1		T2	35		T6	9
valid_sources[0x2c]	9438	1			T2	6		T6	2		T15	22
valid_sources[0x2d]	11568	1			T1	1		T6	21		T14	5
valid_sources[0x2e]	9437	1			T2	4		T6	3		T17	6
valid_sources[0x2f]	9496	1			T2	53		T6	21		T17	3
valid_sources[0x30]	82848	1			T6	4		T15	23		T18	11
valid_sources[0x31]	11237	1			T1	1		T2	20		T6	8
valid_sources[0x32]	9279	1			T2	17		T6	3		T17	2
valid_sources[0x33]	9579	1			T1	1		T2	12		T12	1
valid_sources[0x34]	9501	1			T6	29		T14	2		T17	4
valid_sources[0x35]	9409	1			T2	12		T12	4		T6	6
valid_sources[0x36]	9778	1			T2	21		T14	11		T15	21
valid_sources[0x37]	9536	1			T2	26		T6	6		T15	4
valid_sources[0x38]	10442	1			T1	1		T12	1		T6	12
valid_sources[0x39]	9846	1			T2	34		T6	2		T15	30
valid_sources[0x3a]	9609	1			T2	1		T6	5		T17	2
valid_sources[0x3b]	12969	1			T6	12		T14	4		T15	13
valid_sources[0x3c]	9746	1			T2	11		T12	1		T6	12
valid_sources[0x3d]	10924	1			T2	75		T14	2		T15	16
valid_sources[0x3e]	9746	1			T2	46		T6	22		T14	12
valid_sources[0x3f]	10692	1			T2	8		T6	3		T14	3
valid_sources[0x40]	10087	1			T2	30		T14	1		T15	8
valid_sources[0x41]	11198	1			T2	3		T14	8		T15	38
valid_sources[0x42]	9657	1			T2	10		T14	9		T17	3
valid_sources[0x43]	9629	1			T2	10		T6	5		T17	14
valid_sources[0x44]	9666	1			T2	51		T6	2		T17	6
valid_sources[0x45]	21788	1			T2	58		T6	1		T17	1
valid_sources[0x46]	9851	1			T2	12		T6	12		T14	6
valid_sources[0x47]	12086	1			T2	16		T6	27		T14	5
valid_sources[0x48]	10231	1			T6	4		T14	1		T15	7
valid_sources[0x49]	10225	1			T2	38		T6	8		T15	5
valid_sources[0x4a]	9848	1			T2	12		T14	10		T17	6
valid_sources[0x4b]	9622	1			T2	27		T12	3		T6	8
valid_sources[0x4c]	10978	1			T2	16		T6	12		T14	1
valid_sources[0x4d]	12447	1			T2	31		T14	1		T18	6
valid_sources[0x4e]	9804	1			T2	32		T6	21		T15	46
valid_sources[0x4f]	18884	1			T2	18		T6	9		T17	3
valid_sources[0x50]	9971	1			T2	1		T6	8		T17	2
valid_sources[0x51]	9597	1			T2	35		T6	11		T14	8
valid_sources[0x52]	13026	1			T2	16		T6	4		T17	2
valid_sources[0x53]	9399	1			T2	44		T6	8		T14	1
valid_sources[0x54]	9897	1			T2	21		T6	4		T14	8
valid_sources[0x55]	9813	1			T2	29		T6	12		T15	34
valid_sources[0x56]	9768	1			T1	1		T6	1		T14	2
valid_sources[0x57]	12290	1			T2	12		T13	21		T6	10
valid_sources[0x58]	11819	1			T2	10		T17	2		T18	16
valid_sources[0x59]	9414	1			T2	10		T14	2		T15	17
valid_sources[0x5a]	10493	1			T2	25		T6	21		T17	3
valid_sources[0x5b]	9521	1			T2	8		T6	7		T14	10
valid_sources[0x5c]	9795	1			T2	20		T6	2		T14	11
valid_sources[0x5d]	9715	1			T2	19		T6	15		T14	3
valid_sources[0x5e]	9348	1			T2	11		T6	1		T14	2
valid_sources[0x5f]	9719	1			T2	68		T17	3		T18	8
valid_sources[0x60]	9700	1			T2	36		T15	22		T17	2
valid_sources[0x61]	9578	1			T2	37		T12	1		T6	9
valid_sources[0x62]	12649	1			T2	19		T12	1		T6	2
valid_sources[0x63]	10600	1			T2	13		T6	2		T14	7
valid_sources[0x64]	9339	1			T2	4		T6	17		T17	3
valid_sources[0x65]	12540	1			T2	18		T6	10		T14	3
valid_sources[0x66]	11106	1			T2	12		T6	4		T17	5
valid_sources[0x67]	9609	1			T2	5		T15	22		T17	2
valid_sources[0x68]	11940	1			T2	11		T6	2		T14	1
valid_sources[0x69]	10901	1			T2	29		T6	2		T14	14
valid_sources[0x6a]	9548	1			T2	18		T6	7		T14	4
valid_sources[0x6b]	10653	1			T1	1		T2	86		T6	10
valid_sources[0x6c]	11637	1			T14	12		T15	24		T17	1
valid_sources[0x6d]	9767	1			T2	4		T6	5		T14	3
valid_sources[0x6e]	9559	1			T2	12		T12	2		T14	1
valid_sources[0x6f]	10147	1			T2	30		T6	19		T15	31
valid_sources[0x70]	9684	1			T2	4		T6	1		T15	6
valid_sources[0x71]	9350	1			T2	8		T6	5		T14	1
valid_sources[0x72]	9690	1			T2	5		T6	3		T14	15
valid_sources[0x73]	9248	1			T6	17		T15	27		T17	2
valid_sources[0x74]	9643	1			T6	18		T14	6		T17	3
valid_sources[0x75]	9674	1			T14	7		T17	3		T18	8
valid_sources[0x76]	11266	1			T2	8		T6	15		T15	6
valid_sources[0x77]	9750	1			T2	23		T6	5		T14	3
valid_sources[0x78]	11987	1			T6	11		T14	5		T17	7
valid_sources[0x79]	9446	1			T2	31		T6	3		T14	10
valid_sources[0x7a]	9629	1			T2	13		T6	9		T15	11
valid_sources[0x7b]	11097	1			T2	2		T6	21		T14	4
valid_sources[0x7c]	9627	1			T2	11		T6	22		T15	8
valid_sources[0x7d]	22206	1			T2	32		T14	3		T15	14
valid_sources[0x7e]	9685	1			T14	6		T17	3		T18	16
valid_sources[0x7f]	9847	1			T2	9		T12	2		T6	3
valid_sources[0x80]	11266	1			T14	5		T17	4		T18	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1244693

1

T1

2

T2

2081

T4

183

values[0x0]

all_enables

biggest_size

149123

1

T1

4

T2

342

T3

3

values[0x1]

all_enables

biggest_size

148317

1

T1

7

T2

329

T3

5