Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	99022595	14039	0	0
claim_transition_if_regwen_rd_A	99022595	1257	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99022595	14039	0	0
T10	83718	0	0	0
T11	53583	0	0	0
T43	237336	3	0	0
T49	673572	0	0	0
T50	0	2	0	0
T52	0	6	0	0
T55	23916	0	0	0
T87	0	9	0	0
T148	0	1	0	0
T151	0	17	0	0
T152	0	9	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	310884	0	0	0
T157	10823	0	0	0
T158	29878	0	0	0
T159	1627	0	0	0
T160	19952	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99022595	1257	0	0
T29	22979	0	0	0
T41	1397	0	0	0
T48	163069	0	0	0
T50	535077	24	0	0
T86	0	2	0	0
T107	0	6	0	0
T145	0	8	0	0
T148	0	16	0	0
T154	0	23	0	0
T155	0	3	0	0
T161	0	14	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	14743	0	0	0
T165	44416	0	0	0
T166	33720	0	0	0
T167	3877	0	0	0
T168	19751	0	0	0
T169	18131	0	0	0