Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1630168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1852851

1

T2

11

T3

844

T5

95

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3134041	1			T2	5		T3	658		T5	85
values[0x0]	173879	1			T2	8		T3	306		T5	35
values[0x1]	175099	1			T2	7		T3	310		T5	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1294283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2188736

1

T2

15

T3

941

T5

107

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8590	1			T3	3		T10	7		T11	8
valid_sources[0x01]	8295	1			T3	5		T10	4		T12	3
valid_sources[0x02]	9040	1			T3	7		T5	2		T10	7
valid_sources[0x03]	8487	1			T3	8		T5	1		T10	3
valid_sources[0x04]	8433	1			T3	5		T10	7		T11	1
valid_sources[0x05]	8869	1			T3	5		T5	2		T10	3
valid_sources[0x06]	11992	1			T2	3		T3	6		T12	7
valid_sources[0x07]	8625	1			T3	3		T5	1		T10	6
valid_sources[0x08]	8593	1			T3	7		T10	3		T12	7
valid_sources[0x09]	9655	1			T3	6		T10	6		T12	4
valid_sources[0x0a]	8567	1			T3	6		T10	4		T11	3
valid_sources[0x0b]	9571	1			T3	7		T10	6		T12	7
valid_sources[0x0c]	10012	1			T3	2		T10	8		T6	17
valid_sources[0x0d]	8914	1			T3	3		T5	1		T10	2
valid_sources[0x0e]	9349	1			T3	5		T5	1		T10	5
valid_sources[0x0f]	8486	1			T3	5		T10	13		T12	6
valid_sources[0x10]	10251	1			T3	5		T10	4		T6	17
valid_sources[0x11]	8912	1			T3	4		T5	1		T11	3
valid_sources[0x12]	8680	1			T3	3		T5	2		T10	4
valid_sources[0x13]	9095	1			T3	1		T10	9		T12	3
valid_sources[0x14]	8548	1			T3	4		T10	4		T12	8
valid_sources[0x15]	8598	1			T3	8		T5	2		T10	7
valid_sources[0x16]	31788	1			T3	4		T5	1		T10	10
valid_sources[0x17]	8999	1			T3	9		T11	1		T12	7
valid_sources[0x18]	9177	1			T3	7		T5	2		T10	7
valid_sources[0x19]	8697	1			T3	6		T10	5		T12	11
valid_sources[0x1a]	8612	1			T3	9		T10	1		T12	5
valid_sources[0x1b]	8960	1			T3	5		T5	2		T10	10
valid_sources[0x1c]	9176	1			T3	6		T5	1		T9	1
valid_sources[0x1d]	8532	1			T3	4		T5	1		T10	15
valid_sources[0x1e]	13048	1			T3	1		T10	2		T12	6
valid_sources[0x1f]	12986	1			T3	4		T5	1		T10	7
valid_sources[0x20]	9322	1			T3	3		T10	2		T12	11
valid_sources[0x21]	11527	1			T3	5		T5	1		T10	3
valid_sources[0x22]	12110	1			T3	4		T5	1		T10	3
valid_sources[0x23]	8623	1			T3	6		T5	1		T10	4
valid_sources[0x24]	9970	1			T3	4		T9	2		T10	5
valid_sources[0x25]	8839	1			T3	3		T5	1		T10	3
valid_sources[0x26]	8810	1			T3	6		T10	1		T12	4
valid_sources[0x27]	9034	1			T3	6		T10	7		T6	17
valid_sources[0x28]	8971	1			T3	2		T10	2		T11	3
valid_sources[0x29]	8539	1			T3	4		T10	5		T12	3
valid_sources[0x2a]	8796	1			T3	12		T10	8		T12	2
valid_sources[0x2b]	8384	1			T3	3		T5	1		T10	8
valid_sources[0x2c]	10614	1			T3	2		T5	2		T10	3
valid_sources[0x2d]	8832	1			T3	6		T10	7		T12	14
valid_sources[0x2e]	8316	1			T3	6		T10	4		T11	7
valid_sources[0x2f]	13212	1			T3	4		T10	4		T12	10
valid_sources[0x30]	10143	1			T3	5		T10	10		T12	5
valid_sources[0x31]	8905	1			T3	4		T10	8		T12	4
valid_sources[0x32]	8462	1			T3	6		T10	3		T12	3
valid_sources[0x33]	9357	1			T3	8		T5	1		T10	4
valid_sources[0x34]	8911	1			T3	2		T10	1		T11	7
valid_sources[0x35]	8786	1			T3	2		T10	5		T12	5
valid_sources[0x36]	8403	1			T3	4		T5	2		T10	17
valid_sources[0x37]	11971	1			T3	2		T10	2		T12	6
valid_sources[0x38]	8780	1			T3	6		T10	3		T12	11
valid_sources[0x39]	53603	1			T3	5		T5	2		T10	3
valid_sources[0x3a]	8614	1			T3	1		T5	2		T10	4
valid_sources[0x3b]	10676	1			T3	4		T9	2		T10	12
valid_sources[0x3c]	8675	1			T3	4		T10	7		T12	10
valid_sources[0x3d]	10077	1			T3	2		T5	1		T10	1
valid_sources[0x3e]	8838	1			T3	2		T10	3		T11	1
valid_sources[0x3f]	11702	1			T3	3		T5	2		T10	1
valid_sources[0x40]	8620	1			T10	4		T12	9		T14	2
valid_sources[0x41]	9768	1			T3	5		T5	2		T10	12
valid_sources[0x42]	10291	1			T3	4		T10	3		T12	8
valid_sources[0x43]	8620	1			T3	5		T5	2		T10	6
valid_sources[0x44]	49262	1			T3	5		T10	10		T12	2
valid_sources[0x45]	8790	1			T3	3		T10	6		T12	8
valid_sources[0x46]	10373	1			T3	7		T10	1		T12	2
valid_sources[0x47]	8971	1			T3	6		T10	2		T12	4
valid_sources[0x48]	9129	1			T3	6		T10	4		T12	9
valid_sources[0x49]	9157	1			T3	3		T5	1		T10	4
valid_sources[0x4a]	8638	1			T2	2		T3	6		T10	3
valid_sources[0x4b]	88505	1			T3	6		T5	1		T10	4
valid_sources[0x4c]	8885	1			T3	3		T5	1		T10	6
valid_sources[0x4d]	10359	1			T3	6		T5	1		T10	6
valid_sources[0x4e]	8894	1			T3	3		T5	1		T10	7
valid_sources[0x4f]	9745	1			T3	7		T10	2		T12	7
valid_sources[0x50]	68314	1			T3	5		T10	7		T12	5
valid_sources[0x51]	11811	1			T3	4		T5	2		T10	9
valid_sources[0x52]	8704	1			T3	5		T9	2		T10	11
valid_sources[0x53]	10201	1			T3	4		T10	5		T12	6
valid_sources[0x54]	13730	1			T3	6		T6	17		T12	1
valid_sources[0x55]	8588	1			T3	6		T12	13		T14	4
valid_sources[0x56]	24571	1			T3	4		T10	2		T6	14940
valid_sources[0x57]	9833	1			T3	7		T12	15		T14	3
valid_sources[0x58]	8652	1			T3	8		T10	9		T12	10
valid_sources[0x59]	8569	1			T3	4		T10	1		T11	26
valid_sources[0x5a]	9614	1			T3	4		T5	1		T10	2
valid_sources[0x5b]	8532	1			T3	9		T5	3		T10	5
valid_sources[0x5c]	8553	1			T2	2		T3	4		T10	1
valid_sources[0x5d]	12031	1			T3	6		T11	5		T12	4
valid_sources[0x5e]	9028	1			T3	5		T10	3		T12	7
valid_sources[0x5f]	10971	1			T3	6		T5	1		T10	3
valid_sources[0x60]	83403	1			T3	4		T5	2		T10	2
valid_sources[0x61]	16705	1			T3	3		T5	1		T10	4
valid_sources[0x62]	10810	1			T3	9		T5	1		T10	4
valid_sources[0x63]	8621	1			T3	7		T10	2		T12	2
valid_sources[0x64]	9511	1			T2	1		T3	5		T5	1
valid_sources[0x65]	51278	1			T3	4		T5	1		T10	4
valid_sources[0x66]	8879	1			T3	2		T10	8		T12	7
valid_sources[0x67]	9630	1			T3	11		T10	8		T11	6
valid_sources[0x68]	11263	1			T3	3		T5	1		T10	1
valid_sources[0x69]	16100	1			T3	9		T5	2		T10	2
valid_sources[0x6a]	8855	1			T3	5		T10	2		T12	4
valid_sources[0x6b]	9514	1			T3	6		T10	3		T6	2
valid_sources[0x6c]	8806	1			T3	3		T10	5		T12	9
valid_sources[0x6d]	14711	1			T3	4		T10	1		T12	6
valid_sources[0x6e]	12681	1			T3	7		T10	5		T6	17
valid_sources[0x6f]	8787	1			T3	4		T5	1		T10	5
valid_sources[0x70]	64723	1			T3	5		T10	7		T12	12
valid_sources[0x71]	9911	1			T3	8		T5	1		T10	11
valid_sources[0x72]	8960	1			T3	6		T12	11		T14	2
valid_sources[0x73]	8519	1			T3	8		T10	7		T12	5
valid_sources[0x74]	8667	1			T3	2		T10	8		T12	3
valid_sources[0x75]	9838	1			T3	6		T5	1		T10	4
valid_sources[0x76]	10584	1			T3	3		T9	1		T10	8
valid_sources[0x77]	8996	1			T3	7		T5	1		T10	2
valid_sources[0x78]	8780	1			T3	6		T5	1		T10	2
valid_sources[0x79]	8624	1			T3	6		T10	3		T6	17
valid_sources[0x7a]	109960	1			T3	6		T5	1		T10	5
valid_sources[0x7b]	8559	1			T3	5		T10	12		T12	12
valid_sources[0x7c]	15610	1			T3	1		T5	2		T10	3
valid_sources[0x7d]	13919	1			T3	6		T5	2		T10	4
valid_sources[0x7e]	9162	1			T3	3		T5	1		T10	1
valid_sources[0x7f]	8494	1			T3	2		T10	6		T12	12
valid_sources[0x80]	10780	1			T3	11		T5	2		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1552291

1

T3

308

T5

46

T4

295

values[0x0]

all_enables

biggest_size

150616

1

T2

6

T3

272

T5

24

values[0x1]

all_enables

biggest_size

149944

1

T2

5

T3

264

T5

25