Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	104981655	16053	0	0
claim_transition_if_regwen_rd_A	104981655	1535	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104981655	16053	0	0
T6	600724	4	0	0
T12	43927	0	0	0
T13	242510	0	0	0
T14	7114	0	0	0
T15	30063	0	0	0
T27	857	0	0	0
T28	1178	0	0	0
T32	26934	0	0	0
T35	7283	0	0	0
T37	0	5	0	0
T40	0	7	0	0
T42	0	3	0	0
T43	0	1	0	0
T50	0	6	0	0
T54	7170	0	0	0
T110	0	3	0	0
T114	0	3	0	0
T153	0	1	0	0
T154	0	8	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104981655	1535	0	0
T6	600724	24	0	0
T12	43927	0	0	0
T13	242510	0	0	0
T14	7114	0	0	0
T15	30063	0	0	0
T27	857	0	0	0
T28	1178	0	0	0
T32	26934	0	0	0
T35	7283	0	0	0
T37	0	15	0	0
T54	7170	0	0	0
T110	0	7	0	0
T119	0	4	0	0
T121	0	30	0	0
T131	0	166	0	0
T155	0	11	0	0
T156	0	36	0	0
T157	0	5	0	0
T158	0	50	0	0