Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1676303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1898711

1

T1

211

T2

1056

T3

236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3234088	1			T1	159		T2	812		T3	241
values[0x0]	170117	1			T1	76		T2	407		T3	77
values[0x1]	170809	1			T1	84		T2	393		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1332403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2242611

1

T1

236

T2

1192

T3

267

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7883	1			T2	8		T3	1		T12	2
valid_sources[0x01]	8207	1			T2	11		T12	3		T13	3
valid_sources[0x02]	34715	1			T2	8		T11	8		T14	4
valid_sources[0x03]	9954	1			T1	4		T2	2		T3	1
valid_sources[0x04]	8631	1			T1	2		T2	12		T11	4
valid_sources[0x05]	9275	1			T2	6		T3	3		T11	2
valid_sources[0x06]	8399	1			T1	1		T2	7		T3	1
valid_sources[0x07]	9576	1			T1	2		T2	7		T3	2
valid_sources[0x08]	8057	1			T2	5		T3	4		T12	2
valid_sources[0x09]	119812	1			T1	2		T2	4		T11	9
valid_sources[0x0a]	54122	1			T2	7		T3	2		T11	28
valid_sources[0x0b]	8352	1			T1	3		T2	1		T3	1
valid_sources[0x0c]	8311	1			T2	7		T3	2		T12	1
valid_sources[0x0d]	20789	1			T2	8		T14	2		T15	11
valid_sources[0x0e]	8198	1			T2	10		T3	1		T11	16
valid_sources[0x0f]	7842	1			T2	6		T3	2		T11	19
valid_sources[0x10]	8109	1			T2	6		T12	6		T15	9
valid_sources[0x11]	8081	1			T2	5		T3	1		T11	9
valid_sources[0x12]	8068	1			T2	4		T3	2		T13	2
valid_sources[0x13]	46870	1			T2	8		T3	5		T11	4
valid_sources[0x14]	83174	1			T1	2		T2	3		T3	1
valid_sources[0x15]	8094	1			T1	5		T2	5		T12	3
valid_sources[0x16]	7781	1			T2	3		T3	4		T14	2
valid_sources[0x17]	9499	1			T2	7		T3	1		T11	24
valid_sources[0x18]	8659	1			T2	3		T11	32		T15	7
valid_sources[0x19]	9283	1			T1	2		T2	6		T15	10
valid_sources[0x1a]	8171	1			T1	4		T2	6		T14	1
valid_sources[0x1b]	8079	1			T2	5		T3	2		T15	6
valid_sources[0x1c]	12736	1			T1	11		T2	6		T3	1
valid_sources[0x1d]	8322	1			T2	5		T3	2		T11	22
valid_sources[0x1e]	13680	1			T1	2		T2	7		T13	6
valid_sources[0x1f]	7841	1			T1	1		T2	2		T3	3
valid_sources[0x20]	7836	1			T2	4		T11	8		T13	3
valid_sources[0x21]	8034	1			T2	6		T15	5		T16	2
valid_sources[0x22]	8628	1			T2	8		T13	1		T14	1
valid_sources[0x23]	7838	1			T2	9		T3	2		T14	1
valid_sources[0x24]	7933	1			T2	6		T3	4		T12	3
valid_sources[0x25]	8502	1			T1	1		T2	10		T3	3
valid_sources[0x26]	9728	1			T2	6		T3	2		T13	1
valid_sources[0x27]	7953	1			T1	7		T2	7		T3	3
valid_sources[0x28]	8114	1			T1	2		T2	8		T12	6
valid_sources[0x29]	13028	1			T1	3		T2	6		T3	4
valid_sources[0x2a]	8040	1			T2	8		T3	1		T12	7
valid_sources[0x2b]	7960	1			T2	7		T3	1		T15	9
valid_sources[0x2c]	8868	1			T2	9		T11	20		T12	2
valid_sources[0x2d]	8417	1			T1	5		T2	7		T3	4
valid_sources[0x2e]	8244	1			T2	13		T3	2		T11	2
valid_sources[0x2f]	8438	1			T2	6		T11	17		T14	2
valid_sources[0x30]	8277	1			T2	7		T3	1		T15	8
valid_sources[0x31]	11254	1			T1	1		T2	6		T3	7
valid_sources[0x32]	8103	1			T2	3		T3	5		T15	11
valid_sources[0x33]	9691	1			T2	4		T11	27		T12	8
valid_sources[0x34]	10503	1			T2	9		T3	1		T12	7
valid_sources[0x35]	8040	1			T1	1		T2	5		T3	3
valid_sources[0x36]	8144	1			T2	6		T3	1		T11	14
valid_sources[0x37]	110437	1			T1	1		T2	7		T3	1
valid_sources[0x38]	10239	1			T1	7		T2	6		T3	2
valid_sources[0x39]	9759	1			T2	4		T3	2		T11	8
valid_sources[0x3a]	9056	1			T2	4		T3	2		T11	34
valid_sources[0x3b]	7692	1			T2	7		T3	1		T11	11
valid_sources[0x3c]	8210	1			T1	1		T2	8		T11	5
valid_sources[0x3d]	11342	1			T2	7		T3	1		T13	2
valid_sources[0x3e]	8299	1			T1	1		T2	7		T10	8
valid_sources[0x3f]	9557	1			T2	15		T3	1		T14	2
valid_sources[0x40]	9625	1			T2	3		T3	6		T15	8
valid_sources[0x41]	8288	1			T2	6		T3	1		T13	3
valid_sources[0x42]	8042	1			T2	5		T3	1		T15	12
valid_sources[0x43]	8077	1			T2	5		T3	1		T11	2
valid_sources[0x44]	11586	1			T2	6		T3	3		T11	7
valid_sources[0x45]	40853	1			T2	7		T3	2		T11	2
valid_sources[0x46]	8402	1			T2	7		T3	1		T15	12
valid_sources[0x47]	8204	1			T1	5		T2	6		T11	3
valid_sources[0x48]	7956	1			T2	8		T11	1		T15	10
valid_sources[0x49]	7826	1			T2	7		T3	5		T11	11
valid_sources[0x4a]	8234	1			T2	4		T15	6		T16	6
valid_sources[0x4b]	8313	1			T2	6		T3	2		T15	13
valid_sources[0x4c]	9687	1			T2	5		T3	3		T13	1
valid_sources[0x4d]	8480	1			T2	4		T3	3		T10	3
valid_sources[0x4e]	8376	1			T1	1		T2	5		T3	3
valid_sources[0x4f]	101297	1			T2	6		T14	4		T15	7
valid_sources[0x50]	8512	1			T2	5		T3	3		T11	20
valid_sources[0x51]	8243	1			T1	4		T2	9		T11	8
valid_sources[0x52]	8227	1			T1	1		T2	10		T3	1
valid_sources[0x53]	7739	1			T2	10		T3	2		T11	27
valid_sources[0x54]	23324	1			T1	2		T2	4		T3	4
valid_sources[0x55]	33909	1			T2	2		T3	1		T12	3
valid_sources[0x56]	8490	1			T1	1		T2	8		T3	6
valid_sources[0x57]	8193	1			T2	3		T3	1		T11	12
valid_sources[0x58]	8120	1			T2	4		T3	2		T12	1
valid_sources[0x59]	8313	1			T1	1		T2	7		T12	3
valid_sources[0x5a]	8088	1			T2	6		T3	2		T15	14
valid_sources[0x5b]	12046	1			T1	6		T2	2		T11	12
valid_sources[0x5c]	9304	1			T1	3		T2	6		T3	1
valid_sources[0x5d]	8026	1			T2	6		T3	3		T11	16
valid_sources[0x5e]	8005	1			T1	3		T2	9		T3	2
valid_sources[0x5f]	8100	1			T2	4		T11	17		T14	2
valid_sources[0x60]	8017	1			T1	1		T2	10		T3	2
valid_sources[0x61]	10710	1			T1	4		T2	6		T15	13
valid_sources[0x62]	8030	1			T2	8		T3	2		T13	3
valid_sources[0x63]	9177	1			T1	1		T2	6		T3	1
valid_sources[0x64]	8236	1			T2	7		T3	2		T11	13
valid_sources[0x65]	9311	1			T2	8		T11	12		T12	1
valid_sources[0x66]	82299	1			T1	2		T2	6		T3	3
valid_sources[0x67]	8197	1			T2	7		T3	1		T11	8
valid_sources[0x68]	8025	1			T2	5		T3	2		T11	23
valid_sources[0x69]	8479	1			T1	1		T2	3		T3	2
valid_sources[0x6a]	9887	1			T1	6		T2	7		T15	12
valid_sources[0x6b]	8467	1			T1	4		T2	3		T3	1
valid_sources[0x6c]	9460	1			T1	1		T2	9		T3	1
valid_sources[0x6d]	109250	1			T1	2		T2	4		T3	2
valid_sources[0x6e]	8053	1			T1	1		T2	6		T3	1
valid_sources[0x6f]	8046	1			T1	5		T2	6		T3	4
valid_sources[0x70]	8335	1			T2	2		T3	4		T14	1
valid_sources[0x71]	22739	1			T1	3		T2	7		T3	1
valid_sources[0x72]	7768	1			T2	8		T3	2		T14	1
valid_sources[0x73]	8183	1			T2	6		T13	1		T15	8
valid_sources[0x74]	7874	1			T2	9		T3	1		T11	8
valid_sources[0x75]	9772	1			T2	10		T13	1		T14	1
valid_sources[0x76]	8034	1			T2	3		T3	3		T11	14
valid_sources[0x77]	8316	1			T1	3		T2	3		T3	6
valid_sources[0x78]	8374	1			T2	5		T3	2		T15	5
valid_sources[0x79]	8222	1			T2	5		T3	2		T13	1
valid_sources[0x7a]	10327	1			T2	4		T11	7		T12	1
valid_sources[0x7b]	8326	1			T2	5		T3	2		T11	35
valid_sources[0x7c]	7749	1			T2	5		T3	1		T11	10
valid_sources[0x7d]	8214	1			T2	6		T3	2		T11	2
valid_sources[0x7e]	8154	1			T1	1		T2	4		T3	3
valid_sources[0x7f]	8259	1			T2	6		T3	2		T15	9
valid_sources[0x80]	7890	1			T2	5		T3	3		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1604294

1

T1

69

T2

359

T3

109

values[0x0]

all_enables

biggest_size

147881

1

T1

69

T2

362

T3

70

values[0x1]

all_enables

biggest_size

146536

1

T1

73

T2

335

T3

57