Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106362944	14539	0	0
claim_transition_if_regwen_rd_A	106362944	1829	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106362944	14539	0	0
T20	148635	8	0	0
T21	366614	0	0	0
T22	20426	0	0	0
T23	159782	0	0	0
T41	31137	0	0	0
T42	236933	0	0	0
T54	0	1	0	0
T57	43732	0	0	0
T62	0	2	0	0
T63	0	11	0	0
T78	0	15	0	0
T83	1046	0	0	0
T91	0	2	0	0
T101	0	1	0	0
T123	0	1	0	0
T163	0	13	0	0
T164	0	3	0	0
T165	35595	0	0	0
T166	4180	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106362944	1829	0	0
T91	340477	11	0	0
T124	0	13	0	0
T132	0	256	0	0
T133	0	3	0	0
T160	0	4	0	0
T167	0	8	0	0
T168	0	3	0	0
T169	0	195	0	0
T170	0	73	0	0
T171	0	5	0	0
T172	26482	0	0	0
T173	1523	0	0	0
T174	65452	0	0	0
T175	1031	0	0	0
T176	159948	0	0	0
T177	23114	0	0	0
T178	62033	0	0	0
T179	14064	0	0	0
T180	787	0	0	0