Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1671921

1

T1

1559

T2

2

T3

1447

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2804210	1			T1	1902		T2	2		T3	1809
values[0x0]	163561	1			T1	317		T2	1		T3	308
values[0x1]	164070	1			T1	355		T3	316		T5	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1160111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1971730

1

T1

1761

T2

3

T3

1655

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8343	1			T1	15		T5	6		T11	3
valid_sources[0x01]	6609	1			T1	8		T5	4		T12	1
valid_sources[0x02]	36926	1			T1	11		T5	3		T11	6
valid_sources[0x03]	7330	1			T1	12		T3	15		T11	1
valid_sources[0x04]	6655	1			T1	13		T3	3		T5	3
valid_sources[0x05]	7081	1			T1	12		T3	30		T5	5
valid_sources[0x06]	7645	1			T1	14		T5	3		T12	4
valid_sources[0x07]	6888	1			T1	15		T11	1		T12	5
valid_sources[0x08]	8092	1			T1	2		T11	3		T12	5
valid_sources[0x09]	7113	1			T1	12		T5	4		T11	3
valid_sources[0x0a]	15297	1			T1	11		T11	1		T12	4
valid_sources[0x0b]	7161	1			T1	7		T5	2		T11	3
valid_sources[0x0c]	25906	1			T1	12		T11	2		T12	5
valid_sources[0x0d]	6857	1			T1	9		T11	2		T12	7
valid_sources[0x0e]	7018	1			T1	9		T5	11		T11	1
valid_sources[0x0f]	7000	1			T1	8		T5	5		T11	1
valid_sources[0x10]	6925	1			T1	6		T5	1		T11	1
valid_sources[0x11]	8533	1			T1	10		T3	8		T5	1
valid_sources[0x12]	8557	1			T1	9		T12	7		T14	5
valid_sources[0x13]	7422	1			T1	11		T5	6		T11	3
valid_sources[0x14]	8429	1			T1	9		T5	2		T11	1
valid_sources[0x15]	126675	1			T1	7		T11	1		T12	3
valid_sources[0x16]	6810	1			T1	5		T5	5		T11	5
valid_sources[0x17]	7447	1			T1	9		T11	4		T12	6
valid_sources[0x18]	7140	1			T1	20		T3	83		T5	3
valid_sources[0x19]	7371	1			T1	13		T3	25		T5	3
valid_sources[0x1a]	6624	1			T1	7		T12	9		T13	6
valid_sources[0x1b]	6862	1			T1	8		T3	45		T5	1
valid_sources[0x1c]	36855	1			T1	4		T12	4		T14	3
valid_sources[0x1d]	9564	1			T1	7		T5	5		T11	4
valid_sources[0x1e]	50845	1			T1	19		T5	1		T11	1
valid_sources[0x1f]	6991	1			T1	2		T12	4		T14	8
valid_sources[0x20]	64625	1			T1	6		T3	7		T5	3
valid_sources[0x21]	6968	1			T1	10		T5	1		T12	4
valid_sources[0x22]	7002	1			T1	9		T5	10		T11	3
valid_sources[0x23]	6650	1			T1	16		T5	1		T11	1
valid_sources[0x24]	6741	1			T1	8		T3	29		T5	2
valid_sources[0x25]	6686	1			T1	12		T3	27		T12	7
valid_sources[0x26]	7589	1			T1	6		T5	7		T11	5
valid_sources[0x27]	7371	1			T1	9		T5	1		T11	2
valid_sources[0x28]	6553	1			T1	10		T3	69		T11	4
valid_sources[0x29]	6814	1			T1	12		T11	1		T12	1
valid_sources[0x2a]	7254	1			T1	12		T12	2		T14	13
valid_sources[0x2b]	17348	1			T1	8		T3	11		T11	1
valid_sources[0x2c]	7031	1			T1	11		T5	2		T11	3
valid_sources[0x2d]	7035	1			T1	9		T5	2		T12	1
valid_sources[0x2e]	7001	1			T1	11		T5	1		T12	3
valid_sources[0x2f]	6821	1			T1	9		T11	2		T12	6
valid_sources[0x30]	6892	1			T1	11		T11	3		T12	2
valid_sources[0x31]	66366	1			T1	10		T5	3		T12	2
valid_sources[0x32]	7088	1			T1	6		T5	8		T11	3
valid_sources[0x33]	6383	1			T1	10		T11	3		T12	5
valid_sources[0x34]	6795	1			T1	9		T5	4		T12	6
valid_sources[0x35]	6676	1			T1	10		T5	5		T12	8
valid_sources[0x36]	7101	1			T1	21		T11	3		T12	7
valid_sources[0x37]	7867	1			T1	9		T11	1		T12	6
valid_sources[0x38]	8718	1			T1	8		T5	3		T4	1899
valid_sources[0x39]	6967	1			T1	11		T3	23		T5	1
valid_sources[0x3a]	7406	1			T1	9		T11	1		T12	3
valid_sources[0x3b]	8817	1			T1	5		T5	2		T11	3
valid_sources[0x3c]	7765	1			T1	8		T5	4		T12	2
valid_sources[0x3d]	8495	1			T1	9		T5	8		T11	3
valid_sources[0x3e]	9032	1			T1	17		T5	3		T11	4
valid_sources[0x3f]	7078	1			T1	7		T3	57		T5	3
valid_sources[0x40]	7343	1			T1	5		T10	351		T11	1
valid_sources[0x41]	6863	1			T1	6		T5	3		T12	7
valid_sources[0x42]	6700	1			T1	15		T5	1		T11	4
valid_sources[0x43]	15903	1			T1	12		T5	3		T11	2
valid_sources[0x44]	6906	1			T1	10		T5	4		T11	2
valid_sources[0x45]	6819	1			T1	11		T12	6		T13	37
valid_sources[0x46]	6932	1			T1	6		T11	1		T12	10
valid_sources[0x47]	6990	1			T1	10		T5	4		T11	4
valid_sources[0x48]	6638	1			T1	11		T11	5		T12	4
valid_sources[0x49]	7110	1			T1	8		T3	18		T5	1
valid_sources[0x4a]	7375	1			T1	8		T11	1		T12	8
valid_sources[0x4b]	10882	1			T1	8		T5	7		T12	6
valid_sources[0x4c]	7187	1			T1	9		T5	4		T12	11
valid_sources[0x4d]	6979	1			T1	12		T11	1		T12	7
valid_sources[0x4e]	7039	1			T1	8		T5	2		T12	2
valid_sources[0x4f]	7054	1			T1	15		T5	3		T11	4
valid_sources[0x50]	6998	1			T1	9		T5	5		T11	4
valid_sources[0x51]	6593	1			T1	10		T5	1		T12	5
valid_sources[0x52]	8709	1			T1	10		T3	14		T5	1
valid_sources[0x53]	7313	1			T1	9		T5	2		T11	4
valid_sources[0x54]	6423	1			T1	12		T12	6		T14	1
valid_sources[0x55]	29243	1			T1	7		T3	162		T5	5
valid_sources[0x56]	6823	1			T1	8		T5	6		T12	1
valid_sources[0x57]	7025	1			T1	8		T3	7		T5	1
valid_sources[0x58]	6528	1			T1	12		T5	2		T12	1
valid_sources[0x59]	43766	1			T1	12		T3	11		T5	1
valid_sources[0x5a]	6906	1			T1	8		T5	7		T11	1
valid_sources[0x5b]	12678	1			T1	11		T3	15		T5	5
valid_sources[0x5c]	10164	1			T1	3		T11	4		T12	4
valid_sources[0x5d]	6928	1			T1	12		T5	7		T11	1
valid_sources[0x5e]	14622	1			T1	18		T3	24		T12	3
valid_sources[0x5f]	6612	1			T1	10		T3	4		T5	3
valid_sources[0x60]	7039	1			T1	12		T5	1		T12	6
valid_sources[0x61]	10636	1			T1	11		T3	30		T5	5
valid_sources[0x62]	8856	1			T1	11		T3	26		T5	2
valid_sources[0x63]	7123	1			T1	6		T5	1		T11	1
valid_sources[0x64]	6952	1			T1	12		T5	7		T12	5
valid_sources[0x65]	7106	1			T1	11		T3	8		T5	4
valid_sources[0x66]	8561	1			T1	7		T5	7		T11	1
valid_sources[0x67]	12570	1			T1	19		T5	9		T12	12
valid_sources[0x68]	6505	1			T1	6		T5	9		T11	3
valid_sources[0x69]	32392	1			T1	13		T12	9		T14	7
valid_sources[0x6a]	6981	1			T1	2		T3	119		T5	2
valid_sources[0x6b]	7205	1			T1	6		T3	61		T5	1
valid_sources[0x6c]	7160	1			T1	8		T3	49		T5	2
valid_sources[0x6d]	6852	1			T1	12		T11	1		T12	6
valid_sources[0x6e]	8403	1			T1	12		T3	9		T5	6
valid_sources[0x6f]	21831	1			T1	7		T5	1		T11	2
valid_sources[0x70]	10017	1			T1	16		T11	6		T12	5
valid_sources[0x71]	7028	1			T1	11		T3	2		T11	1
valid_sources[0x72]	8768	1			T1	16		T11	1		T12	4
valid_sources[0x73]	39837	1			T1	7		T3	30		T5	12
valid_sources[0x74]	6851	1			T1	10		T5	2		T12	5
valid_sources[0x75]	45519	1			T1	17		T5	4		T11	2
valid_sources[0x76]	6893	1			T1	6		T5	6		T11	2
valid_sources[0x77]	7649	1			T1	7		T5	2		T12	10
valid_sources[0x78]	7316	1			T1	4		T12	10		T13	1
valid_sources[0x79]	6655	1			T1	8		T11	2		T14	5
valid_sources[0x7a]	6824	1			T1	11		T5	1		T11	3
valid_sources[0x7b]	10681	1			T1	17		T12	9		T14	5
valid_sources[0x7c]	6682	1			T1	9		T11	2		T12	2
valid_sources[0x7d]	10250	1			T1	18		T5	2		T11	4
valid_sources[0x7e]	12148	1			T1	2		T5	4		T11	1
valid_sources[0x7f]	10685	1			T1	7		T5	2		T11	1
valid_sources[0x80]	6727	1			T1	6		T5	4		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1389062

1

T1

966

T2

1

T3

896

values[0x0]

all_enables

biggest_size

142023

1

T1

279

T2

1

T3

265

values[0x1]

all_enables

biggest_size

140836

1

T1

314

T3

286

T5

67