Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98436772	15197	0	0
claim_transition_if_regwen_rd_A	98436772	967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98436772	15197	0	0
T33	954	0	0	0
T40	31294	0	0	0
T42	104705	5	0	0
T43	268663	0	0	0
T44	0	2	0	0
T57	0	3	0	0
T58	0	5	0	0
T91	239503	0	0	0
T92	0	13	0	0
T93	0	2	0	0
T112	0	5	0	0
T149	0	12	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	40517	0	0	0
T153	108786	0	0	0
T154	24137	0	0	0
T155	8519	0	0	0
T156	16256	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98436772	967	0	0
T94	0	1	0	0
T117	0	6	0	0
T123	0	7	0	0
T151	119471	1	0	0
T157	0	7	0	0
T158	0	250	0	0
T159	0	7	0	0
T160	0	24	0	0
T161	0	18	0	0
T162	0	25	0	0
T163	339716	0	0	0
T164	38298	0	0	0
T165	33882	0	0	0
T166	1849	0	0	0
T167	39693	0	0	0
T168	30872	0	0	0
T169	40160	0	0	0
T170	41470	0	0	0
T171	820	0	0	0