Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1312499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1535756

1

T1

1360

T2

66

T3

99

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2498609	1			T1	1605		T2	76		T3	86
values[0x0]	174624	1			T1	342		T2	19		T3	29
values[0x1]	175022	1			T1	330		T2	16		T3	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1040802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1807453

1

T1

1566

T2

75

T3

109

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8018	1			T1	14		T2	1		T11	8
valid_sources[0x01]	8163	1			T1	7		T11	10		T15	10
valid_sources[0x02]	8481	1			T1	14		T2	2		T11	8
valid_sources[0x03]	8393	1			T1	7		T11	10		T13	1
valid_sources[0x04]	7854	1			T1	9		T2	1		T11	4
valid_sources[0x05]	8280	1			T1	7		T2	1		T11	6
valid_sources[0x06]	9956	1			T1	5		T2	2		T11	4
valid_sources[0x07]	8149	1			T1	11		T2	3		T11	5
valid_sources[0x08]	8332	1			T1	1		T2	1		T11	3
valid_sources[0x09]	7952	1			T1	10		T11	6		T14	7
valid_sources[0x0a]	8156	1			T1	7		T11	14		T15	2
valid_sources[0x0b]	7942	1			T1	18		T11	5		T13	1
valid_sources[0x0c]	8191	1			T1	8		T11	6		T14	3
valid_sources[0x0d]	9596	1			T1	4		T2	1		T11	2
valid_sources[0x0e]	8912	1			T1	12		T11	12		T15	9
valid_sources[0x0f]	8185	1			T1	1		T2	1		T11	2
valid_sources[0x10]	11299	1			T1	8		T2	1		T11	4
valid_sources[0x11]	8516	1			T1	7		T11	6		T15	7
valid_sources[0x12]	8239	1			T1	4		T11	11		T13	1
valid_sources[0x13]	8428	1			T1	22		T11	7		T14	4
valid_sources[0x14]	10944	1			T1	5		T11	7		T15	1
valid_sources[0x15]	8019	1			T1	14		T11	6		T15	1
valid_sources[0x16]	36483	1			T1	10		T2	1		T11	6
valid_sources[0x17]	27990	1			T1	9		T11	4		T15	12
valid_sources[0x18]	8142	1			T1	7		T2	1		T11	5
valid_sources[0x19]	10598	1			T1	7		T11	10		T15	7
valid_sources[0x1a]	41892	1			T1	8		T11	8		T13	2
valid_sources[0x1b]	8147	1			T1	12		T2	1		T11	9
valid_sources[0x1c]	8135	1			T1	13		T11	8		T14	2
valid_sources[0x1d]	8557	1			T1	21		T2	1		T11	2
valid_sources[0x1e]	8158	1			T1	8		T11	4		T15	3
valid_sources[0x1f]	7952	1			T1	4		T11	5		T15	9
valid_sources[0x20]	8013	1			T1	8		T11	2		T13	2
valid_sources[0x21]	9705	1			T1	18		T11	8		T15	9
valid_sources[0x22]	8313	1			T1	7		T2	1		T11	5
valid_sources[0x23]	8403	1			T1	5		T2	1		T11	8
valid_sources[0x24]	7812	1			T1	11		T11	8		T14	1
valid_sources[0x25]	8570	1			T1	14		T11	8		T13	1
valid_sources[0x26]	14148	1			T1	5		T11	7		T15	2
valid_sources[0x27]	7915	1			T1	16		T2	2		T11	8
valid_sources[0x28]	9353	1			T1	3		T2	1		T11	6
valid_sources[0x29]	8118	1			T1	5		T11	12		T14	3
valid_sources[0x2a]	8567	1			T1	12		T2	1		T11	4
valid_sources[0x2b]	10024	1			T1	13		T11	9		T15	7
valid_sources[0x2c]	10882	1			T1	10		T2	1		T11	7
valid_sources[0x2d]	10371	1			T1	6		T11	6		T14	2
valid_sources[0x2e]	10224	1			T1	6		T2	1		T11	6
valid_sources[0x2f]	8990	1			T1	11		T11	4		T14	4
valid_sources[0x30]	7940	1			T1	12		T11	4		T13	1
valid_sources[0x31]	8343	1			T1	6		T2	1		T11	9
valid_sources[0x32]	15262	1			T1	6		T11	11		T13	2
valid_sources[0x33]	9865	1			T1	1		T2	1		T11	6
valid_sources[0x34]	8222	1			T1	12		T2	1		T11	8
valid_sources[0x35]	10178	1			T1	7		T11	7		T15	2
valid_sources[0x36]	8286	1			T1	8		T11	12		T15	1
valid_sources[0x37]	9487	1			T1	11		T11	4		T14	6
valid_sources[0x38]	24671	1			T1	6		T3	158		T11	2
valid_sources[0x39]	9250	1			T1	11		T11	5		T14	1
valid_sources[0x3a]	10045	1			T1	10		T11	5		T15	3
valid_sources[0x3b]	12220	1			T1	13		T2	1		T11	10
valid_sources[0x3c]	7985	1			T1	15		T11	6		T15	4
valid_sources[0x3d]	9914	1			T1	31		T11	6		T13	1
valid_sources[0x3e]	8118	1			T1	14		T11	6		T13	2
valid_sources[0x3f]	25826	1			T1	17		T2	1		T11	5
valid_sources[0x40]	8015	1			T1	10		T11	4		T15	8
valid_sources[0x41]	8008	1			T1	7		T11	6		T15	5
valid_sources[0x42]	8400	1			T1	14		T11	10		T15	4
valid_sources[0x43]	8527	1			T1	4		T2	1		T11	5
valid_sources[0x44]	7878	1			T1	4		T2	2		T11	5
valid_sources[0x45]	8228	1			T1	9		T2	1		T11	11
valid_sources[0x46]	9156	1			T1	4		T2	1		T11	4
valid_sources[0x47]	7791	1			T1	12		T11	2		T14	3
valid_sources[0x48]	9417	1			T1	13		T11	6		T13	2
valid_sources[0x49]	10808	1			T1	10		T11	6		T12	2604
valid_sources[0x4a]	8357	1			T1	2		T11	6		T15	2
valid_sources[0x4b]	9401	1			T1	12		T2	2		T11	8
valid_sources[0x4c]	11767	1			T1	12		T2	3		T11	7
valid_sources[0x4d]	8175	1			T1	4		T2	1		T11	7
valid_sources[0x4e]	8064	1			T1	12		T11	11		T13	1
valid_sources[0x4f]	8901	1			T1	13		T11	3		T15	8
valid_sources[0x50]	8044	1			T1	7		T11	3		T15	4
valid_sources[0x51]	10184	1			T1	9		T2	1		T11	6
valid_sources[0x52]	8190	1			T1	14		T11	4		T15	1
valid_sources[0x53]	7942	1			T1	3		T11	11		T13	2
valid_sources[0x54]	107948	1			T1	16		T11	9		T13	2
valid_sources[0x55]	8707	1			T1	9		T2	1		T11	5
valid_sources[0x56]	8798	1			T1	5		T2	1		T11	6
valid_sources[0x57]	8431	1			T1	11		T11	9		T13	2
valid_sources[0x58]	8205	1			T1	17		T11	9		T15	2
valid_sources[0x59]	9308	1			T11	4		T15	16		T51	3
valid_sources[0x5a]	8993	1			T1	3		T11	8		T14	2
valid_sources[0x5b]	8261	1			T1	10		T2	1		T11	6
valid_sources[0x5c]	8267	1			T1	11		T11	6		T13	1
valid_sources[0x5d]	9228	1			T1	6		T2	1		T11	5
valid_sources[0x5e]	7968	1			T1	7		T11	3		T13	2
valid_sources[0x5f]	8230	1			T1	3		T11	7		T15	6
valid_sources[0x60]	9747	1			T1	3		T11	6		T15	3
valid_sources[0x61]	8373	1			T1	8		T11	8		T13	2
valid_sources[0x62]	9367	1			T1	8		T11	8		T15	7
valid_sources[0x63]	7789	1			T1	10		T2	2		T11	8
valid_sources[0x64]	7782	1			T1	5		T11	4		T13	1
valid_sources[0x65]	9543	1			T1	20		T2	2		T11	4
valid_sources[0x66]	10660	1			T1	9		T11	15		T13	1
valid_sources[0x67]	8119	1			T1	9		T11	2		T15	4
valid_sources[0x68]	8023	1			T1	4		T11	3		T13	1
valid_sources[0x69]	10382	1			T1	6		T11	6		T13	1
valid_sources[0x6a]	7962	1			T1	11		T2	1		T11	7
valid_sources[0x6b]	8401	1			T1	9		T11	9		T14	1
valid_sources[0x6c]	11606	1			T1	6		T11	8		T14	6
valid_sources[0x6d]	8103	1			T1	10		T2	2		T11	4
valid_sources[0x6e]	10588	1			T1	8		T2	1		T11	3
valid_sources[0x6f]	15334	1			T1	10		T11	10		T13	2
valid_sources[0x70]	8062	1			T1	9		T11	6		T14	4
valid_sources[0x71]	8079	1			T1	7		T11	14		T16	11
valid_sources[0x72]	10009	1			T1	6		T11	4		T15	6
valid_sources[0x73]	8191	1			T1	3		T2	1		T11	8
valid_sources[0x74]	7812	1			T1	2		T2	3		T11	7
valid_sources[0x75]	10751	1			T1	10		T11	7		T14	3
valid_sources[0x76]	7864	1			T1	7		T11	3		T13	4
valid_sources[0x77]	8015	1			T1	8		T11	3		T14	1
valid_sources[0x78]	8207	1			T1	10		T11	4		T14	4
valid_sources[0x79]	7983	1			T1	10		T11	5		T13	2
valid_sources[0x7a]	8075	1			T1	14		T11	9		T13	2
valid_sources[0x7b]	8662	1			T1	11		T11	6		T15	3
valid_sources[0x7c]	14243	1			T1	6		T11	5		T14	1
valid_sources[0x7d]	10331	1			T1	3		T11	5		T14	3
valid_sources[0x7e]	7854	1			T1	14		T11	3		T15	4
valid_sources[0x7f]	12174	1			T1	3		T11	6		T15	5
valid_sources[0x80]	9634	1			T1	5		T11	7		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1234579

1

T1

777

T2

37

T3

38

values[0x0]

all_enables

biggest_size

151060

1

T1

299

T2

17

T3

27

values[0x1]

all_enables

biggest_size

150117

1

T1

284

T2

12

T3

34