Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	116429096	14492	0	0
claim_transition_if_regwen_rd_A	116429096	1863	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116429096	14492	0	0
T4	671479	13	0	0
T5	225070	0	0	0
T6	160999	0	0	0
T19	8151	0	0	0
T20	191352	6	0	0
T25	56525	0	0	0
T26	34860	0	0	0
T27	22579	0	0	0
T28	26876	0	0	0
T29	19540	0	0	0
T45	0	2	0	0
T57	0	1	0	0
T87	0	3	0	0
T88	0	5	0	0
T111	0	8	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	5	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116429096	1863	0	0
T57	177082	8	0	0
T58	0	6	0	0
T87	0	4	0	0
T88	0	5	0	0
T148	0	26	0	0
T149	0	11	0	0
T150	0	1	0	0
T151	0	8	0	0
T152	0	8	0	0
T153	0	4	0	0
T154	23042	0	0	0
T155	1165	0	0	0
T156	3169	0	0	0
T157	1287	0	0	0
T158	5803	0	0	0
T159	6322	0	0	0
T160	25635	0	0	0
T161	1172	0	0	0
T162	38456	0	0	0