Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1267009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1474457

1

T1

1474

T2

669

T3

1015

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2413608	1			T1	1851		T2	599		T3	1028
values[0x0]	163506	1			T1	297		T2	213		T3	316
values[0x1]	164352	1			T1	351		T2	219		T3	300

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1004427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1737039

1

T1

1692

T2

750

T3

1166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9192	1			T3	5		T15	6		T16	9
valid_sources[0x01]	8209	1			T3	8		T15	4		T16	1
valid_sources[0x02]	8414	1			T1	30		T3	15		T15	3
valid_sources[0x03]	8465	1			T3	4		T15	10		T16	13
valid_sources[0x04]	8377	1			T3	8		T15	7		T16	5
valid_sources[0x05]	8504	1			T3	7		T15	6		T16	9
valid_sources[0x06]	8488	1			T1	162		T3	11		T15	3
valid_sources[0x07]	8348	1			T3	2		T15	5		T16	12
valid_sources[0x08]	8228	1			T3	1		T15	5		T16	9
valid_sources[0x09]	22190	1			T1	10		T3	9		T15	4
valid_sources[0x0a]	8914	1			T1	2		T3	9		T15	9
valid_sources[0x0b]	8331	1			T3	10		T15	4		T16	10
valid_sources[0x0c]	8629	1			T3	6		T15	6		T16	9
valid_sources[0x0d]	42131	1			T1	68		T3	16		T12	13
valid_sources[0x0e]	8919	1			T1	7		T3	8		T15	5
valid_sources[0x0f]	8612	1			T1	68		T3	6		T15	5
valid_sources[0x10]	29665	1			T1	1		T3	8		T15	8
valid_sources[0x11]	8499	1			T3	4		T15	6		T16	7
valid_sources[0x12]	8576	1			T1	32		T3	18		T15	5
valid_sources[0x13]	8558	1			T3	7		T15	3		T16	3
valid_sources[0x14]	8618	1			T3	6		T15	4		T16	6
valid_sources[0x15]	10904	1			T3	4		T15	4		T16	6
valid_sources[0x16]	8538	1			T3	3		T15	6		T16	8
valid_sources[0x17]	8671	1			T3	9		T15	4		T16	17
valid_sources[0x18]	8618	1			T3	4		T15	5		T16	13
valid_sources[0x19]	8444	1			T15	3		T16	3		T40	13
valid_sources[0x1a]	8377	1			T3	6		T15	3		T16	8
valid_sources[0x1b]	9380	1			T1	16		T3	13		T15	8
valid_sources[0x1c]	8412	1			T3	4		T15	10		T16	5
valid_sources[0x1d]	7865	1			T3	3		T15	7		T16	5
valid_sources[0x1e]	8517	1			T1	20		T3	10		T15	8
valid_sources[0x1f]	8189	1			T1	20		T3	4		T15	2
valid_sources[0x20]	9290	1			T3	5		T15	7		T16	10
valid_sources[0x21]	8757	1			T3	2		T15	9		T16	21
valid_sources[0x22]	8356	1			T15	4		T16	7		T42	7
valid_sources[0x23]	10317	1			T3	9		T15	1		T16	12
valid_sources[0x24]	8524	1			T3	9		T15	2		T16	7
valid_sources[0x25]	8248	1			T1	13		T3	11		T15	7
valid_sources[0x26]	8477	1			T3	3		T15	7		T16	10
valid_sources[0x27]	8465	1			T1	62		T3	10		T15	6
valid_sources[0x28]	8133	1			T15	9		T16	7		T42	6
valid_sources[0x29]	8484	1			T3	2		T15	6		T16	8
valid_sources[0x2a]	8096	1			T1	37		T3	6		T15	3
valid_sources[0x2b]	8432	1			T15	6		T16	15		T42	2
valid_sources[0x2c]	8033	1			T15	2		T16	16		T42	1
valid_sources[0x2d]	10115	1			T3	4		T15	3		T16	5
valid_sources[0x2e]	34092	1			T3	11		T15	12		T16	2
valid_sources[0x2f]	8127	1			T15	6		T16	7		T42	15
valid_sources[0x30]	8527	1			T3	3		T15	5		T16	5
valid_sources[0x31]	8491	1			T1	7		T3	1		T15	5
valid_sources[0x32]	8143	1			T3	7		T15	11		T16	12
valid_sources[0x33]	12651	1			T3	8		T13	2783		T15	2
valid_sources[0x34]	8797	1			T3	4		T15	3		T16	4
valid_sources[0x35]	8396	1			T3	6		T15	6		T16	8
valid_sources[0x36]	11454	1			T3	3		T15	2		T16	15
valid_sources[0x37]	8361	1			T3	6		T15	8		T16	12
valid_sources[0x38]	8328	1			T3	2		T15	3		T16	4
valid_sources[0x39]	8745	1			T15	4		T16	7		T40	40
valid_sources[0x3a]	8795	1			T3	4		T15	8		T16	8
valid_sources[0x3b]	9646	1			T3	6		T15	10		T16	14
valid_sources[0x3c]	8050	1			T3	16		T15	3		T16	4
valid_sources[0x3d]	8729	1			T1	63		T15	6		T16	6
valid_sources[0x3e]	8162	1			T1	36		T3	6		T15	8
valid_sources[0x3f]	11382	1			T3	12		T15	6		T16	10
valid_sources[0x40]	9855	1			T3	3		T15	4		T16	5
valid_sources[0x41]	9441	1			T3	4		T15	10		T16	5
valid_sources[0x42]	8398	1			T12	1		T15	5		T16	12
valid_sources[0x43]	8135	1			T3	2		T15	7		T16	7
valid_sources[0x44]	8262	1			T3	12		T15	3		T16	9
valid_sources[0x45]	8327	1			T1	49		T3	6		T15	3
valid_sources[0x46]	10519	1			T3	7		T15	8		T16	5
valid_sources[0x47]	35314	1			T3	5		T15	7		T16	4
valid_sources[0x48]	13337	1			T1	16		T3	9		T15	3
valid_sources[0x49]	9822	1			T3	6		T12	4		T15	7
valid_sources[0x4a]	10267	1			T3	4		T15	4		T16	6
valid_sources[0x4b]	8304	1			T3	3		T12	43		T15	4
valid_sources[0x4c]	10574	1			T3	6		T15	3		T16	7
valid_sources[0x4d]	22265	1			T1	20		T3	3		T15	4
valid_sources[0x4e]	8559	1			T3	8		T15	3		T16	8
valid_sources[0x4f]	8411	1			T3	9		T15	3		T16	8
valid_sources[0x50]	8408	1			T3	7		T15	7		T16	11
valid_sources[0x51]	8849	1			T1	43		T3	2		T15	2
valid_sources[0x52]	9735	1			T1	34		T3	3		T12	15
valid_sources[0x53]	12113	1			T3	3		T15	7		T16	3
valid_sources[0x54]	8598	1			T1	22		T3	20		T15	8
valid_sources[0x55]	9956	1			T1	35		T3	3		T15	6
valid_sources[0x56]	8775	1			T3	11		T15	10		T16	6
valid_sources[0x57]	10997	1			T1	51		T3	3		T14	765
valid_sources[0x58]	8254	1			T3	4		T15	4		T16	16
valid_sources[0x59]	32806	1			T3	3		T16	10		T40	8
valid_sources[0x5a]	8466	1			T3	18		T15	6		T16	21
valid_sources[0x5b]	8481	1			T1	17		T3	15		T15	4
valid_sources[0x5c]	8258	1			T3	22		T15	7		T16	4
valid_sources[0x5d]	8341	1			T3	4		T15	6		T16	6
valid_sources[0x5e]	8884	1			T3	16		T15	6		T16	7
valid_sources[0x5f]	16871	1			T3	1		T15	3		T16	5
valid_sources[0x60]	9555	1			T3	9		T15	5		T16	8
valid_sources[0x61]	9916	1			T3	9		T15	5		T16	8
valid_sources[0x62]	9851	1			T3	2		T15	6		T16	8
valid_sources[0x63]	13919	1			T15	5		T16	12		T40	2
valid_sources[0x64]	10611	1			T3	2		T15	11		T16	9
valid_sources[0x65]	12093	1			T1	40		T3	4		T15	5
valid_sources[0x66]	9186	1			T3	5		T15	3		T16	13
valid_sources[0x67]	8777	1			T3	10		T15	4		T16	8
valid_sources[0x68]	8303	1			T1	22		T3	1		T15	6
valid_sources[0x69]	8171	1			T3	1		T15	3		T16	6
valid_sources[0x6a]	11323	1			T3	11		T15	9		T16	11
valid_sources[0x6b]	8511	1			T3	7		T15	5		T16	16
valid_sources[0x6c]	9526	1			T3	2		T15	5		T16	14
valid_sources[0x6d]	8828	1			T1	25		T3	1		T15	6
valid_sources[0x6e]	8467	1			T1	2		T3	4		T15	6
valid_sources[0x6f]	19346	1			T3	2		T15	5		T16	11
valid_sources[0x70]	8522	1			T1	19		T3	8		T15	3
valid_sources[0x71]	12778	1			T3	9		T15	5		T16	12
valid_sources[0x72]	8223	1			T1	8		T3	4		T15	4
valid_sources[0x73]	8451	1			T1	69		T3	7		T15	5
valid_sources[0x74]	9973	1			T3	13		T15	7		T16	13
valid_sources[0x75]	8644	1			T3	3		T15	7		T16	14
valid_sources[0x76]	8078	1			T1	9		T3	4		T15	6
valid_sources[0x77]	9065	1			T3	4		T15	4		T16	3
valid_sources[0x78]	8304	1			T3	14		T15	4		T16	4
valid_sources[0x79]	8657	1			T3	12		T15	3		T16	2
valid_sources[0x7a]	9451	1			T1	123		T3	1		T15	5
valid_sources[0x7b]	8664	1			T3	10		T15	6		T16	23
valid_sources[0x7c]	8169	1			T3	6		T15	10		T16	6
valid_sources[0x7d]	17951	1			T1	22		T3	6		T15	4
valid_sources[0x7e]	8562	1			T3	1		T15	3		T16	5
valid_sources[0x7f]	8615	1			T1	83		T3	19		T15	5
valid_sources[0x80]	12952	1			T3	3		T15	6		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1191903

1

T1

919

T2

303

T3

474

values[0x0]

all_enables

biggest_size

141740

1

T1

251

T2

177

T3

284

values[0x1]

all_enables

biggest_size

140814

1

T1

304

T2

189

T3

257