Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95757074	14391	0	0
claim_transition_if_regwen_rd_A	95757074	1192	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95757074	14391	0	0
T46	21890	0	0	0
T49	141609	0	0	0
T62	341777	10	0	0
T73	0	2	0	0
T82	0	1	0	0
T94	142120	0	0	0
T109	0	6	0	0
T111	0	8	0	0
T147	0	3	0	0
T150	0	4	0	0
T151	0	2	0	0
T152	0	9	0	0
T153	0	2	0	0
T154	18590	0	0	0
T155	31303	0	0	0
T156	44274	0	0	0
T157	21304	0	0	0
T158	4377	0	0	0
T159	52163	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95757074	1192	0	0
T52	0	6	0	0
T73	0	11	0	0
T78	0	3	0	0
T93	156994	3	0	0
T96	0	9	0	0
T120	0	15	0	0
T147	0	13	0	0
T150	0	19	0	0
T160	0	2	0	0
T161	0	11	0	0
T162	262575	0	0	0
T163	32962	0	0	0
T164	101891	0	0	0
T165	19499	0	0	0
T166	1255	0	0	0
T167	33078	0	0	0
T168	1579	0	0	0
T169	26809	0	0	0
T170	1639	0	0	0