Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1326090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1538245

1

T1

130

T2

168

T3

1563

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2533004	1			T1	162		T2	146		T3	2019
values[0x0]	165994	1			T1	41		T2	70		T3	348
values[0x1]	165337	1			T1	20		T2	52		T3	340

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1052229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1812106

1

T1

158

T2

181

T3

1815

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23415	1			T3	5		T13	16		T14	2
valid_sources[0x01]	8704	1			T3	16		T13	1		T15	6
valid_sources[0x02]	8872	1			T3	12		T13	10		T14	1
valid_sources[0x03]	10959	1			T3	11		T13	9		T15	7
valid_sources[0x04]	8643	1			T3	23		T14	1		T15	3
valid_sources[0x05]	8331	1			T2	1		T3	9		T13	19
valid_sources[0x06]	8395	1			T3	12		T13	8		T15	4
valid_sources[0x07]	10906	1			T3	14		T13	1		T14	2
valid_sources[0x08]	8475	1			T3	9		T15	10		T22	8
valid_sources[0x09]	8462	1			T3	14		T15	6		T22	2
valid_sources[0x0a]	8742	1			T2	19		T3	11		T13	5
valid_sources[0x0b]	8949	1			T3	11		T13	3		T14	2
valid_sources[0x0c]	9039	1			T3	13		T13	3		T15	7
valid_sources[0x0d]	11001	1			T3	11		T13	14		T15	10
valid_sources[0x0e]	8816	1			T3	19		T13	7		T14	3
valid_sources[0x0f]	11311	1			T3	18		T13	18		T15	3
valid_sources[0x10]	10973	1			T2	14		T3	7		T13	6
valid_sources[0x11]	8899	1			T3	13		T13	9		T14	5
valid_sources[0x12]	13044	1			T3	24		T13	17		T15	11
valid_sources[0x13]	8845	1			T3	14		T11	5		T13	1
valid_sources[0x14]	8813	1			T3	16		T13	3		T14	1
valid_sources[0x15]	10306	1			T2	8		T3	7		T15	2
valid_sources[0x16]	9987	1			T3	11		T13	4		T15	11
valid_sources[0x17]	8927	1			T3	16		T13	5		T14	3
valid_sources[0x18]	9666	1			T3	12		T15	5		T5	257
valid_sources[0x19]	8685	1			T2	3		T3	17		T10	3
valid_sources[0x1a]	8641	1			T3	23		T13	1		T15	4
valid_sources[0x1b]	8962	1			T3	8		T13	15		T15	5
valid_sources[0x1c]	10066	1			T2	10		T3	12		T15	8
valid_sources[0x1d]	8569	1			T3	12		T11	2		T13	2
valid_sources[0x1e]	8355	1			T3	21		T13	15		T15	9
valid_sources[0x1f]	8884	1			T3	10		T13	13		T15	5
valid_sources[0x20]	8703	1			T3	22		T13	3		T14	1
valid_sources[0x21]	8523	1			T3	13		T13	6		T15	8
valid_sources[0x22]	8843	1			T3	15		T13	7		T14	1
valid_sources[0x23]	8787	1			T3	8		T13	10		T14	3
valid_sources[0x24]	8474	1			T3	5		T13	11		T14	1
valid_sources[0x25]	8970	1			T13	3		T15	5		T5	317
valid_sources[0x26]	8663	1			T3	8		T13	6		T14	4
valid_sources[0x27]	8624	1			T2	3		T3	12		T13	16
valid_sources[0x28]	9309	1			T3	16		T14	1		T15	3
valid_sources[0x29]	8656	1			T2	2		T3	20		T14	3
valid_sources[0x2a]	8747	1			T3	9		T11	1		T13	2
valid_sources[0x2b]	14477	1			T3	6		T10	2		T13	17
valid_sources[0x2c]	8571	1			T3	9		T13	4		T14	1
valid_sources[0x2d]	9754	1			T3	12		T13	1		T15	3
valid_sources[0x2e]	9968	1			T3	15		T13	2		T15	14
valid_sources[0x2f]	8442	1			T3	7		T11	2		T13	1
valid_sources[0x30]	8464	1			T3	4		T13	3		T15	8
valid_sources[0x31]	11320	1			T3	6		T15	6		T22	1
valid_sources[0x32]	8698	1			T3	16		T13	18		T15	8
valid_sources[0x33]	9767	1			T3	6		T13	2		T14	3
valid_sources[0x34]	8435	1			T2	7		T3	7		T10	2
valid_sources[0x35]	10543	1			T3	18		T13	8		T14	1
valid_sources[0x36]	8688	1			T3	8		T13	7		T15	7
valid_sources[0x37]	8697	1			T3	5		T13	3		T14	5
valid_sources[0x38]	9952	1			T3	9		T11	1		T13	5
valid_sources[0x39]	9095	1			T3	7		T11	1		T15	11
valid_sources[0x3a]	8443	1			T3	14		T11	1		T13	2
valid_sources[0x3b]	12163	1			T3	14		T13	6		T15	5
valid_sources[0x3c]	16089	1			T3	26		T13	13		T14	1
valid_sources[0x3d]	10603	1			T3	7		T13	6		T15	11
valid_sources[0x3e]	9578	1			T3	11		T10	1		T13	5
valid_sources[0x3f]	10646	1			T3	4		T14	2		T15	3
valid_sources[0x40]	9854	1			T3	1		T13	3		T14	1
valid_sources[0x41]	8654	1			T3	6		T13	12		T14	4
valid_sources[0x42]	8546	1			T3	10		T13	7		T14	1
valid_sources[0x43]	8639	1			T3	8		T15	5		T5	305
valid_sources[0x44]	11878	1			T3	14		T13	1		T15	5
valid_sources[0x45]	8569	1			T3	9		T14	1		T15	8
valid_sources[0x46]	8762	1			T3	21		T13	2		T15	6
valid_sources[0x47]	8456	1			T3	12		T13	3		T15	7
valid_sources[0x48]	8525	1			T3	5		T13	5		T15	9
valid_sources[0x49]	8524	1			T3	1		T13	13		T14	2
valid_sources[0x4a]	8981	1			T3	9		T13	6		T14	4
valid_sources[0x4b]	8361	1			T3	3		T13	8		T15	6
valid_sources[0x4c]	9014	1			T1	223		T3	9		T10	1
valid_sources[0x4d]	8314	1			T3	7		T11	1		T13	7
valid_sources[0x4e]	8515	1			T3	13		T13	8		T14	1
valid_sources[0x4f]	8687	1			T13	6		T15	9		T22	1
valid_sources[0x50]	8600	1			T3	7		T13	7		T14	3
valid_sources[0x51]	11117	1			T3	10		T14	2		T15	1
valid_sources[0x52]	15956	1			T3	9		T13	10		T14	2
valid_sources[0x53]	9034	1			T3	16		T13	10		T14	1
valid_sources[0x54]	10488	1			T3	22		T13	1		T14	4
valid_sources[0x55]	8530	1			T3	6		T13	20		T15	6
valid_sources[0x56]	8673	1			T3	13		T13	4		T14	2
valid_sources[0x57]	9413	1			T3	5		T10	2		T14	1
valid_sources[0x58]	8663	1			T3	11		T14	5		T15	3
valid_sources[0x59]	9232	1			T3	3		T13	2		T15	6
valid_sources[0x5a]	8668	1			T3	5		T11	5		T13	15
valid_sources[0x5b]	8538	1			T3	4		T13	1		T15	6
valid_sources[0x5c]	8590	1			T3	9		T14	1		T15	2
valid_sources[0x5d]	10795	1			T3	3		T13	1		T14	2
valid_sources[0x5e]	8606	1			T3	7		T13	1		T14	6
valid_sources[0x5f]	54900	1			T3	5		T13	1		T14	2
valid_sources[0x60]	11768	1			T3	8		T13	14		T14	2
valid_sources[0x61]	17474	1			T3	11		T14	1		T15	6
valid_sources[0x62]	8611	1			T3	23		T15	9		T5	276
valid_sources[0x63]	8822	1			T3	10		T14	1		T15	3
valid_sources[0x64]	9732	1			T3	7		T13	8		T14	2
valid_sources[0x65]	8664	1			T2	5		T3	9		T10	1
valid_sources[0x66]	10011	1			T3	12		T11	6		T14	2
valid_sources[0x67]	8731	1			T3	12		T13	3		T14	1
valid_sources[0x68]	9668	1			T3	13		T15	5		T5	304
valid_sources[0x69]	10370	1			T3	13		T13	5		T15	5
valid_sources[0x6a]	10646	1			T3	15		T13	8		T14	2
valid_sources[0x6b]	10122	1			T3	13		T13	2		T15	8
valid_sources[0x6c]	8347	1			T3	11		T13	4		T14	4
valid_sources[0x6d]	12422	1			T3	11		T15	4		T5	247
valid_sources[0x6e]	8271	1			T2	1		T3	10		T10	1
valid_sources[0x6f]	9481	1			T3	5		T13	8		T15	11
valid_sources[0x70]	8548	1			T3	8		T13	6		T14	1
valid_sources[0x71]	71075	1			T3	9		T13	2		T14	1
valid_sources[0x72]	14077	1			T3	16		T14	2		T15	7
valid_sources[0x73]	8820	1			T3	4		T13	4		T14	4
valid_sources[0x74]	102368	1			T3	13		T14	1		T15	7
valid_sources[0x75]	9397	1			T3	5		T13	5		T14	4
valid_sources[0x76]	8823	1			T3	9		T13	4		T14	2
valid_sources[0x77]	9553	1			T3	13		T13	4		T15	6
valid_sources[0x78]	32653	1			T3	2		T13	12		T14	1
valid_sources[0x79]	10250	1			T3	8		T10	1		T13	5
valid_sources[0x7a]	9498	1			T3	10		T13	5		T14	2
valid_sources[0x7b]	8595	1			T3	8		T13	2		T15	4
valid_sources[0x7c]	9837	1			T3	12		T11	10		T13	16
valid_sources[0x7d]	8652	1			T3	9		T13	1		T15	5
valid_sources[0x7e]	8641	1			T3	9		T13	18		T14	3
valid_sources[0x7f]	9323	1			T3	7		T13	6		T14	2
valid_sources[0x80]	8626	1			T3	4		T13	5		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1252469

1

T1

77

T2

70

T3

954

values[0x0]

all_enables

biggest_size

143853

1

T1

37

T2

58

T3

309

values[0x1]

all_enables

biggest_size

141923

1

T1

16

T2

40

T3

300