Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	100886177	13645	0	0
claim_transition_if_regwen_rd_A	100886177	1931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100886177	13645	0	0
T46	282585	0	0	0
T51	42450	0	0	0
T58	242730	3	0	0
T59	0	15	0	0
T61	21033	0	0	0
T63	1626	0	0	0
T64	3021	0	0	0
T83	0	6	0	0
T84	0	2	0	0
T88	0	3	0	0
T97	0	6	0	0
T137	0	7	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	32360	0	0	0
T142	15590	0	0	0
T143	1827	0	0	0
T144	18298	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100886177	1931	0	0
T98	0	9	0	0
T103	0	11	0	0
T108	0	23	0	0
T138	0	3	0	0
T140	0	9	0	0
T145	193104	2	0	0
T146	0	15	0	0
T147	0	10	0	0
T148	0	152	0	0
T149	0	235	0	0
T150	234310	0	0	0
T151	24259	0	0	0
T152	26651	0	0	0
T153	9339	0	0	0
T154	132415	0	0	0
T155	280670	0	0	0
T156	1519	0	0	0
T157	3794	0	0	0
T158	57400	0	0	0