Unified Coverage Report :: Module :: prim_fifo_async_simple

Module Definition

dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_fifo_async_simple

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.12			79.12

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req	63.57			63.57
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp	95.95			95.95

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.57			63.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.24			75.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
74.30			74.30				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	100.00			100.00

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95			95.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86			97.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
74.30			74.30				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	100.00			100.00

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=66,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
63.57	63.57

tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

	Total	Covered	Percent
Totals	10	8	80.00
Total Bits	280	178	63.57
Total Bits 0->1	140	89	63.57
Total Bits 1->0	140	89	63.57


Ports	10	8	80.00
Port Bits	280	178	63.57
Port Bits 0->1	140	89	63.57
Port Bits 1->0	140	89	63.57

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_wr_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rst_wr_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
wvalid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wdata_i[40:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wdata_i[65:41]	No	No		No		INPUT
clk_rd_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_rd_ni	Yes	Yes	T4,T5,T9	Yes	T2,T4,T5	INPUT
rvalid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rready_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rdata_o[39:0]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rdata_o[65:40]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=34,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
95.95	95.95

tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

	Total	Covered	Percent
Totals	9	7	77.78
Total Bits	150	142	94.67
Total Bits 0->1	75	71	94.67
Total Bits 1->0	75	71	94.67


Ports	9	7	77.78
Port Bits	150	142	94.67
Port Bits 0->1	75	71	94.67
Port Bits 1->0	75	71	94.67

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_wr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_wr_ni	Yes	Yes	T4,T5,T9	Yes	T2,T4,T5	INPUT
wvalid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wdata_i[1:0]	No	No		No		INPUT
wdata_i[33:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
clk_rd_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rst_rd_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rvalid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rready_i	Unreachable	Unreachable		Unreachable		INPUT
rdata_o[1:0]	No	No		No		OUTPUT
rdata_o[33:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

	Total	Covered	Percent
Totals	10	8	80.00
Total Bits	280	178	63.57
Total Bits 0->1	140	89	63.57
Total Bits 1->0	140	89	63.57


Ports	10	8	80.00
Port Bits	280	178	63.57
Port Bits 0->1	140	89	63.57
Port Bits 1->0	140	89	63.57

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_wr_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rst_wr_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
wvalid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wdata_i[40:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wdata_i[65:41]	No	No		No		INPUT
clk_rd_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_rd_ni	Yes	Yes	T4,T5,T9	Yes	T2,T4,T5	INPUT
rvalid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rready_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rdata_o[39:0]	Yes	Yes	*T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rdata_o[65:40]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

	Total	Covered	Percent
Totals	9	7	77.78
Total Bits	148	142	95.95
Total Bits 0->1	73	71	97.26
Total Bits 1->0	75	71	94.67


Ports	9	7	77.78
Port Bits	148	142	95.95
Port Bits 0->1	73	71	97.26
Port Bits 1->0	75	71	94.67

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_wr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_wr_ni	Yes	Yes	T4,T5,T9	Yes	T2,T4,T5	INPUT
wvalid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
wready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wdata_i[1:0]	No	No		No		INPUT
wdata_i[33:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
clk_rd_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rst_rd_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rvalid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rready_i	Unreachable	Unreachable		Unreachable		INPUT
rdata_o[1:0]	No	No		Excluded		OUTPUT	0->1:VC_COV_UNR
rdata_o[33:2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%