Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1449293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1669718

1

T1

432

T2

442

T3

198

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2773003	1			T1	403		T2	346		T3	199
values[0x0]	172244	1			T1	164		T2	173		T3	97
values[0x1]	173764	1			T1	172		T2	171		T3	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1968439

1

T1

511

T2

516

T3

225

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7469	1			T1	3		T3	2		T8	6
valid_sources[0x01]	10812	1			T1	3		T5	2		T6	10
valid_sources[0x02]	7630	1			T1	2		T3	1		T5	1
valid_sources[0x03]	9306	1			T1	5		T5	4		T8	3
valid_sources[0x04]	8326	1			T1	3		T8	1		T11	11
valid_sources[0x05]	82325	1			T1	3		T3	1		T11	16
valid_sources[0x06]	9031	1			T1	4		T3	2		T5	1
valid_sources[0x07]	7790	1			T1	4		T3	3		T5	2
valid_sources[0x08]	11888	1			T1	4		T8	3		T11	6
valid_sources[0x09]	7946	1			T1	3		T3	1		T8	5
valid_sources[0x0a]	8295	1			T1	3		T3	1		T5	4
valid_sources[0x0b]	8094	1			T1	6		T3	2		T6	1
valid_sources[0x0c]	7825	1			T1	6		T6	12		T8	1
valid_sources[0x0d]	8063	1			T1	3		T3	4		T5	5
valid_sources[0x0e]	8167	1			T1	1		T3	3		T8	6
valid_sources[0x0f]	8423	1			T1	4		T3	2		T8	2
valid_sources[0x10]	7593	1			T1	7		T3	2		T5	1
valid_sources[0x11]	7915	1			T1	2		T6	3		T11	6
valid_sources[0x12]	7892	1			T1	3		T11	4		T16	7
valid_sources[0x13]	8111	1			T3	4		T8	2		T11	9
valid_sources[0x14]	7835	1			T1	2		T3	1		T5	5
valid_sources[0x15]	8282	1			T1	2		T3	1		T11	6
valid_sources[0x16]	7788	1			T1	4		T3	1		T8	1
valid_sources[0x17]	7720	1			T1	4		T3	2		T8	2
valid_sources[0x18]	7976	1			T1	3		T3	1		T5	3
valid_sources[0x19]	7904	1			T1	5		T3	2		T8	2
valid_sources[0x1a]	8058	1			T1	3		T11	4		T20	1
valid_sources[0x1b]	10994	1			T1	3		T5	1		T8	1
valid_sources[0x1c]	8337	1			T1	3		T3	2		T5	1
valid_sources[0x1d]	8641	1			T1	3		T3	2		T5	4
valid_sources[0x1e]	8405	1			T1	2		T3	2		T5	6
valid_sources[0x1f]	8058	1			T1	5		T3	3		T8	1
valid_sources[0x20]	11568	1			T1	4		T3	1		T5	6
valid_sources[0x21]	17080	1			T1	2		T3	1		T11	7
valid_sources[0x22]	8467	1			T1	1		T3	2		T5	3
valid_sources[0x23]	122395	1			T1	4		T5	3		T8	1
valid_sources[0x24]	33968	1			T1	4		T11	6		T16	10
valid_sources[0x25]	7882	1			T1	1		T8	13		T11	5
valid_sources[0x26]	8250	1			T1	6		T3	1		T6	4
valid_sources[0x27]	8019	1			T1	1		T3	1		T8	1
valid_sources[0x28]	8197	1			T1	4		T3	2		T8	3
valid_sources[0x29]	8143	1			T1	4		T3	2		T8	2
valid_sources[0x2a]	8070	1			T3	2		T5	1		T8	7
valid_sources[0x2b]	7935	1			T1	2		T3	3		T5	6
valid_sources[0x2c]	8380	1			T1	2		T3	1		T6	12
valid_sources[0x2d]	8076	1			T1	3		T3	5		T11	3
valid_sources[0x2e]	7938	1			T1	2		T3	2		T8	1
valid_sources[0x2f]	7921	1			T1	4		T3	2		T5	1
valid_sources[0x30]	8201	1			T1	4		T3	1		T5	8
valid_sources[0x31]	7839	1			T1	2		T3	2		T8	3
valid_sources[0x32]	9226	1			T1	2		T8	2		T11	8
valid_sources[0x33]	7998	1			T1	4		T3	1		T8	2
valid_sources[0x34]	78102	1			T1	3		T3	1		T11	5
valid_sources[0x35]	7849	1			T1	2		T3	1		T8	1
valid_sources[0x36]	8259	1			T1	2		T11	9		T15	1
valid_sources[0x37]	8015	1			T1	2		T5	6		T8	1
valid_sources[0x38]	8199	1			T1	3		T3	1		T8	1
valid_sources[0x39]	8503	1			T1	4		T3	3		T5	2
valid_sources[0x3a]	9182	1			T1	2		T3	2		T5	4
valid_sources[0x3b]	7813	1			T1	4		T5	2		T8	1
valid_sources[0x3c]	7733	1			T1	2		T3	1		T5	1
valid_sources[0x3d]	7917	1			T1	3		T3	3		T5	3
valid_sources[0x3e]	8029	1			T1	1		T3	2		T5	6
valid_sources[0x3f]	8690	1			T1	8		T3	3		T5	1
valid_sources[0x40]	7788	1			T1	3		T3	1		T5	1
valid_sources[0x41]	7921	1			T1	2		T3	2		T5	3
valid_sources[0x42]	29542	1			T1	8		T3	3		T5	2
valid_sources[0x43]	10359	1			T1	5		T3	3		T8	1
valid_sources[0x44]	8052	1			T1	6		T3	2		T8	3
valid_sources[0x45]	13607	1			T1	6		T3	1		T8	5
valid_sources[0x46]	10142	1			T1	3		T3	3		T5	4
valid_sources[0x47]	7699	1			T1	2		T3	1		T5	5
valid_sources[0x48]	9492	1			T1	2		T5	9		T8	12
valid_sources[0x49]	11137	1			T1	3		T3	2		T8	2
valid_sources[0x4a]	7644	1			T1	2		T3	1		T11	8
valid_sources[0x4b]	8005	1			T1	3		T5	1		T8	2
valid_sources[0x4c]	9949	1			T1	6		T3	1		T5	3
valid_sources[0x4d]	7901	1			T1	2		T3	1		T5	2
valid_sources[0x4e]	9697	1			T1	3		T3	2		T8	1
valid_sources[0x4f]	7796	1			T1	4		T6	7		T8	2
valid_sources[0x50]	9263	1			T1	4		T3	2		T8	3
valid_sources[0x51]	8260	1			T1	5		T3	5		T11	4
valid_sources[0x52]	11038	1			T1	1		T5	1		T8	2
valid_sources[0x53]	7837	1			T1	2		T3	1		T6	2
valid_sources[0x54]	8840	1			T1	2		T3	1		T8	1
valid_sources[0x55]	9270	1			T1	2		T3	1		T8	1
valid_sources[0x56]	8456	1			T3	2		T5	6		T8	6
valid_sources[0x57]	8649	1			T1	2		T3	5		T8	2
valid_sources[0x58]	12739	1			T1	2		T5	1		T8	11
valid_sources[0x59]	7853	1			T1	3		T3	6		T5	32
valid_sources[0x5a]	8331	1			T1	2		T5	5		T6	2
valid_sources[0x5b]	7835	1			T8	1		T11	7		T16	4
valid_sources[0x5c]	10558	1			T1	4		T3	1		T8	4
valid_sources[0x5d]	8169	1			T1	6		T5	1		T8	1
valid_sources[0x5e]	7649	1			T1	5		T3	2		T8	1
valid_sources[0x5f]	9681	1			T1	5		T3	1		T6	2
valid_sources[0x60]	9408	1			T1	2		T3	1		T8	6
valid_sources[0x61]	9692	1			T1	4		T3	1		T5	2
valid_sources[0x62]	7893	1			T1	4		T3	2		T8	3
valid_sources[0x63]	9659	1			T1	4		T3	1		T5	4
valid_sources[0x64]	9693	1			T1	1		T5	5		T8	5
valid_sources[0x65]	8613	1			T1	3		T3	2		T8	2
valid_sources[0x66]	10684	1			T1	3		T5	4		T6	12
valid_sources[0x67]	89787	1			T1	5		T3	1		T8	1
valid_sources[0x68]	7727	1			T1	2		T3	2		T5	3
valid_sources[0x69]	8334	1			T1	1		T3	1		T5	4
valid_sources[0x6a]	8216	1			T1	4		T3	2		T5	5
valid_sources[0x6b]	8106	1			T1	1		T3	1		T5	7
valid_sources[0x6c]	58959	1			T1	2		T3	1		T8	4
valid_sources[0x6d]	8011	1			T1	3		T3	1		T5	3
valid_sources[0x6e]	9338	1			T1	3		T3	2		T5	2
valid_sources[0x6f]	11166	1			T1	3		T2	690		T3	1
valid_sources[0x70]	8269	1			T3	3		T5	3		T6	14
valid_sources[0x71]	22672	1			T1	4		T8	1		T11	7
valid_sources[0x72]	7764	1			T1	3		T3	2		T8	8
valid_sources[0x73]	7710	1			T1	2		T3	1		T7	5
valid_sources[0x74]	7846	1			T1	3		T3	1		T5	1
valid_sources[0x75]	7927	1			T1	3		T6	6		T11	7
valid_sources[0x76]	7258	1			T1	4		T5	2		T11	5
valid_sources[0x77]	7884	1			T1	5		T3	1		T8	2
valid_sources[0x78]	7779	1			T1	3		T11	7		T20	1
valid_sources[0x79]	7823	1			T1	3		T3	3		T8	1
valid_sources[0x7a]	9921	1			T1	2		T3	1		T5	1
valid_sources[0x7b]	10506	1			T1	3		T3	3		T8	4
valid_sources[0x7c]	9701	1			T1	2		T5	3		T11	5
valid_sources[0x7d]	7884	1			T1	5		T8	4		T11	11
valid_sources[0x7e]	8501	1			T1	2		T8	7		T11	4
valid_sources[0x7f]	34889	1			T1	2		T3	1		T4	2041
valid_sources[0x80]	9175	1			T1	3		T3	2		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1372037

1

T1

134

T2

148

T3

93

values[0x0]

all_enables

biggest_size

148944

1

T1

142

T2

152

T3

58

values[0x1]

all_enables

biggest_size

148737

1

T1

156

T2

142

T3

47