Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95074570	15174	0	0
claim_transition_if_regwen_rd_A	95074570	1240	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95074570	15174	0	0
T32	157048	1	0	0
T41	0	2	0	0
T43	293711	0	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	20993	0	0	0
T137	0	2	0	0
T138	0	3	0	0
T139	0	16	0	0
T140	0	14	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	602464	0	0	0
T144	1674	0	0	0
T145	8892	0	0	0
T146	5463	0	0	0
T147	32516	0	0	0
T148	16264	0	0	0
T149	7857	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95074570	1240	0	0
T32	157048	9	0	0
T43	293711	0	0	0
T84	20993	0	0	0
T98	0	29	0	0
T104	0	97	0	0
T107	0	10	0	0
T113	0	2	0	0
T125	0	12	0	0
T131	0	57	0	0
T138	0	3	0	0
T142	0	10	0	0
T143	602464	0	0	0
T144	1674	0	0	0
T145	8892	0	0	0
T146	5463	0	0	0
T147	32516	0	0	0
T148	16264	0	0	0
T149	7857	0	0	0
T150	0	3	0	0