Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253899	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1467157

1

T1

12

T2

107

T9

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2385229	1			T2	92		T9	47		T10	480
values[0x0]	167658	1			T1	19		T2	37		T9	12
values[0x1]	168169	1			T1	30		T2	35		T9	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	994413	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1726643

1

T1

15

T2

122

T9

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8590	1			T10	4		T6	1		T35	2
valid_sources[0x01]	8451	1			T10	1		T6	1		T14	9
valid_sources[0x02]	8380	1			T10	2		T14	16		T37	7
valid_sources[0x03]	8495	1			T2	1		T11	1		T35	2
valid_sources[0x04]	9587	1			T2	2		T14	3		T37	5
valid_sources[0x05]	8590	1			T10	2		T37	5		T16	6
valid_sources[0x06]	10122	1			T2	2		T10	1		T14	2
valid_sources[0x07]	8790	1			T2	2		T10	2		T35	2
valid_sources[0x08]	8440	1			T10	1		T6	6		T35	1
valid_sources[0x09]	9609	1			T10	5		T11	1		T14	16
valid_sources[0x0a]	8824	1			T2	1		T11	1		T37	4
valid_sources[0x0b]	8479	1			T10	9		T19	5		T14	8
valid_sources[0x0c]	8849	1			T2	1		T10	1		T6	5
valid_sources[0x0d]	8334	1			T10	2		T6	3		T14	8
valid_sources[0x0e]	8657	1			T10	4		T14	13		T37	6
valid_sources[0x0f]	8536	1			T2	1		T10	2		T6	6
valid_sources[0x10]	8288	1			T2	3		T10	2		T14	4
valid_sources[0x11]	31273	1			T2	1		T10	1		T11	1
valid_sources[0x12]	9498	1			T2	1		T10	1		T6	3
valid_sources[0x13]	8426	1			T2	1		T10	6		T6	1
valid_sources[0x14]	25781	1			T2	1		T6	10		T19	2
valid_sources[0x15]	8897	1			T10	4		T35	1		T37	4
valid_sources[0x16]	8540	1			T10	3		T6	6		T14	2
valid_sources[0x17]	8701	1			T2	1		T10	2		T6	1
valid_sources[0x18]	8200	1			T2	1		T10	1		T35	3
valid_sources[0x19]	8649	1			T10	3		T37	4		T16	7
valid_sources[0x1a]	12827	1			T10	1		T11	1		T14	2
valid_sources[0x1b]	9322	1			T2	1		T10	3		T35	2
valid_sources[0x1c]	9508	1			T10	2		T14	25		T35	1
valid_sources[0x1d]	10409	1			T10	1		T6	1		T11	1
valid_sources[0x1e]	8450	1			T10	1		T11	1		T14	9
valid_sources[0x1f]	8312	1			T2	2		T10	3		T37	1
valid_sources[0x20]	11306	1			T2	1		T10	1		T19	1
valid_sources[0x21]	8596	1			T2	1		T10	2		T19	1
valid_sources[0x22]	9371	1			T10	2		T11	1		T14	5
valid_sources[0x23]	9857	1			T10	5		T37	5		T16	3
valid_sources[0x24]	7937	1			T10	1		T19	3		T14	13
valid_sources[0x25]	8523	1			T2	5		T10	2		T6	10
valid_sources[0x26]	8349	1			T37	6		T16	15		T36	5
valid_sources[0x27]	8227	1			T2	3		T10	4		T6	2
valid_sources[0x28]	8402	1			T9	79		T10	5		T11	1
valid_sources[0x29]	8645	1			T10	2		T6	6		T11	1
valid_sources[0x2a]	8865	1			T2	1		T10	5		T6	2
valid_sources[0x2b]	8340	1			T2	1		T10	3		T35	2
valid_sources[0x2c]	8374	1			T2	1		T10	2		T6	2
valid_sources[0x2d]	8617	1			T2	2		T6	1		T19	2
valid_sources[0x2e]	9741	1			T6	2		T19	1		T14	1
valid_sources[0x2f]	8407	1			T2	2		T10	2		T35	1
valid_sources[0x30]	9545	1			T10	4		T35	3		T37	5
valid_sources[0x31]	8625	1			T10	1		T6	3		T14	1
valid_sources[0x32]	8406	1			T10	1		T14	2		T35	1
valid_sources[0x33]	8588	1			T10	1		T35	2		T37	4
valid_sources[0x34]	8236	1			T10	4		T14	11		T37	3
valid_sources[0x35]	8317	1			T10	5		T6	5		T14	13
valid_sources[0x36]	8638	1			T2	1		T10	2		T11	3
valid_sources[0x37]	10437	1			T2	1		T10	5		T35	2
valid_sources[0x38]	8830	1			T2	1		T10	2		T6	2
valid_sources[0x39]	8729	1			T10	3		T6	1		T14	2
valid_sources[0x3a]	11374	1			T2	3		T10	5		T37	5
valid_sources[0x3b]	8684	1			T2	1		T6	3		T35	1
valid_sources[0x3c]	8607	1			T2	1		T10	1		T14	14
valid_sources[0x3d]	8401	1			T2	2		T10	3		T14	9
valid_sources[0x3e]	8681	1			T10	1		T6	4		T37	4
valid_sources[0x3f]	8126	1			T2	1		T10	4		T35	2
valid_sources[0x40]	8689	1			T2	1		T10	1		T11	1
valid_sources[0x41]	8951	1			T10	3		T6	2		T37	5
valid_sources[0x42]	8716	1			T10	2		T6	1		T14	8
valid_sources[0x43]	8533	1			T6	1		T37	7		T16	9
valid_sources[0x44]	8850	1			T2	2		T10	6		T14	3
valid_sources[0x45]	8516	1			T2	1		T10	4		T6	3
valid_sources[0x46]	8465	1			T2	1		T10	3		T14	24
valid_sources[0x47]	8715	1			T10	1		T37	9		T16	22
valid_sources[0x48]	8315	1			T10	2		T19	2		T14	8
valid_sources[0x49]	9886	1			T2	1		T10	4		T11	1
valid_sources[0x4a]	8431	1			T10	8		T35	2		T37	4
valid_sources[0x4b]	8780	1			T10	3		T37	3		T16	5
valid_sources[0x4c]	9693	1			T10	3		T14	10		T35	3
valid_sources[0x4d]	8486	1			T10	2		T14	4		T35	2
valid_sources[0x4e]	9111	1			T14	3		T35	3		T37	8
valid_sources[0x4f]	8584	1			T2	3		T10	2		T14	7
valid_sources[0x50]	8729	1			T10	1		T6	7		T37	3
valid_sources[0x51]	9398	1			T10	2		T35	1		T37	8
valid_sources[0x52]	14575	1			T2	1		T10	4		T14	4
valid_sources[0x53]	10186	1			T10	4		T19	2		T27	1
valid_sources[0x54]	8438	1			T2	2		T10	1		T6	10
valid_sources[0x55]	9333	1			T2	1		T10	7		T15	658
valid_sources[0x56]	9306	1			T2	3		T10	2		T6	5
valid_sources[0x57]	8834	1			T10	2		T14	2		T35	1
valid_sources[0x58]	8352	1			T2	1		T37	5		T16	5
valid_sources[0x59]	16192	1			T10	3		T6	15		T14	13
valid_sources[0x5a]	8504	1			T11	2		T14	1		T37	3
valid_sources[0x5b]	102467	1			T10	1		T14	10		T35	1
valid_sources[0x5c]	8381	1			T2	2		T10	2		T6	5
valid_sources[0x5d]	18721	1			T2	1		T14	8		T37	4
valid_sources[0x5e]	8546	1			T2	4		T10	1		T19	2
valid_sources[0x5f]	8373	1			T2	2		T10	1		T11	1
valid_sources[0x60]	8557	1			T10	7		T6	1		T35	3
valid_sources[0x61]	8905	1			T10	2		T37	9		T16	10
valid_sources[0x62]	9984	1			T2	1		T10	1		T6	8
valid_sources[0x63]	8437	1			T10	3		T11	1		T35	1
valid_sources[0x64]	8339	1			T2	2		T10	3		T14	8
valid_sources[0x65]	8305	1			T2	2		T10	3		T14	2
valid_sources[0x66]	8419	1			T10	1		T37	4		T16	9
valid_sources[0x67]	8256	1			T2	2		T10	3		T6	2
valid_sources[0x68]	8458	1			T19	2		T14	1		T37	3
valid_sources[0x69]	9521	1			T2	2		T10	3		T6	5
valid_sources[0x6a]	8700	1			T10	4		T14	3		T35	1
valid_sources[0x6b]	8943	1			T10	3		T19	2		T14	9
valid_sources[0x6c]	8206	1			T2	1		T35	2		T37	9
valid_sources[0x6d]	8524	1			T2	1		T10	3		T11	1
valid_sources[0x6e]	8595	1			T2	1		T10	1		T14	2
valid_sources[0x6f]	8097	1			T10	4		T14	10		T35	1
valid_sources[0x70]	8132	1			T10	1		T6	4		T11	1
valid_sources[0x71]	8696	1			T14	2		T35	1		T37	4
valid_sources[0x72]	8624	1			T10	5		T35	1		T37	6
valid_sources[0x73]	8293	1			T2	1		T10	2		T6	1
valid_sources[0x74]	11264	1			T10	2		T6	2		T14	10
valid_sources[0x75]	8592	1			T10	5		T6	4		T19	4
valid_sources[0x76]	10653	1			T14	4		T37	9		T16	9
valid_sources[0x77]	8601	1			T10	9		T35	1		T37	5
valid_sources[0x78]	8788	1			T2	1		T10	1		T14	7
valid_sources[0x79]	8252	1			T6	1		T37	5		T16	4
valid_sources[0x7a]	8536	1			T2	1		T10	1		T14	3
valid_sources[0x7b]	8313	1			T2	1		T10	5		T14	7
valid_sources[0x7c]	20014	1			T2	1		T10	4		T6	3
valid_sources[0x7d]	8633	1			T10	3		T6	1		T14	5
valid_sources[0x7e]	14641	1			T10	1		T6	4		T35	1
valid_sources[0x7f]	14945	1			T10	2		T6	4		T14	6
valid_sources[0x80]	11617	1			T10	7		T6	1		T29	2860

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1178393

1

T2

45

T9

25

T10

244

values[0x0]

all_enables

biggest_size

145037

1

T1

8

T2

31

T9

9

values[0x1]

all_enables

biggest_size

143727

1

T1

4

T2

31

T9

18