Module Definition
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Module : lc_ctrl_kmac_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_kmac_if 100.00 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_lc_ctrl_kmac_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.37 99.10 100.00 100.00 97.73 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.10 100.00 83.10 99.89 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_flop_2sync 100.00 100.00 100.00
u_prim_sync_reqack_data_in 98.41 98.18 100.00 95.45 100.00
u_state_regs 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : lc_ctrl_kmac_if
Line No.TotalCoveredPercent
TOTAL4141100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN8111100.00
ALWAYS8888100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10711100.00
ALWAYS1592121100.00
ALWAYS20333100.00
ALWAYS20633100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
81 1 1
88 1 1
89 1 1
90 1 1
91 1 1
93 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
102 1 1
103 1 1
104 1 1
107 1 1
159 1 1
160 1 1
161 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
MISSING_ELSE
MISSING_ELSE
179 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
MISSING_ELSE
189 1 1
190 1 1
191 1 1
MISSING_ELSE
196 1 1
203 3 3
206 1 1
207 1 1
209 1 1

Cond Coverage for Module : lc_ctrl_kmac_if
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       95
 EXPRESSION (token_hash_req_i && token_hash_ack_d)
             --------1-------    --------2-------
-1--2-StatusTests
01CoveredT48,T49,T52
10CoveredT3,T4,T13
11CoveredT3,T4,T13 

 LINE       107
 EXPRESSION (token_hash_req_i & ((~token_hash_ack_q)))
             --------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T13
11CoveredT3,T4,T13
FSM Coverage for Module : lc_ctrl_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DoneSt 191 Covered T3,T4,T13
FirstSt 203 Covered T1,T2,T3
SecondSt 173 Covered T3,T4,T13
WaitSt 184 Covered T3,T4,T13


transitionsLine No.CoveredTests
DoneSt->FirstSt 203 Covered T3,T4,T13
FirstSt->SecondSt 173 Covered T3,T4,T13
SecondSt->FirstSt 203 Covered T162
SecondSt->WaitSt 184 Covered T3,T4,T13
WaitSt->DoneSt 191 Covered T3,T4,T13
WaitSt->FirstSt 203 Covered T163,T164,T165


Branch Coverage for Module : lc_ctrl_kmac_if
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 3 3 100.00
CASE 164 9 9 100.00
IF 203 2 2 100.00
IF 206 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	95	if ((token_hash_req_i && token_hash_ack_d))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T13
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	164	case (state_q)
-2-:	168	if (kmac_req)
-3-:	172	if (kmac_data_i.ready)
-4-:	183	if (kmac_data_i.ready)
-5-:	189	if (kmac_data_i.done)

Branches:
-1--2--3--4--5-StatusTests
FirstSt 1 1 - - Covered T3,T4,T13
FirstSt 1 0 - - Covered T3,T4,T17
FirstSt 0 - - - Covered T1,T2,T3
SecondSt - - 1 - Covered T3,T4,T13
SecondSt - - 0 - Covered T3,T4,T17
WaitSt - - - 1 Covered T3,T4,T13
WaitSt - - - 0 Covered T3,T4,T13
DoneSt - - - - Covered T3,T4,T13
default - - - - Covered T37,T16,T17 



	LineNo.	Expression
-1-:	203	if ((!rst_kmac_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	206	if ((!rst_kmac_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : lc_ctrl_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataStable_A 103596998 35187379 0 0
u_state_regs_A 101046872 96921023 0 0


DataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 103596998 35187379 0 0
T3 52346 9972 0 0
T4 125893 99859 0 0
T5 21766 0 0 0
T6 36620 0 0 0
T9 2999 0 0 0
T10 8624 0 0 0
T11 2251 0 0 0
T12 30843 0 0 0
T13 139180 54276 0 0
T14 0 878 0 0
T16 0 1261 0 0
T17 0 346858 0 0
T19 2100 0 0 0
T28 0 42 0 0
T29 0 897 0 0
T36 0 918 0 0
T40 0 9525 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101046872 96921023 0 0
T1 3679 3612 0 0
T2 4434 3669 0 0
T3 52346 51184 0 0
T4 125893 125222 0 0
T5 21766 21417 0 0
T6 36620 36553 0 0
T9 2999 2615 0 0
T10 8624 7329 0 0
T11 2251 2191 0 0
T12 30843 29720 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%