Module Definition
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Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
clk1_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
sel_i No No No INPUT
clk_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT


Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 78366226 78364594 0 0
selKnown1 103597949 103596317 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 78366226 78364594 0 0
T2 10 9 0 0
T3 41979 41977 0 0
T4 130622 130620 0 0
T5 15745 15743 0 0
T6 54292 54290 0 0
T7 0 19646 0 0
T9 6 4 0 0
T10 18 16 0 0
T11 2 0 0 0
T12 38957 38955 0 0
T13 223811 223809 0 0
T14 0 97 0 0
T15 0 15 0 0
T16 0 641319 0 0
T17 0 936062 0 0
T18 0 217867 0 0
T19 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 103597949 103596317 0 0
T1 3679 3678 0 0
T2 4434 4433 0 0
T3 52346 52345 0 0
T4 125893 125892 0 0
T5 21766 21765 0 0
T6 36625 36623 0 0
T7 0 1 0 0
T8 0 4 0 0
T9 2999 2998 0 0
T10 8624 8623 0 0
T11 2252 2250 0 0
T12 30844 30842 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T19 1 0 0 0
T20 0 5 0 0
T21 0 3 0 0
T22 0 1 0 0
T23 0 1 0 0
T24 0 4 0 0
T25 0 4 0 0
T26 0 4 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
clk1_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
sel_i No No No INPUT
clk_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
clk1_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
sel_i No No No INPUT
clk_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 78309040 78308224 0 0
selKnown1 103596998 103596182 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 78309040 78308224 0 0
T3 41963 41962 0 0
T4 130612 130611 0 0
T5 15740 15739 0 0
T6 54291 54290 0 0
T7 0 19646 0 0
T9 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T12 38943 38942 0 0
T13 223774 223773 0 0
T16 0 641319 0 0
T17 0 936062 0 0
T18 0 217867 0 0
T19 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 103596998 103596182 0 0
T1 3679 3678 0 0
T2 4434 4433 0 0
T3 52346 52345 0 0
T4 125893 125892 0 0
T5 21766 21765 0 0
T6 36620 36619 0 0
T9 2999 2998 0 0
T10 8624 8623 0 0
T11 2251 2250 0 0
T12 30843 30842 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 57186 56370 0 0
selKnown1 951 135 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 57186 56370 0 0
T2 10 9 0 0
T3 16 15 0 0
T4 10 9 0 0
T5 5 4 0 0
T6 1 0 0 0
T9 5 4 0 0
T10 17 16 0 0
T11 1 0 0 0
T12 14 13 0 0
T13 37 36 0 0
T14 0 97 0 0
T15 0 15 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 951 135 0 0
T6 5 4 0 0
T7 0 1 0 0
T8 0 4 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T19 1 0 0 0
T20 0 5 0 0
T21 0 3 0 0
T22 0 1 0 0
T23 0 1 0 0
T24 0 4 0 0
T25 0 4 0 0
T26 0 4 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%