Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	94.59	100.00	100.00		83.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack	97.03	97.22	100.00			90.91	100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack	100.00			100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.03	97.22	100.00			90.91	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	97.92	100.00			94.74	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_sync_reqack_data_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
63.57			63.57				i_cdc_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00			100.00
gen_rz_hs_protocol.req_sync	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.95			95.95				i_cdc_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00			100.00
gen_rz_hs_protocol.req_sync	100.00			100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		37	35	94.59
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	11	91.67
ALWAYS	263	12	11	91.67
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	0	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	0	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T52
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T48,T49
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

---

Toggle Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	16	16	100.00
Total Bits 0->1	8	8	100.00
Total Bits 1->0	8	8	100.00

Ports	8	8	100.00
Port Bits	16	16	100.00
Port Bits 0->1	8	8	100.00
Port Bits 1->0	8	8	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_src_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_src_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_dst_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_dst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
req_chk_i	Unreachable	Unreachable		Unreachable		INPUT
src_req_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_ack_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_req_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_ack_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	10	83.33
CASE	225	4	3	75.00
CASE	269	4	3	75.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T3,T4,T13
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Not Covered
ODD	-	0	Covered	T3,T4,T13

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T3,T4,T13
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Not Covered
ODD	-	0	Covered	T3,T4,T13

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	98862377	22893	0	0
SyncReqAckHoldReq	103596998	24163	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	98862377	22893	0	0
T3	52346	15	0	0
T4	125893	9	0	0
T5	21766	0	0	0
T6	36620	0	0	0
T9	2999	0	0	0
T10	8624	0	0	0
T11	2251	0	0	0
T12	30843	0	0	0
T13	139180	30	0	0
T14	0	43	0	0
T16	0	125	0	0
T17	0	97	0	0
T19	2100	0	0	0
T28	0	4	0	0
T29	0	89	0	0
T36	0	92	0	0
T40	0	50	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	103596998	24163	0	0
T3	52346	15	0	0
T4	125893	9	0	0
T5	21766	0	0	0
T6	36620	0	0	0
T9	2999	0	0	0
T10	8624	0	0	0
T11	2251	0	0	0
T12	30843	0	0	0
T13	139180	30	0	0
T14	0	43	0	0
T16	0	125	0	0
T17	0	97	0	0
T19	2100	0	0	0
T28	0	4	0	0
T29	0	89	0	0
T36	0	92	0	0
T40	0	50	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	35	97.22
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	11	11	100.00
ALWAYS	263	12	11	91.67
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	0	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T52
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T48,T49
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		11	10	90.91
CASE	225	3	3	100.00
CASE	269	4	3	75.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
EVEN	1	-	Covered	T3,T4,T13
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Excluded		VC_COV_UNR
ODD	-	0	Covered	T3,T4,T13

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T3,T4,T13
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Not Covered
ODD	-	0	Covered	T3,T4,T13

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	98862377	22893	0	0
SyncReqAckHoldReq	103596998	24163	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	98862377	22893	0	0
T3	52346	15	0	0
T4	125893	9	0	0
T5	21766	0	0	0
T6	36620	0	0	0
T9	2999	0	0	0
T10	8624	0	0	0
T11	2251	0	0	0
T12	30843	0	0	0
T13	139180	30	0	0
T14	0	43	0	0
T16	0	125	0	0
T17	0	97	0	0
T19	2100	0	0	0
T28	0	4	0	0
T29	0	89	0	0
T36	0	92	0	0
T40	0	50	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	103596998	24163	0	0
T3	52346	15	0	0
T4	125893	9	0	0
T5	21766	0	0	0
T6	36620	0	0	0
T9	2999	0	0	0
T10	8624	0	0	0
T11	2251	0	0	0
T12	30843	0	0	0
T13	139180	30	0	0
T14	0	43	0	0
T16	0	125	0	0
T17	0	97	0	0
T19	2100	0	0	0
T28	0	4	0	0
T29	0	89	0	0
T36	0	92	0	0
T40	0	50	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	16	16	100.00
Total Bits 0->1	8	8	100.00
Total Bits 1->0	8	8	100.00

Ports	8	8	100.00
Port Bits	16	16	100.00
Port Bits 0->1	8	8	100.00
Port Bits 1->0	8	8	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_src_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rst_src_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_dst_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_dst_ni	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
req_chk_i	Unreachable	Unreachable		Unreachable		INPUT
src_req_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_ack_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_req_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_ack_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	16	16	100.00
Total Bits 0->1	8	8	100.00
Total Bits 1->0	8	8	100.00

Ports	8	8	100.00
Port Bits	16	16	100.00
Port Bits 0->1	8	8	100.00
Port Bits 1->0	8	8	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_src_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_src_ni	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
clk_dst_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rst_dst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
req_chk_i	Unreachable	Unreachable		Unreachable		INPUT
src_req_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_ack_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_req_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
dst_ack_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT