Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1729409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1952437

1

T1

202

T9

118

T10

1632

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3333407	1			T1	160		T9	113		T10	1905
values[0x0]	174183	1			T1	75		T9	42		T10	389
values[0x1]	174256	1			T1	69		T9	37		T10	395

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1374045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2307801

1

T1

226

T9

135

T10

1866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10873	1			T1	3		T10	18		T11	1
valid_sources[0x01]	10785	1			T1	2		T10	3		T13	4
valid_sources[0x02]	11661	1			T10	2		T11	6		T13	3
valid_sources[0x03]	10924	1			T10	3		T11	3		T13	8
valid_sources[0x04]	74479	1			T10	17		T11	4		T13	3
valid_sources[0x05]	10607	1			T10	3		T11	2		T13	4
valid_sources[0x06]	11819	1			T10	3		T11	2		T13	3
valid_sources[0x07]	11714	1			T1	1		T10	24		T13	5
valid_sources[0x08]	11007	1			T10	19		T11	6		T13	4
valid_sources[0x09]	10579	1			T10	15		T11	4		T13	1
valid_sources[0x0a]	11932	1			T10	14		T11	7		T13	3
valid_sources[0x0b]	11051	1			T10	11		T11	1		T15	25
valid_sources[0x0c]	11049	1			T1	1		T10	15		T11	1
valid_sources[0x0d]	11224	1			T10	7		T11	7		T14	3
valid_sources[0x0e]	10746	1			T10	4		T11	1		T15	6
valid_sources[0x0f]	10609	1			T1	1		T10	1		T11	13
valid_sources[0x10]	14073	1			T10	7		T11	13		T13	1
valid_sources[0x11]	55866	1			T1	1		T10	10		T11	4
valid_sources[0x12]	10763	1			T1	2		T10	11		T11	9
valid_sources[0x13]	10743	1			T1	5		T10	11		T11	3
valid_sources[0x14]	11348	1			T10	14		T11	8		T13	6
valid_sources[0x15]	13063	1			T10	11		T11	4		T13	1
valid_sources[0x16]	12022	1			T1	2		T10	11		T13	1
valid_sources[0x17]	11086	1			T10	15		T11	5		T12	3
valid_sources[0x18]	13141	1			T1	3		T10	16		T11	6
valid_sources[0x19]	11105	1			T10	9		T11	1		T13	3
valid_sources[0x1a]	10785	1			T1	2		T10	11		T11	9
valid_sources[0x1b]	11248	1			T10	8		T11	10		T13	1
valid_sources[0x1c]	10676	1			T10	10		T11	2		T15	4
valid_sources[0x1d]	10814	1			T10	5		T11	9		T13	2
valid_sources[0x1e]	10788	1			T10	11		T11	3		T15	11
valid_sources[0x1f]	11572	1			T1	7		T10	17		T11	1
valid_sources[0x20]	13376	1			T1	2		T10	6		T13	1
valid_sources[0x21]	10715	1			T1	1		T10	14		T11	7
valid_sources[0x22]	11448	1			T9	7		T10	2		T13	2
valid_sources[0x23]	11446	1			T1	2		T10	19		T11	2
valid_sources[0x24]	10791	1			T1	6		T10	14		T11	10
valid_sources[0x25]	11752	1			T1	1		T10	20		T11	1
valid_sources[0x26]	11916	1			T10	7		T11	1		T13	2
valid_sources[0x27]	11982	1			T10	18		T11	2		T13	3
valid_sources[0x28]	11055	1			T10	15		T13	5		T15	8
valid_sources[0x29]	56184	1			T10	8		T11	4		T15	10
valid_sources[0x2a]	10930	1			T1	1		T10	16		T11	3
valid_sources[0x2b]	11422	1			T1	8		T10	8		T13	2
valid_sources[0x2c]	11084	1			T9	22		T10	1		T14	2
valid_sources[0x2d]	11047	1			T10	3		T11	6		T15	6
valid_sources[0x2e]	11567	1			T10	10		T11	1		T13	2
valid_sources[0x2f]	10786	1			T10	11		T11	1		T13	2
valid_sources[0x30]	11071	1			T10	11		T11	10		T13	2
valid_sources[0x31]	34578	1			T10	4		T11	4		T13	4
valid_sources[0x32]	10620	1			T10	16		T11	3		T13	1
valid_sources[0x33]	13305	1			T1	11		T10	3		T11	3
valid_sources[0x34]	10752	1			T10	2		T13	2		T14	2
valid_sources[0x35]	10896	1			T10	4		T11	21		T13	6
valid_sources[0x36]	10984	1			T10	17		T11	1		T13	3
valid_sources[0x37]	10902	1			T10	26		T11	10		T13	1
valid_sources[0x38]	11002	1			T1	2		T10	11		T11	4
valid_sources[0x39]	10870	1			T1	1		T10	7		T11	13
valid_sources[0x3a]	11507	1			T10	13		T11	2		T14	1
valid_sources[0x3b]	10875	1			T10	24		T11	2		T13	1
valid_sources[0x3c]	11944	1			T10	5		T11	7		T13	5
valid_sources[0x3d]	10813	1			T1	3		T9	19		T10	15
valid_sources[0x3e]	10519	1			T1	3		T10	4		T11	7
valid_sources[0x3f]	10517	1			T10	8		T14	1		T15	10
valid_sources[0x40]	10849	1			T1	4		T10	15		T11	1
valid_sources[0x41]	17578	1			T10	7		T11	5		T14	2
valid_sources[0x42]	12743	1			T10	13		T11	2		T13	1
valid_sources[0x43]	12052	1			T10	16		T11	2		T14	3
valid_sources[0x44]	10930	1			T10	2		T11	23		T13	4
valid_sources[0x45]	10558	1			T10	11		T11	2		T15	4
valid_sources[0x46]	10816	1			T1	1		T10	5		T11	5
valid_sources[0x47]	34118	1			T10	6		T11	4		T13	2
valid_sources[0x48]	12063	1			T1	1		T10	5		T11	2
valid_sources[0x49]	11631	1			T10	11		T13	3		T14	4
valid_sources[0x4a]	10939	1			T10	13		T11	1		T13	3
valid_sources[0x4b]	11006	1			T10	17		T11	6		T13	1
valid_sources[0x4c]	11105	1			T1	1		T10	19		T13	2
valid_sources[0x4d]	10712	1			T1	2		T10	10		T11	12
valid_sources[0x4e]	10946	1			T10	5		T11	4		T13	7
valid_sources[0x4f]	10736	1			T1	2		T10	7		T13	2
valid_sources[0x50]	11684	1			T1	1		T10	8		T11	3
valid_sources[0x51]	10628	1			T10	20		T11	3		T13	2
valid_sources[0x52]	10566	1			T10	16		T11	1		T15	12
valid_sources[0x53]	11110	1			T10	23		T11	8		T14	1
valid_sources[0x54]	10624	1			T10	5		T11	5		T13	4
valid_sources[0x55]	10876	1			T1	4		T10	3		T11	7
valid_sources[0x56]	13540	1			T1	5		T10	5		T11	8
valid_sources[0x57]	10824	1			T1	4		T10	16		T11	5
valid_sources[0x58]	12962	1			T10	21		T11	2		T13	4
valid_sources[0x59]	10901	1			T1	2		T10	14		T11	3
valid_sources[0x5a]	10934	1			T10	17		T11	3		T13	3
valid_sources[0x5b]	10377	1			T10	2		T11	2		T13	1
valid_sources[0x5c]	11783	1			T1	1		T10	3		T11	7
valid_sources[0x5d]	10519	1			T10	14		T11	6		T15	21
valid_sources[0x5e]	11467	1			T10	10		T11	1		T13	2
valid_sources[0x5f]	10990	1			T10	11		T11	1		T13	1
valid_sources[0x60]	10139	1			T10	18		T11	3		T15	7
valid_sources[0x61]	11136	1			T10	11		T11	9		T13	1
valid_sources[0x62]	11737	1			T1	1		T10	10		T11	2
valid_sources[0x63]	12350	1			T10	4		T11	4		T15	13
valid_sources[0x64]	12199	1			T1	1		T10	15		T13	8
valid_sources[0x65]	10595	1			T10	6		T11	3		T13	2
valid_sources[0x66]	10350	1			T10	6		T11	9		T13	2
valid_sources[0x67]	10607	1			T1	2		T10	18		T11	1
valid_sources[0x68]	20327	1			T1	5		T10	12		T11	4
valid_sources[0x69]	10966	1			T10	2		T11	7		T13	3
valid_sources[0x6a]	10479	1			T1	1		T10	10		T11	4
valid_sources[0x6b]	11259	1			T10	11		T11	4		T15	6
valid_sources[0x6c]	10598	1			T1	2		T10	3		T11	2
valid_sources[0x6d]	11170	1			T1	4		T10	3		T11	10
valid_sources[0x6e]	29344	1			T1	2		T10	12		T11	10
valid_sources[0x6f]	16510	1			T1	4		T10	3		T11	2
valid_sources[0x70]	11049	1			T10	9		T11	3		T13	3
valid_sources[0x71]	10763	1			T10	1		T11	19		T13	1
valid_sources[0x72]	10771	1			T10	9		T11	12		T15	11
valid_sources[0x73]	10531	1			T1	1		T10	3		T11	2
valid_sources[0x74]	10792	1			T1	1		T10	28		T11	2
valid_sources[0x75]	12703	1			T1	9		T10	14		T11	4
valid_sources[0x76]	10885	1			T10	11		T11	4		T13	2
valid_sources[0x77]	11053	1			T10	4		T11	3		T13	3
valid_sources[0x78]	11083	1			T1	1		T10	10		T11	5
valid_sources[0x79]	26517	1			T10	7		T13	1		T15	14
valid_sources[0x7a]	10726	1			T10	8		T11	1		T13	2
valid_sources[0x7b]	13095	1			T9	36		T10	12		T11	2
valid_sources[0x7c]	11692	1			T1	1		T10	31		T11	2
valid_sources[0x7d]	10402	1			T10	19		T11	1		T13	5
valid_sources[0x7e]	10269	1			T1	2		T10	8		T15	5
valid_sources[0x7f]	14316	1			T1	1		T10	9		T11	1
valid_sources[0x80]	11177	1			T10	17		T13	1		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1652149

1

T1

78

T9

52

T10

952

values[0x0]

all_enables

biggest_size

151249

1

T1

67

T9

35

T10

339

values[0x1]

all_enables

biggest_size

149039

1

T1

57

T9

31

T10

341