Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	120520114	14973	0	0
claim_transition_if_regwen_rd_A	120520114	1822	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120520114	14973	0	0
T5	19564	0	0	0
T15	126667	2	0	0
T16	0	7	0	0
T17	0	5	0	0
T37	1032	0	0	0
T38	1262	0	0	0
T41	31394	0	0	0
T42	17572	0	0	0
T50	0	8	0	0
T61	25918	0	0	0
T62	2556	0	0	0
T92	49172	0	0	0
T94	2200	0	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	15	0	0
T156	0	2	0	0
T157	0	9	0	0
T158	0	5	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120520114	1822	0	0
T54	0	13	0	0
T119	0	46	0	0
T121	0	38	0	0
T123	0	1	0	0
T144	0	55	0	0
T159	243889	6	0	0
T160	218109	8	0	0
T161	0	7	0	0
T162	0	29	0	0
T163	0	9	0	0
T164	3973	0	0	0
T165	42778	0	0	0
T166	4091	0	0	0
T167	30914	0	0	0
T168	114395	0	0	0
T169	3865	0	0	0
T170	4458	0	0	0
T171	26273	0	0	0