Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1528663	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1752040

1

T1

17

T2

288

T3

220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2936117	1			T1	26		T2	259		T3	180
values[0x0]	171851	1			T1	4		T2	120		T3	83
values[0x1]	172735	1			T1	4		T2	99		T3	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2066350

1

T1

22

T2

327

T3

245

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9285	1			T1	1		T2	1		T3	3
valid_sources[0x01]	9824	1			T2	4		T4	2		T13	13
valid_sources[0x02]	8612	1			T2	4		T3	1		T4	4
valid_sources[0x03]	55654	1			T2	2		T4	7		T11	6
valid_sources[0x04]	8983	1			T2	1		T3	2		T4	6
valid_sources[0x05]	8720	1			T2	2		T4	1		T11	13
valid_sources[0x06]	27678	1			T2	1		T3	8		T4	9
valid_sources[0x07]	9827	1			T2	1		T3	1		T4	13
valid_sources[0x08]	9028	1			T2	1		T4	6		T11	4
valid_sources[0x09]	8945	1			T3	6		T4	17		T11	8
valid_sources[0x0a]	8738	1			T3	3		T4	1		T11	5
valid_sources[0x0b]	9082	1			T2	2		T4	2		T11	4
valid_sources[0x0c]	8795	1			T4	10		T11	2		T13	8
valid_sources[0x0d]	58134	1			T2	1		T3	5		T4	4
valid_sources[0x0e]	8447	1			T2	2		T4	2		T11	15
valid_sources[0x0f]	24763	1			T11	15		T13	16		T15	2
valid_sources[0x10]	12233	1			T2	3		T11	11		T13	15
valid_sources[0x11]	8388	1			T2	1		T13	12		T15	3
valid_sources[0x12]	8844	1			T2	1		T4	4		T11	17
valid_sources[0x13]	8411	1			T2	3		T4	13		T11	5
valid_sources[0x14]	8635	1			T2	3		T4	7		T11	13
valid_sources[0x15]	8948	1			T2	2		T3	6		T4	7
valid_sources[0x16]	9107	1			T2	2		T11	4		T13	16
valid_sources[0x17]	8314	1			T2	1		T11	11		T13	16
valid_sources[0x18]	8695	1			T2	2		T4	10		T13	8
valid_sources[0x19]	8911	1			T3	11		T4	1		T13	12
valid_sources[0x1a]	8932	1			T4	5		T11	13		T13	13
valid_sources[0x1b]	12880	1			T2	2		T3	1		T4	7
valid_sources[0x1c]	9099	1			T2	1		T4	1		T11	11
valid_sources[0x1d]	8796	1			T2	3		T3	1		T4	5
valid_sources[0x1e]	10348	1			T3	1		T4	19		T11	1
valid_sources[0x1f]	12520	1			T2	2		T4	10		T11	10
valid_sources[0x20]	9363	1			T2	4		T4	13		T11	23
valid_sources[0x21]	9153	1			T2	2		T4	1		T11	9
valid_sources[0x22]	8758	1			T13	5		T15	8		T32	15
valid_sources[0x23]	8428	1			T2	1		T3	1		T4	12
valid_sources[0x24]	8717	1			T2	2		T4	6		T13	10
valid_sources[0x25]	10260	1			T2	3		T3	7		T4	10
valid_sources[0x26]	11345	1			T2	1		T3	2		T4	7
valid_sources[0x27]	9204	1			T2	4		T3	6		T11	3
valid_sources[0x28]	14113	1			T2	1		T4	2		T11	4
valid_sources[0x29]	10464	1			T2	3		T4	2		T11	11
valid_sources[0x2a]	8351	1			T2	2		T4	2		T11	11
valid_sources[0x2b]	8400	1			T4	2		T11	7		T5	24
valid_sources[0x2c]	8600	1			T2	4		T11	12		T13	10
valid_sources[0x2d]	11126	1			T2	4		T3	2		T4	11
valid_sources[0x2e]	8875	1			T2	3		T3	4		T4	1
valid_sources[0x2f]	8753	1			T2	3		T3	8		T4	3
valid_sources[0x30]	8625	1			T2	4		T4	1		T11	8
valid_sources[0x31]	9015	1			T2	2		T3	7		T4	7
valid_sources[0x32]	8500	1			T1	1		T2	3		T4	3
valid_sources[0x33]	8719	1			T3	3		T4	1		T11	10
valid_sources[0x34]	8998	1			T2	1		T4	9		T11	3
valid_sources[0x35]	10606	1			T1	1		T2	2		T3	2
valid_sources[0x36]	8377	1			T2	1		T11	9		T13	10
valid_sources[0x37]	38678	1			T2	2		T3	1		T4	10
valid_sources[0x38]	8790	1			T4	4		T11	16		T13	13
valid_sources[0x39]	29239	1			T4	9		T11	14		T13	8
valid_sources[0x3a]	42768	1			T1	1		T2	2		T3	5
valid_sources[0x3b]	12518	1			T2	1		T4	7		T11	16
valid_sources[0x3c]	94152	1			T4	2		T11	18		T13	18
valid_sources[0x3d]	16788	1			T2	4		T11	7		T13	7
valid_sources[0x3e]	9539	1			T2	2		T4	8		T11	25
valid_sources[0x3f]	128940	1			T3	1		T4	1		T11	9
valid_sources[0x40]	9008	1			T2	2		T4	1		T11	19
valid_sources[0x41]	10439	1			T1	1		T2	4		T3	5
valid_sources[0x42]	8388	1			T2	2		T4	1		T11	36
valid_sources[0x43]	8847	1			T4	5		T11	5		T13	17
valid_sources[0x44]	8807	1			T2	3		T4	9		T11	4
valid_sources[0x45]	74320	1			T2	4		T4	10		T11	13
valid_sources[0x46]	27048	1			T4	4		T11	8		T13	9
valid_sources[0x47]	8422	1			T3	1		T4	1		T11	6
valid_sources[0x48]	9133	1			T2	1		T11	18		T13	12
valid_sources[0x49]	9534	1			T2	3		T4	5		T11	5
valid_sources[0x4a]	8790	1			T4	7		T11	2		T13	7
valid_sources[0x4b]	12132	1			T2	1		T3	4		T4	11
valid_sources[0x4c]	8246	1			T2	1		T11	6		T13	15
valid_sources[0x4d]	9353	1			T2	4		T4	6		T11	5
valid_sources[0x4e]	9955	1			T2	2		T4	4		T11	4
valid_sources[0x4f]	8963	1			T2	3		T3	8		T4	5
valid_sources[0x50]	8841	1			T2	2		T3	3		T4	2
valid_sources[0x51]	10765	1			T1	1		T2	2		T3	4
valid_sources[0x52]	8986	1			T2	1		T3	1		T4	2
valid_sources[0x53]	18911	1			T2	2		T4	4		T13	11
valid_sources[0x54]	11003	1			T3	3		T4	10		T11	5
valid_sources[0x55]	8323	1			T2	4		T4	5		T11	1
valid_sources[0x56]	10405	1			T2	1		T4	4		T11	12
valid_sources[0x57]	22295	1			T2	1		T3	1		T4	3
valid_sources[0x58]	10398	1			T2	1		T4	5		T11	9
valid_sources[0x59]	9146	1			T2	3		T4	20		T13	19
valid_sources[0x5a]	42549	1			T2	4		T4	5		T13	6
valid_sources[0x5b]	12180	1			T2	1		T3	1		T4	7
valid_sources[0x5c]	11983	1			T2	2		T4	5		T13	17
valid_sources[0x5d]	8733	1			T2	3		T4	3		T11	9
valid_sources[0x5e]	8819	1			T2	2		T4	3		T11	10
valid_sources[0x5f]	8852	1			T4	10		T11	1		T13	9
valid_sources[0x60]	8810	1			T2	3		T3	1		T4	7
valid_sources[0x61]	8741	1			T13	12		T14	1		T15	2
valid_sources[0x62]	9085	1			T2	2		T4	9		T11	4
valid_sources[0x63]	8833	1			T2	1		T4	4		T11	14
valid_sources[0x64]	8757	1			T4	5		T11	9		T13	7
valid_sources[0x65]	9190	1			T4	7		T11	2		T13	10
valid_sources[0x66]	8650	1			T2	2		T4	3		T11	8
valid_sources[0x67]	8381	1			T2	1		T4	7		T11	29
valid_sources[0x68]	9075	1			T2	2		T4	3		T11	8
valid_sources[0x69]	8616	1			T2	5		T3	2		T4	7
valid_sources[0x6a]	11187	1			T4	1		T11	2		T13	9
valid_sources[0x6b]	9422	1			T1	1		T2	2		T3	4
valid_sources[0x6c]	9710	1			T2	2		T4	9		T11	13
valid_sources[0x6d]	8680	1			T1	2		T2	3		T4	7
valid_sources[0x6e]	10196	1			T2	2		T4	4		T11	1
valid_sources[0x6f]	10025	1			T2	3		T3	1		T11	13
valid_sources[0x70]	8907	1			T1	1		T3	1		T4	9
valid_sources[0x71]	10778	1			T2	2		T3	2		T4	5
valid_sources[0x72]	8797	1			T2	4		T3	10		T4	7
valid_sources[0x73]	8630	1			T2	4		T11	25		T13	14
valid_sources[0x74]	8488	1			T2	1		T3	2		T4	10
valid_sources[0x75]	25276	1			T3	1		T4	11		T11	10
valid_sources[0x76]	8956	1			T2	1		T3	1		T4	12
valid_sources[0x77]	15034	1			T3	2		T4	10		T11	5
valid_sources[0x78]	8593	1			T2	1		T13	13		T15	7
valid_sources[0x79]	9079	1			T1	2		T2	3		T3	3
valid_sources[0x7a]	11794	1			T1	2		T2	1		T4	3
valid_sources[0x7b]	10149	1			T4	5		T11	3		T13	21
valid_sources[0x7c]	10732	1			T2	3		T4	1		T11	4
valid_sources[0x7d]	19667	1			T2	2		T4	2		T11	3
valid_sources[0x7e]	8997	1			T1	3		T2	1		T3	2
valid_sources[0x7f]	10911	1			T1	1		T2	4		T4	1
valid_sources[0x80]	9024	1			T2	2		T4	5		T11	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1454907

1

T1

11

T2

127

T3

86

values[0x0]

all_enables

biggest_size

149153

1

T1

4

T2

85

T3

72

values[0x1]

all_enables

biggest_size

147980

1

T1

2

T2

76

T3

62