Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1993667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2222377

1

T2

1028

T3

15

T10

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3860630	1			T2	929		T3	5		T10	5
values[0x0]	177768	1			T2	344		T3	10		T10	7
values[0x1]	177646	1			T2	336		T3	5		T10	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1585403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2630641

1

T2

1147

T3

16

T10

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20230	1			T2	7		T6	171		T12	7
valid_sources[0x01]	13774	1			T2	2		T6	193		T12	4
valid_sources[0x02]	13070	1			T2	8		T11	2		T6	180
valid_sources[0x03]	12646	1			T2	1		T6	175		T12	6
valid_sources[0x04]	13916	1			T2	7		T11	1		T6	188
valid_sources[0x05]	13202	1			T2	5		T6	161		T12	3
valid_sources[0x06]	13317	1			T2	7		T11	3		T6	177
valid_sources[0x07]	14329	1			T2	5		T11	3		T6	194
valid_sources[0x08]	13064	1			T2	7		T11	2		T6	195
valid_sources[0x09]	12772	1			T2	4		T11	2		T6	160
valid_sources[0x0a]	13032	1			T2	11		T11	2		T6	206
valid_sources[0x0b]	13168	1			T2	5		T11	3		T6	191
valid_sources[0x0c]	19272	1			T2	3		T11	1		T6	183
valid_sources[0x0d]	13064	1			T2	11		T11	6		T6	161
valid_sources[0x0e]	13631	1			T2	4		T11	2		T6	181
valid_sources[0x0f]	12876	1			T2	8		T6	188		T12	5
valid_sources[0x10]	13028	1			T2	5		T6	165		T12	7
valid_sources[0x11]	36179	1			T2	5		T11	1		T6	222
valid_sources[0x12]	85103	1			T2	7		T4	1		T11	4
valid_sources[0x13]	13205	1			T2	6		T11	2		T6	185
valid_sources[0x14]	13448	1			T2	2		T11	4		T6	188
valid_sources[0x15]	27679	1			T2	6		T11	7		T6	168
valid_sources[0x16]	12855	1			T2	8		T11	3		T6	185
valid_sources[0x17]	12871	1			T2	8		T11	6		T6	178
valid_sources[0x18]	13602	1			T2	9		T11	2		T6	170
valid_sources[0x19]	13323	1			T2	10		T4	68		T11	1
valid_sources[0x1a]	15150	1			T2	8		T11	5		T6	181
valid_sources[0x1b]	31015	1			T2	5		T6	205		T12	8
valid_sources[0x1c]	13083	1			T2	5		T11	5		T6	201
valid_sources[0x1d]	13088	1			T2	9		T11	5		T6	199
valid_sources[0x1e]	15314	1			T2	7		T11	1		T6	191
valid_sources[0x1f]	14794	1			T2	2		T11	5		T6	188
valid_sources[0x20]	12835	1			T2	5		T11	3		T6	207
valid_sources[0x21]	14068	1			T2	11		T11	2		T6	204
valid_sources[0x22]	18238	1			T2	6		T11	14		T6	206
valid_sources[0x23]	14523	1			T2	3		T6	193		T12	6
valid_sources[0x24]	14855	1			T2	2		T11	6		T6	186
valid_sources[0x25]	13239	1			T2	3		T4	85		T11	4
valid_sources[0x26]	13815	1			T2	6		T6	211		T12	6
valid_sources[0x27]	13144	1			T2	7		T11	4		T6	158
valid_sources[0x28]	15123	1			T2	3		T11	1		T6	180
valid_sources[0x29]	13748	1			T11	10		T6	208		T12	6
valid_sources[0x2a]	14217	1			T2	5		T11	7		T6	170
valid_sources[0x2b]	13384	1			T2	9		T11	1		T6	178
valid_sources[0x2c]	15254	1			T2	3		T11	1		T6	190
valid_sources[0x2d]	13008	1			T2	4		T11	3		T6	193
valid_sources[0x2e]	15669	1			T2	6		T11	1		T6	179
valid_sources[0x2f]	12818	1			T2	3		T6	184		T12	3
valid_sources[0x30]	12500	1			T2	6		T11	1		T6	199
valid_sources[0x31]	42908	1			T2	7		T11	3		T6	180
valid_sources[0x32]	15724	1			T2	3		T6	195		T12	2
valid_sources[0x33]	13780	1			T2	5		T11	6		T6	192
valid_sources[0x34]	13232	1			T2	2		T4	18		T11	3
valid_sources[0x35]	13064	1			T2	8		T4	10		T6	176
valid_sources[0x36]	13024	1			T2	6		T11	3		T6	192
valid_sources[0x37]	15925	1			T2	10		T11	5		T6	174
valid_sources[0x38]	13376	1			T2	6		T4	85		T11	5
valid_sources[0x39]	13094	1			T2	6		T11	5		T6	201
valid_sources[0x3a]	12925	1			T2	7		T11	1		T6	200
valid_sources[0x3b]	24859	1			T2	11		T11	2		T6	211
valid_sources[0x3c]	31785	1			T2	2		T11	4		T6	182
valid_sources[0x3d]	16796	1			T2	4		T11	11		T6	189
valid_sources[0x3e]	13009	1			T2	7		T4	3		T11	6
valid_sources[0x3f]	14899	1			T2	6		T11	4		T6	178
valid_sources[0x40]	13297	1			T2	12		T4	19		T6	180
valid_sources[0x41]	12688	1			T2	6		T11	10		T6	200
valid_sources[0x42]	12761	1			T2	8		T11	1		T6	159
valid_sources[0x43]	14254	1			T2	5		T11	3		T6	153
valid_sources[0x44]	13164	1			T2	5		T11	1		T6	172
valid_sources[0x45]	12765	1			T2	4		T11	4		T6	162
valid_sources[0x46]	12638	1			T2	2		T6	190		T12	4
valid_sources[0x47]	13009	1			T2	6		T11	2		T6	159
valid_sources[0x48]	13011	1			T2	5		T11	3		T6	161
valid_sources[0x49]	12695	1			T2	4		T11	3		T6	177
valid_sources[0x4a]	14535	1			T2	6		T11	1		T6	168
valid_sources[0x4b]	12998	1			T2	6		T11	3		T6	180
valid_sources[0x4c]	13343	1			T2	6		T6	183		T12	5
valid_sources[0x4d]	12797	1			T2	5		T6	179		T12	7
valid_sources[0x4e]	12722	1			T2	8		T11	5		T6	186
valid_sources[0x4f]	14298	1			T2	11		T11	1		T6	175
valid_sources[0x50]	13071	1			T2	8		T6	163		T12	2
valid_sources[0x51]	12736	1			T2	7		T11	8		T6	189
valid_sources[0x52]	13311	1			T2	8		T11	2		T6	166
valid_sources[0x53]	14346	1			T2	8		T11	2		T6	170
valid_sources[0x54]	13535	1			T2	9		T11	3		T6	208
valid_sources[0x55]	13476	1			T2	10		T11	1		T6	169
valid_sources[0x56]	13549	1			T2	7		T11	2		T6	175
valid_sources[0x57]	13622	1			T2	5		T11	5		T6	185
valid_sources[0x58]	13995	1			T2	8		T11	5		T6	168
valid_sources[0x59]	15528	1			T2	9		T11	5		T6	179
valid_sources[0x5a]	13085	1			T2	12		T11	4		T6	178
valid_sources[0x5b]	12651	1			T2	7		T11	3		T6	183
valid_sources[0x5c]	14325	1			T2	9		T11	1		T6	187
valid_sources[0x5d]	13177	1			T2	4		T11	7		T6	186
valid_sources[0x5e]	13081	1			T2	9		T11	2		T6	183
valid_sources[0x5f]	12785	1			T2	12		T11	3		T6	167
valid_sources[0x60]	13110	1			T2	6		T11	2		T6	190
valid_sources[0x61]	13542	1			T2	6		T6	173		T12	13
valid_sources[0x62]	12870	1			T2	7		T3	20		T11	5
valid_sources[0x63]	36525	1			T2	7		T6	175		T12	2
valid_sources[0x64]	32371	1			T2	8		T11	2		T6	198
valid_sources[0x65]	13254	1			T2	8		T11	6		T6	173
valid_sources[0x66]	13027	1			T2	7		T11	3		T6	202
valid_sources[0x67]	13100	1			T2	4		T11	5		T6	208
valid_sources[0x68]	15583	1			T2	11		T11	7		T6	185
valid_sources[0x69]	15513	1			T2	4		T4	25		T11	4
valid_sources[0x6a]	12745	1			T2	5		T6	162		T12	3
valid_sources[0x6b]	96733	1			T2	7		T11	1		T6	183
valid_sources[0x6c]	13076	1			T2	7		T11	5		T6	181
valid_sources[0x6d]	13178	1			T2	7		T11	1		T6	185
valid_sources[0x6e]	16233	1			T2	7		T11	1		T6	180
valid_sources[0x6f]	13473	1			T2	2		T11	13		T6	176
valid_sources[0x70]	14491	1			T2	5		T11	7		T6	179
valid_sources[0x71]	13121	1			T2	8		T4	84		T11	1
valid_sources[0x72]	27686	1			T2	5		T11	7		T6	174
valid_sources[0x73]	40565	1			T2	6		T11	4		T6	162
valid_sources[0x74]	78670	1			T2	9		T11	1		T6	174
valid_sources[0x75]	12504	1			T2	7		T6	190		T12	4
valid_sources[0x76]	12842	1			T2	7		T11	5		T6	167
valid_sources[0x77]	12907	1			T2	11		T6	170		T12	7
valid_sources[0x78]	56814	1			T2	4		T11	4		T6	179
valid_sources[0x79]	62577	1			T2	11		T11	2		T6	177
valid_sources[0x7a]	14363	1			T2	10		T11	1		T6	162
valid_sources[0x7b]	14795	1			T2	7		T4	7		T11	3
valid_sources[0x7c]	13153	1			T2	4		T4	10		T11	12
valid_sources[0x7d]	14753	1			T2	2		T11	1		T6	194
valid_sources[0x7e]	13158	1			T2	9		T6	190		T12	4
valid_sources[0x7f]	18783	1			T2	7		T11	2		T6	179
valid_sources[0x80]	13021	1			T2	4		T4	20		T11	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1916041

1

T2

437

T3

2

T10

1

values[0x0]

all_enables

biggest_size

154074

1

T2

297

T3

9

T10

6

values[0x1]

all_enables

biggest_size

152262

1

T2

294

T3

4

T10

6