Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	116262820	14515	0	0
claim_transition_if_regwen_rd_A	116262820	1643	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116262820	14515	0	0
T6	421132	2	0	0
T12	31072	0	0	0
T13	22637	0	0	0
T14	26939	0	0	0
T15	707378	0	0	0
T16	104497	0	0	0
T34	23268	0	0	0
T35	34825	0	0	0
T55	27647	0	0	0
T56	18268	0	0	0
T83	0	7	0	0
T102	0	13	0	0
T103	0	4	0	0
T140	0	1	0	0
T141	0	20	0	0
T142	0	2	0	0
T143	0	12	0	0
T144	0	6	0	0
T145	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116262820	1643	0	0
T22	37016	0	0	0
T23	34390	0	0	0
T24	86243	0	0	0
T53	16242	0	0	0
T84	200179	8	0	0
T86	0	3	0	0
T111	0	10	0	0
T130	0	48	0	0
T145	0	4	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	23	0	0
T149	0	458	0	0
T150	0	3	0	0
T151	815	0	0	0
T152	20159	0	0	0
T153	101100	0	0	0
T154	4253	0	0	0
T155	67161	0	0	0