Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1680629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1901976

1

T2

1049

T3

130

T9

800

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3242674	1			T2	1318		T3	128		T9	774
values[0x0]	169238	1			T2	261		T3	38		T9	270
values[0x1]	170693	1			T2	243		T3	42		T9	234

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1335350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2247255

1

T2

1208

T3

148

T9

899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7721	1			T2	10		T16	3		T43	5
valid_sources[0x01]	7916	1			T13	7		T16	3		T43	4
valid_sources[0x02]	10500	1			T2	9		T3	1		T13	12
valid_sources[0x03]	8206	1			T2	7		T3	1		T10	1
valid_sources[0x04]	53763	1			T2	4		T13	8		T16	4
valid_sources[0x05]	11813	1			T2	6		T10	19		T16	7
valid_sources[0x06]	7770	1			T2	7		T16	5		T43	3
valid_sources[0x07]	8052	1			T2	7		T13	4		T16	4
valid_sources[0x08]	8051	1			T2	4		T13	19		T16	6
valid_sources[0x09]	8244	1			T2	20		T10	1		T13	5
valid_sources[0x0a]	9379	1			T2	3		T3	1		T13	5
valid_sources[0x0b]	10018	1			T2	5		T13	11		T16	8
valid_sources[0x0c]	7929	1			T2	8		T16	5		T43	3
valid_sources[0x0d]	7767	1			T2	9		T13	1		T16	7
valid_sources[0x0e]	8024	1			T2	1		T13	2		T16	5
valid_sources[0x0f]	7897	1			T2	5		T3	2		T13	8
valid_sources[0x10]	8518	1			T10	10		T13	9		T16	5
valid_sources[0x11]	8080	1			T2	4		T3	1		T13	2
valid_sources[0x12]	8046	1			T2	6		T11	2		T16	4
valid_sources[0x13]	7654	1			T2	16		T16	5		T43	2
valid_sources[0x14]	7860	1			T2	5		T13	8		T16	9
valid_sources[0x15]	8218	1			T2	10		T16	4		T43	5
valid_sources[0x16]	8005	1			T2	9		T10	7		T13	16
valid_sources[0x17]	9647	1			T2	8		T13	23		T16	1
valid_sources[0x18]	8582	1			T2	4		T3	1		T13	26
valid_sources[0x19]	8191	1			T2	5		T10	6		T13	13
valid_sources[0x1a]	7767	1			T2	7		T3	3		T13	1
valid_sources[0x1b]	9319	1			T2	8		T13	8		T16	4
valid_sources[0x1c]	8323	1			T2	3		T3	5		T16	11
valid_sources[0x1d]	8231	1			T2	6		T13	12		T16	5
valid_sources[0x1e]	7830	1			T2	14		T13	1		T14	6
valid_sources[0x1f]	8060	1			T2	3		T3	5		T13	19
valid_sources[0x20]	8475	1			T2	6		T13	10		T16	4
valid_sources[0x21]	9385	1			T2	3		T11	1		T13	4
valid_sources[0x22]	23580	1			T2	5		T3	1		T13	14
valid_sources[0x23]	8034	1			T2	1		T3	8		T13	3
valid_sources[0x24]	8643	1			T2	2		T3	3		T16	3
valid_sources[0x25]	26090	1			T2	9		T11	2		T13	8
valid_sources[0x26]	8178	1			T2	14		T13	5		T16	6
valid_sources[0x27]	8190	1			T2	3		T3	2		T13	18
valid_sources[0x28]	7971	1			T2	5		T13	6		T16	4
valid_sources[0x29]	8182	1			T2	6		T3	3		T16	7
valid_sources[0x2a]	9688	1			T2	12		T13	9		T16	4
valid_sources[0x2b]	7998	1			T2	3		T13	6		T16	4
valid_sources[0x2c]	8142	1			T2	7		T10	9		T13	4
valid_sources[0x2d]	7803	1			T2	4		T11	2		T13	4
valid_sources[0x2e]	7780	1			T2	3		T16	11		T43	4
valid_sources[0x2f]	29383	1			T2	9		T13	7		T16	5
valid_sources[0x30]	7901	1			T2	8		T10	8		T13	3
valid_sources[0x31]	9661	1			T2	18		T10	31		T13	29
valid_sources[0x32]	10853	1			T2	4		T3	5		T13	10
valid_sources[0x33]	8010	1			T2	2		T11	1		T16	3
valid_sources[0x34]	8461	1			T2	10		T16	5		T43	4
valid_sources[0x35]	8439	1			T2	7		T13	6		T16	6
valid_sources[0x36]	8367	1			T2	5		T13	8		T16	4
valid_sources[0x37]	8161	1			T2	3		T3	2		T13	14
valid_sources[0x38]	8523	1			T2	4		T3	1		T13	5
valid_sources[0x39]	7794	1			T2	1		T10	1		T13	4
valid_sources[0x3a]	8052	1			T2	7		T16	3		T43	3
valid_sources[0x3b]	17624	1			T2	8		T3	3		T13	3
valid_sources[0x3c]	12141	1			T2	6		T3	2		T16	2
valid_sources[0x3d]	9331	1			T2	9		T13	12		T16	4
valid_sources[0x3e]	8236	1			T2	7		T13	16		T16	2
valid_sources[0x3f]	8098	1			T10	2		T13	3		T16	2
valid_sources[0x40]	8269	1			T2	8		T11	1		T13	1
valid_sources[0x41]	29572	1			T2	8		T13	12		T16	2
valid_sources[0x42]	9117	1			T2	15		T3	6		T16	3
valid_sources[0x43]	24587	1			T2	12		T3	6		T13	19
valid_sources[0x44]	8336	1			T2	5		T13	7		T16	4
valid_sources[0x45]	7983	1			T2	9		T13	2		T16	6
valid_sources[0x46]	9118	1			T2	14		T3	4		T11	1
valid_sources[0x47]	8233	1			T2	6		T3	2		T13	2
valid_sources[0x48]	7889	1			T2	2		T13	11		T16	1
valid_sources[0x49]	8212	1			T2	9		T13	27		T16	6
valid_sources[0x4a]	10303	1			T2	8		T13	10		T16	3
valid_sources[0x4b]	9979	1			T2	8		T13	8		T16	6
valid_sources[0x4c]	8217	1			T2	11		T13	16		T16	4
valid_sources[0x4d]	10281	1			T2	1		T13	7		T16	2
valid_sources[0x4e]	9879	1			T2	6		T16	2		T43	3
valid_sources[0x4f]	9072	1			T13	26		T15	326		T16	4
valid_sources[0x50]	14828	1			T2	8		T10	17		T13	3
valid_sources[0x51]	8066	1			T2	3		T13	24		T16	2
valid_sources[0x52]	8621	1			T2	7		T10	3		T13	20
valid_sources[0x53]	9537	1			T2	8		T3	1		T13	6
valid_sources[0x54]	8642	1			T2	8		T13	8		T16	4
valid_sources[0x55]	8219	1			T2	3		T3	3		T13	1
valid_sources[0x56]	7938	1			T13	4		T16	5		T43	4
valid_sources[0x57]	12326	1			T2	5		T13	10		T16	7
valid_sources[0x58]	8158	1			T2	6		T13	3		T16	2
valid_sources[0x59]	7870	1			T2	13		T13	2		T16	4
valid_sources[0x5a]	36256	1			T2	8		T13	32		T16	1
valid_sources[0x5b]	40550	1			T2	3		T3	2		T13	11
valid_sources[0x5c]	8211	1			T2	15		T3	1		T10	20
valid_sources[0x5d]	8419	1			T2	13		T13	5		T16	6
valid_sources[0x5e]	7870	1			T2	4		T3	1		T13	2
valid_sources[0x5f]	137271	1			T2	7		T3	3		T10	8
valid_sources[0x60]	8494	1			T2	6		T3	5		T10	10
valid_sources[0x61]	8244	1			T2	2		T13	1		T16	2
valid_sources[0x62]	8293	1			T2	12		T13	1		T16	3
valid_sources[0x63]	7961	1			T2	11		T13	11		T16	4
valid_sources[0x64]	7971	1			T2	12		T13	1		T16	7
valid_sources[0x65]	8546	1			T2	1		T3	1		T13	16
valid_sources[0x66]	26592	1			T2	9		T13	2		T16	4
valid_sources[0x67]	7906	1			T2	9		T13	25		T16	8
valid_sources[0x68]	14307	1			T2	3		T13	12		T16	2
valid_sources[0x69]	8085	1			T2	7		T13	4		T16	8
valid_sources[0x6a]	8104	1			T2	9		T3	3		T10	13
valid_sources[0x6b]	8401	1			T2	8		T16	1		T43	6
valid_sources[0x6c]	8179	1			T2	3		T13	7		T14	2
valid_sources[0x6d]	7824	1			T2	15		T3	2		T16	3
valid_sources[0x6e]	7998	1			T2	14		T13	1		T16	9
valid_sources[0x6f]	8006	1			T2	3		T13	28		T16	10
valid_sources[0x70]	8144	1			T13	32		T16	15		T43	3
valid_sources[0x71]	8147	1			T2	5		T13	8		T16	4
valid_sources[0x72]	8144	1			T2	4		T10	4		T13	1
valid_sources[0x73]	7796	1			T2	6		T13	1		T16	5
valid_sources[0x74]	8317	1			T2	9		T13	9		T16	4
valid_sources[0x75]	8385	1			T2	14		T10	15		T13	6
valid_sources[0x76]	8324	1			T2	1		T3	2		T13	2
valid_sources[0x77]	13215	1			T2	2		T13	7		T16	6
valid_sources[0x78]	8312	1			T2	2		T13	9		T16	10
valid_sources[0x79]	8220	1			T2	27		T3	7		T13	5
valid_sources[0x7a]	8488	1			T2	5		T3	3		T13	7
valid_sources[0x7b]	24604	1			T2	6		T13	3		T16	2
valid_sources[0x7c]	7974	1			T2	19		T13	3		T16	5
valid_sources[0x7d]	7989	1			T2	9		T13	9		T16	1
valid_sources[0x7e]	8426	1			T2	15		T12	69		T13	8
valid_sources[0x7f]	9893	1			T2	17		T3	4		T16	1
valid_sources[0x80]	8580	1			T2	9		T10	12		T13	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1608811

1

T2

618

T3

64

T9

365

values[0x0]

all_enables

biggest_size

146670

1

T2

226

T3

34

T9

230

values[0x1]

all_enables

biggest_size

146495

1

T2

205

T3

32

T9

205