Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111656790	15832	0	0
claim_transition_if_regwen_rd_A	111656790	1273	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111656790	15832	0	0
T4	172026	2	0	0
T5	175031	0	0	0
T6	19109	0	0	0
T18	382788	0	0	0
T21	0	3	0	0
T29	1091	0	0	0
T30	6340	0	0	0
T34	1357	0	0	0
T35	1514	0	0	0
T53	0	4	0	0
T85	6399	0	0	0
T97	30026	0	0	0
T103	0	1	0	0
T106	0	5	0	0
T138	0	1	0	0
T176	0	1	0	0
T177	0	5	0	0
T178	0	1	0	0
T179	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111656790	1273	0	0
T147	0	4	0	0
T148	0	4	0	0
T178	121492	4	0	0
T180	0	12	0	0
T181	0	6	0	0
T182	0	31	0	0
T183	0	2	0	0
T184	0	47	0	0
T185	0	46	0	0
T186	0	35	0	0
T187	944	0	0	0
T188	39609	0	0	0
T189	290310	0	0	0
T190	35989	0	0	0
T191	26349	0	0	0
T192	2651	0	0	0
T193	4012	0	0	0
T194	1008	0	0	0
T195	65827	0	0	0