Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1528965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1750175

1

T3

1070

T8

825

T9

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2936673	1			T3	980		T8	641		T9	27
values[0x0]	171303	1			T3	335		T8	317		T9	4
values[0x1]	171164	1			T3	337		T8	315		T9	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2064722

1

T3

1190

T8

941

T9

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12821	1			T3	2		T8	9		T4	1
valid_sources[0x01]	10022	1			T3	6		T4	1		T10	1
valid_sources[0x02]	10822	1			T3	4		T8	3		T4	1
valid_sources[0x03]	13202	1			T3	5		T8	9		T10	2
valid_sources[0x04]	12089	1			T3	1		T8	17		T9	1
valid_sources[0x05]	12546	1			T3	10		T8	7		T10	4
valid_sources[0x06]	9758	1			T3	8		T8	7		T4	1
valid_sources[0x07]	9991	1			T3	10		T8	1		T4	3
valid_sources[0x08]	9969	1			T3	7		T8	2		T10	7
valid_sources[0x09]	15412	1			T3	5		T8	7		T4	2
valid_sources[0x0a]	10033	1			T3	5		T8	6		T4	1
valid_sources[0x0b]	9861	1			T3	9		T8	1		T4	1
valid_sources[0x0c]	9649	1			T3	4		T8	3		T4	1
valid_sources[0x0d]	9494	1			T3	5		T4	1		T10	2
valid_sources[0x0e]	10029	1			T3	5		T8	3		T4	1
valid_sources[0x0f]	9857	1			T3	10		T8	10		T4	1
valid_sources[0x10]	10139	1			T3	8		T8	7		T10	10
valid_sources[0x11]	11948	1			T3	3		T8	2		T4	3
valid_sources[0x12]	9879	1			T3	6		T8	3		T10	2
valid_sources[0x13]	10409	1			T3	11		T8	3		T4	1
valid_sources[0x14]	11867	1			T3	7		T8	3		T4	1
valid_sources[0x15]	9573	1			T3	8		T8	2		T4	1
valid_sources[0x16]	9698	1			T3	9		T4	2		T10	6
valid_sources[0x17]	10183	1			T3	5		T8	2		T4	1
valid_sources[0x18]	11147	1			T3	2		T8	1		T10	1
valid_sources[0x19]	9852	1			T3	10		T8	10		T4	1
valid_sources[0x1a]	9796	1			T3	1		T8	6		T4	3
valid_sources[0x1b]	9728	1			T3	9		T8	4		T10	1
valid_sources[0x1c]	12847	1			T3	6		T8	1		T9	1
valid_sources[0x1d]	10190	1			T3	7		T8	5		T4	2
valid_sources[0x1e]	9869	1			T3	10		T8	2		T10	3
valid_sources[0x1f]	10973	1			T3	6		T8	7		T4	1
valid_sources[0x20]	12782	1			T3	5		T8	5		T10	8
valid_sources[0x21]	23120	1			T3	12		T8	2		T10	1
valid_sources[0x22]	9858	1			T3	2		T8	5		T4	1
valid_sources[0x23]	9804	1			T3	7		T8	7		T4	4
valid_sources[0x24]	10597	1			T3	5		T8	7		T11	1
valid_sources[0x25]	12764	1			T3	5		T8	5		T4	1
valid_sources[0x26]	10211	1			T3	6		T8	1		T9	1
valid_sources[0x27]	10016	1			T3	9		T8	3		T4	3
valid_sources[0x28]	10149	1			T3	8		T8	8		T4	1
valid_sources[0x29]	11895	1			T3	9		T8	5		T9	1
valid_sources[0x2a]	11505	1			T3	6		T8	4		T10	7
valid_sources[0x2b]	10039	1			T3	9		T8	7		T10	3
valid_sources[0x2c]	9724	1			T3	4		T8	5		T4	3
valid_sources[0x2d]	11350	1			T3	3		T8	3		T4	2
valid_sources[0x2e]	10495	1			T3	7		T8	4		T4	1
valid_sources[0x2f]	9771	1			T3	5		T8	3		T4	1
valid_sources[0x30]	9945	1			T3	8		T8	5		T10	2
valid_sources[0x31]	10055	1			T3	3		T8	4		T10	7
valid_sources[0x32]	9974	1			T3	11		T8	1		T10	8
valid_sources[0x33]	11128	1			T3	6		T8	6		T4	1
valid_sources[0x34]	10513	1			T3	4		T8	4		T4	3
valid_sources[0x35]	10097	1			T3	6		T8	9		T10	9
valid_sources[0x36]	10190	1			T3	6		T8	3		T10	6
valid_sources[0x37]	9553	1			T3	5		T8	4		T10	9
valid_sources[0x38]	10047	1			T3	5		T8	11		T4	3
valid_sources[0x39]	10787	1			T3	7		T8	5		T10	5
valid_sources[0x3a]	22706	1			T3	10		T8	5		T4	1
valid_sources[0x3b]	10186	1			T3	10		T8	3		T9	3
valid_sources[0x3c]	10123	1			T3	10		T8	2		T4	1
valid_sources[0x3d]	10107	1			T3	7		T8	1		T4	1
valid_sources[0x3e]	10102	1			T3	6		T8	3		T4	4
valid_sources[0x3f]	10160	1			T3	11		T8	5		T4	2
valid_sources[0x40]	11051	1			T3	7		T8	7		T4	1
valid_sources[0x41]	13313	1			T3	3		T8	4		T4	1
valid_sources[0x42]	22321	1			T3	6		T8	3		T4	1
valid_sources[0x43]	29611	1			T3	7		T8	1		T9	2
valid_sources[0x44]	9931	1			T3	3		T8	7		T11	1
valid_sources[0x45]	9987	1			T3	11		T8	9		T4	1
valid_sources[0x46]	9849	1			T3	6		T8	7		T4	1
valid_sources[0x47]	9955	1			T3	7		T8	7		T11	2
valid_sources[0x48]	10001	1			T3	8		T8	11		T4	3
valid_sources[0x49]	11303	1			T3	7		T8	2		T10	7
valid_sources[0x4a]	11149	1			T3	9		T8	5		T4	2
valid_sources[0x4b]	10016	1			T3	8		T8	12		T4	1
valid_sources[0x4c]	10366	1			T3	6		T8	2		T4	2
valid_sources[0x4d]	9841	1			T3	6		T8	6		T4	1
valid_sources[0x4e]	9838	1			T3	5		T10	6		T11	2
valid_sources[0x4f]	10023	1			T3	10		T8	4		T4	3
valid_sources[0x50]	10523	1			T3	11		T8	1		T4	6
valid_sources[0x51]	13202	1			T3	11		T8	3		T10	1
valid_sources[0x52]	9733	1			T3	9		T8	2		T4	6
valid_sources[0x53]	10455	1			T3	6		T8	7		T4	2
valid_sources[0x54]	9462	1			T3	11		T8	10		T10	8
valid_sources[0x55]	10048	1			T3	6		T8	11		T4	1
valid_sources[0x56]	14676	1			T3	9		T8	4		T4	1
valid_sources[0x57]	12495	1			T3	4		T8	3		T4	4
valid_sources[0x58]	22423	1			T3	8		T8	6		T10	10
valid_sources[0x59]	11627	1			T3	9		T8	7		T4	2
valid_sources[0x5a]	11741	1			T3	7		T8	1		T4	2
valid_sources[0x5b]	9981	1			T3	6		T8	3		T10	1
valid_sources[0x5c]	9827	1			T3	5		T8	7		T4	1
valid_sources[0x5d]	11297	1			T3	8		T8	7		T4	1
valid_sources[0x5e]	10121	1			T3	11		T8	7		T10	4
valid_sources[0x5f]	11374	1			T3	9		T8	5		T4	1
valid_sources[0x60]	11813	1			T3	11		T8	1		T10	3
valid_sources[0x61]	10208	1			T3	4		T8	4		T4	1
valid_sources[0x62]	9720	1			T3	4		T8	2		T4	3
valid_sources[0x63]	9955	1			T3	4		T8	4		T9	2
valid_sources[0x64]	12894	1			T3	4		T8	9		T4	1
valid_sources[0x65]	10222	1			T3	2		T8	4		T10	3
valid_sources[0x66]	26578	1			T3	9		T8	7		T4	2
valid_sources[0x67]	9726	1			T3	3		T8	3		T4	3
valid_sources[0x68]	10287	1			T3	6		T8	3		T11	3
valid_sources[0x69]	10218	1			T3	6		T8	2		T4	3
valid_sources[0x6a]	11595	1			T3	6		T8	9		T10	2
valid_sources[0x6b]	9960	1			T3	10		T8	2		T4	2
valid_sources[0x6c]	72980	1			T3	7		T8	1		T4	1
valid_sources[0x6d]	10006	1			T3	9		T8	3		T4	2
valid_sources[0x6e]	10312	1			T3	8		T8	5		T4	4
valid_sources[0x6f]	11449	1			T3	7		T8	3		T4	4
valid_sources[0x70]	10388	1			T3	7		T8	4		T4	2
valid_sources[0x71]	9939	1			T3	8		T8	4		T4	3
valid_sources[0x72]	9742	1			T3	8		T8	6		T4	1
valid_sources[0x73]	9912	1			T3	5		T8	2		T10	1
valid_sources[0x74]	12734	1			T3	4		T8	4		T4	2
valid_sources[0x75]	10097	1			T3	3		T8	1		T4	3
valid_sources[0x76]	10246	1			T3	5		T8	7		T4	1
valid_sources[0x77]	10064	1			T3	5		T8	7		T4	1
valid_sources[0x78]	10078	1			T3	7		T8	8		T4	2
valid_sources[0x79]	12548	1			T3	3		T8	2		T9	3
valid_sources[0x7a]	11572	1			T3	9		T8	7		T10	2
valid_sources[0x7b]	16658	1			T3	6		T8	4		T4	1
valid_sources[0x7c]	12127	1			T3	7		T8	5		T4	2
valid_sources[0x7d]	11292	1			T3	6		T8	8		T4	2
valid_sources[0x7e]	10099	1			T3	8		T8	4		T4	1
valid_sources[0x7f]	26087	1			T3	4		T8	3		T11	3
valid_sources[0x80]	9950	1			T3	3		T8	6		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1454424

1

T3

486

T8

274

T9

11

values[0x0]

all_enables

biggest_size

148728

1

T3

294

T8

280

T9

4

values[0x1]

all_enables

biggest_size

147023

1

T3

290

T8

271

T9

4