Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101112170	14170	0	0
claim_transition_if_regwen_rd_A	101112170	1064	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101112170	14170	0	0
T34	379772	4	0	0
T35	37775	0	0	0
T41	20845	0	0	0
T43	0	2	0	0
T46	30250	0	0	0
T47	30625	0	0	0
T54	0	9	0	0
T86	2321	0	0	0
T88	0	9	0	0
T89	0	1	0	0
T93	0	2	0	0
T97	26361	0	0	0
T98	8682	0	0	0
T99	47588	0	0	0
T100	24194	0	0	0
T117	0	16	0	0
T150	0	8	0	0
T151	0	6	0	0
T152	0	11	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101112170	1064	0	0
T49	23465	0	0	0
T72	3377	0	0	0
T89	264703	2	0	0
T90	35852	0	0	0
T91	31131	0	0	0
T92	34095	0	0	0
T93	170041	0	0	0
T94	40113	0	0	0
T95	336053	0	0	0
T96	42728	0	0	0
T113	0	8	0	0
T119	0	35	0	0
T122	0	10	0	0
T127	0	2	0	0
T135	0	52	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	33	0	0
T156	0	57	0	0