Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.99	95.50	93.38	97.67	98.55	99.00	96.11

Total test records in report: 1002

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2379977263			Jun 26 04:39:41 PM PDT 24	Jun 26 04:39:46 PM PDT 24	105616760 ps
T1002	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1951518484			Jun 26 04:39:58 PM PDT 24	Jun 26 04:40:03 PM PDT 24	26569801 ps

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.2702201519
Short name	T7
Test name
Test status
Simulation time	986605894 ps
CPU time	6.82 seconds
Started	Jun 26 04:42:06 PM PDT 24
Finished	Jun 26 04:42:15 PM PDT 24
Peak memory	217708 kb
Host	smart-20a1497f-112e-4700-afe8-57eed6e549e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702201519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.2702201519
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.3869496143
Short name	T15
Test name
Test status
Simulation time	32430610366 ps
CPU time	162.14 seconds
Started	Jun 26 04:41:59 PM PDT 24
Finished	Jun 26 04:44:42 PM PDT 24
Peak memory	276152 kb
Host	smart-1f5f1b7e-c0dc-4a09-90bd-cd55a7791636
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869496143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.3869496143
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.2238575477
Short name	T33
Test name
Test status
Simulation time	1768125471 ps
CPU time	12.61 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:44 PM PDT 24
Peak memory	226308 kb
Host	smart-b76e6a73-ff3f-40d8-b3ca-72bc0158bffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238575477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2238575477
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2228222473
Short name	T34
Test name
Test status
Simulation time	50635135735 ps
CPU time	777.68 seconds
Started	Jun 26 04:41:31 PM PDT 24
Finished	Jun 26 04:54:32 PM PDT 24
Peak memory	316864 kb
Host	smart-6a336924-95cd-40a0-9b82-587b9db6269e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2228222473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2228222473
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.3464299042
Short name	T13
Test name
Test status
Simulation time	319967434 ps
CPU time	13.71 seconds
Started	Jun 26 04:42:39 PM PDT 24
Finished	Jun 26 04:42:55 PM PDT 24
Peak memory	226304 kb
Host	smart-5e3c1d56-415b-4fa0-aa2a-3eabb8e939aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464299042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3464299042
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.735004702
Short name	T121
Test name
Test status
Simulation time	51708866 ps
CPU time	2.38 seconds
Started	Jun 26 04:39:49 PM PDT 24
Finished	Jun 26 04:39:53 PM PDT 24
Peak memory	217328 kb
Host	smart-96e245a2-0fc8-455d-9678-6f0bd2c1aa62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735004 702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.735004702
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1568255570
Short name	T29
Test name
Test status
Simulation time	39265134 ps
CPU time	0.82 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:41:17 PM PDT 24
Peak memory	209128 kb
Host	smart-ec014ef8-5c81-4593-be0b-cbc2aa5b44af
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568255570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_volatile_unlock_smoke.1568255570
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.2738300467
Short name	T48
Test name
Test status
Simulation time	1254221185 ps
CPU time	38.34 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	270016 kb
Host	smart-a2bbc942-0b67-4107-a26f-70c1c141e959
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738300467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2738300467
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3346771604
Short name	T116
Test name
Test status
Simulation time	364402252 ps
CPU time	3.84 seconds
Started	Jun 26 04:39:53 PM PDT 24
Finished	Jun 26 04:39:59 PM PDT 24
Peak memory	221868 kb
Host	smart-68c01ebc-d0c2-4e31-8d8c-a837e67971bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346771604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.3346771604
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.2034719039
Short name	T107
Test name
Test status
Simulation time	446431129 ps
CPU time	9.95 seconds
Started	Jun 26 04:41:41 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	218592 kb
Host	smart-8af4369b-3096-493c-aa07-7ea35ec83f65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034719039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2034719039
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.850015198
Short name	T37
Test name
Test status
Simulation time	324460281 ps
CPU time	9.01 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:41:59 PM PDT 24
Peak memory	218488 kb
Host	smart-4d61763e-d957-4a10-b837-4bb9fc4e0a91
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850015198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.850015198
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.3374524317
Short name	T5
Test name
Test status
Simulation time	1278327184 ps
CPU time	7.62 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:43:22 PM PDT 24
Peak memory	217576 kb
Host	smart-dceec999-0556-4aa0-a153-655d9824fb34
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374524317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3374524317
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.886302404
Short name	T183
Test name
Test status
Simulation time	148437131 ps
CPU time	1.01 seconds
Started	Jun 26 04:39:53 PM PDT 24
Finished	Jun 26 04:39:56 PM PDT 24
Peak memory	208740 kb
Host	smart-2a2d87ed-9bb9-4b4d-a91c-3abe47acc973
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886302404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.886302404
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.3890405310
Short name	T70
Test name
Test status
Simulation time	35209886 ps
CPU time	1.02 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:40:48 PM PDT 24
Peak memory	209252 kb
Host	smart-cd858adc-9704-4936-83ac-b466e471374e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890405310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3890405310
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.19910339
Short name	T127
Test name
Test status
Simulation time	138058758 ps
CPU time	2.17 seconds
Started	Jun 26 04:39:18 PM PDT 24
Finished	Jun 26 04:39:21 PM PDT 24
Peak memory	217080 kb
Host	smart-cc52c248-47ec-465e-86ee-ede85fac2ead
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19910339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.19910339
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2613218513
Short name	T139
Test name
Test status
Simulation time	45784684 ps
CPU time	1.84 seconds
Started	Jun 26 04:39:13 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	221636 kb
Host	smart-a0d82398-124a-4c9e-8409-4152dd134f45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613218513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.2613218513
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.2657288193
Short name	T383
Test name
Test status
Simulation time	10091734210 ps
CPU time	83.01 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:43:12 PM PDT 24
Peak memory	251200 kb
Host	smart-69f4f991-2987-4937-b271-501eeaaa2cdc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657288193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.2657288193
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2887715840
Short name	T1
Test name
Test status
Simulation time	6932564129 ps
CPU time	57.4 seconds
Started	Jun 26 04:41:44 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	275764 kb
Host	smart-9ed2e932-8c6a-4fc0-a338-e746f6a61741
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887715840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.2887715840
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1453833294
Short name	T126
Test name
Test status
Simulation time	74116043 ps
CPU time	2.83 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	221920 kb
Host	smart-a3870888-90fa-4808-aafb-d97574c351bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453833294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.1453833294
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.892463254
Short name	T112
Test name
Test status
Simulation time	509939983 ps
CPU time	17.13 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:42:06 PM PDT 24
Peak memory	247212 kb
Host	smart-49212d7e-2d98-45a6-b814-78c8470af1c5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892463254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_ jtag_state_post_trans.892463254
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1619274415
Short name	T143
Test name
Test status
Simulation time	1479766192 ps
CPU time	5.25 seconds
Started	Jun 26 04:39:31 PM PDT 24
Finished	Jun 26 04:39:38 PM PDT 24
Peak memory	208892 kb
Host	smart-a60d4f78-3b40-4dec-b028-92f5e09841ea
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619274415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1619274415
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.562258557
Short name	T89
Test name
Test status
Simulation time	54020785953 ps
CPU time	463.67 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:49:56 PM PDT 24
Peak memory	529972 kb
Host	smart-a75c5b0e-0109-4a8a-a470-a02c69467bf2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=562258557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.562258557
Directory	/workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3233447123
Short name	T124
Test name
Test status
Simulation time	46328401 ps
CPU time	2.09 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:56 PM PDT 24
Peak memory	217124 kb
Host	smart-669bc76d-290d-4fbc-a6dc-5f527b7ddc65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233447123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3233447123
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1761659779
Short name	T134
Test name
Test status
Simulation time	120775628 ps
CPU time	3.23 seconds
Started	Jun 26 04:39:28 PM PDT 24
Finished	Jun 26 04:39:33 PM PDT 24
Peak memory	222136 kb
Host	smart-96c67b16-49ad-4bf5-bf1f-cbbe80174e80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761659779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.1761659779
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.2020644865
Short name	T199
Test name
Test status
Simulation time	32755986 ps
CPU time	0.79 seconds
Started	Jun 26 04:40:37 PM PDT 24
Finished	Jun 26 04:40:44 PM PDT 24
Peak memory	209232 kb
Host	smart-8ee583d3-67ea-45d2-9075-c25d19dfe77d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020644865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2020644865
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.1290497400
Short name	T198
Test name
Test status
Simulation time	37304850 ps
CPU time	0.83 seconds
Started	Jun 26 04:40:42 PM PDT 24
Finished	Jun 26 04:40:50 PM PDT 24
Peak memory	209136 kb
Host	smart-aa8ce1fd-df24-4207-9d5c-f3ec04401b90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290497400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1290497400
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.2101664145
Short name	T202
Test name
Test status
Simulation time	34497219 ps
CPU time	0.92 seconds
Started	Jun 26 04:40:47 PM PDT 24
Finished	Jun 26 04:40:55 PM PDT 24
Peak memory	209280 kb
Host	smart-b65d8aa7-d9ff-4f3a-8042-f16cabc8b26c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101664145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2101664145
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.164447284
Short name	T62
Test name
Test status
Simulation time	40916287 ps
CPU time	2.11 seconds
Started	Jun 26 04:40:37 PM PDT 24
Finished	Jun 26 04:40:46 PM PDT 24
Peak memory	214184 kb
Host	smart-ec9ee943-9ef3-4d29-9b8e-72e7a4f123ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164447284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.164447284
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3503607891
Short name	T119
Test name
Test status
Simulation time	65219077 ps
CPU time	1.94 seconds
Started	Jun 26 04:39:07 PM PDT 24
Finished	Jun 26 04:39:10 PM PDT 24
Peak memory	221236 kb
Host	smart-ad45166c-0e23-45fa-9434-be52d732413a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503607891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.3503607891
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2155119463
Short name	T131
Test name
Test status
Simulation time	1043828025 ps
CPU time	2.52 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:39:52 PM PDT 24
Peak memory	217292 kb
Host	smart-d9d0df46-4c16-4f8d-b3f6-d9ce8cecec8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155119463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.2155119463
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.658744667
Short name	T114
Test name
Test status
Simulation time	48342641 ps
CPU time	1.94 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	221624 kb
Host	smart-a0dbd21f-36b3-4f86-9ce7-bb3adc9b74fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658744667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_ err.658744667
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1482357822
Short name	T115
Test name
Test status
Simulation time	80082815 ps
CPU time	2.72 seconds
Started	Jun 26 04:39:56 PM PDT 24
Finished	Jun 26 04:40:01 PM PDT 24
Peak memory	221952 kb
Host	smart-036ffb28-fe3f-48c4-ae21-065a983b8046
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482357822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.1482357822
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.334535782
Short name	T142
Test name
Test status
Simulation time	234356630 ps
CPU time	2.56 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:56 PM PDT 24
Peak memory	217140 kb
Host	smart-646f7bdb-a810-446e-8642-1c089bd6fb95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334535782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_ err.334535782
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.448039108
Short name	T133
Test name
Test status
Simulation time	292103183 ps
CPU time	1.84 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:56 PM PDT 24
Peak memory	221652 kb
Host	smart-de1648d0-3915-403a-9dd3-3f2553aa8ab9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448039108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_ err.448039108
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.291449048
Short name	T136
Test name
Test status
Simulation time	62046367 ps
CPU time	2.67 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:40:01 PM PDT 24
Peak memory	217128 kb
Host	smart-df8665b5-b89e-4e7b-90cf-634c7ce4fd61
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291449048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_ err.291449048
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1312448421
Short name	T141
Test name
Test status
Simulation time	372819882 ps
CPU time	2.69 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:31 PM PDT 24
Peak memory	217160 kb
Host	smart-95920728-1778-478b-bb21-0e5a59c29215
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312448421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.1312448421
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1477451419
Short name	T140
Test name
Test status
Simulation time	206759929 ps
CPU time	3.08 seconds
Started	Jun 26 04:39:39 PM PDT 24
Finished	Jun 26 04:39:43 PM PDT 24
Peak memory	222040 kb
Host	smart-489a1ea8-97fb-4b00-94a5-f2912c4a9390
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477451419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.1477451419
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4145323829
Short name	T132
Test name
Test status
Simulation time	117032782 ps
CPU time	1.99 seconds
Started	Jun 26 04:39:49 PM PDT 24
Finished	Jun 26 04:39:52 PM PDT 24
Peak memory	221652 kb
Host	smart-4e16968f-b98d-40ba-a040-11271dd9e71f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145323829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.4145323829
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4217014394
Short name	T2
Test name
Test status
Simulation time	2182980199 ps
CPU time	14.21 seconds
Started	Jun 26 04:41:30 PM PDT 24
Finished	Jun 26 04:41:48 PM PDT 24
Peak memory	218516 kb
Host	smart-a98c0b4c-8c68-4f28-8d9f-5f65d9ac3b93
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217014394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_post_trans.4217014394
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2259840702
Short name	T904
Test name
Test status
Simulation time	32327601 ps
CPU time	1.71 seconds
Started	Jun 26 04:39:10 PM PDT 24
Finished	Jun 26 04:39:13 PM PDT 24
Peak memory	208924 kb
Host	smart-c11859ed-d113-4dd3-b924-529cfd630719
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259840702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.2259840702
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.348694047
Short name	T952
Test name
Test status
Simulation time	104431157 ps
CPU time	2.04 seconds
Started	Jun 26 04:39:08 PM PDT 24
Finished	Jun 26 04:39:12 PM PDT 24
Peak memory	208908 kb
Host	smart-3b61274c-8c40-4594-a7ff-7a52294ca201
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348694047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash .348694047
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2112994674
Short name	T902
Test name
Test status
Simulation time	52707291 ps
CPU time	0.91 seconds
Started	Jun 26 04:39:05 PM PDT 24
Finished	Jun 26 04:39:07 PM PDT 24
Peak memory	209360 kb
Host	smart-d0d37cd6-b851-4f1b-a033-47af8fa7d729
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112994674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.2112994674
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1997088014
Short name	T125
Test name
Test status
Simulation time	78962445 ps
CPU time	1.46 seconds
Started	Jun 26 04:39:09 PM PDT 24
Finished	Jun 26 04:39:12 PM PDT 24
Peak memory	217208 kb
Host	smart-332821d7-5502-4ac2-82dd-735f4023765d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997088014 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1997088014
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2890981949
Short name	T187
Test name
Test status
Simulation time	42517085 ps
CPU time	0.97 seconds
Started	Jun 26 04:39:08 PM PDT 24
Finished	Jun 26 04:39:10 PM PDT 24
Peak memory	208948 kb
Host	smart-1a5aa53a-b229-46e3-8a92-8ede42726d8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890981949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2890981949
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.589824192
Short name	T950
Test name
Test status
Simulation time	92098596 ps
CPU time	1.15 seconds
Started	Jun 26 04:39:09 PM PDT 24
Finished	Jun 26 04:39:12 PM PDT 24
Peak memory	208260 kb
Host	smart-de7cbdbc-c987-4761-a3c4-0f4fff37423c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589824192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.lc_ctrl_jtag_alert_test.589824192
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.241076647
Short name	T958
Test name
Test status
Simulation time	266650432 ps
CPU time	3.35 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	208604 kb
Host	smart-ac74b8c2-42aa-4fdb-863f-25b69160c888
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241076647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_aliasing.241076647
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3366683923
Short name	T878
Test name
Test status
Simulation time	566173894 ps
CPU time	6.48 seconds
Started	Jun 26 04:39:07 PM PDT 24
Finished	Jun 26 04:39:14 PM PDT 24
Peak memory	216696 kb
Host	smart-007d5cfa-c963-406b-ba36-6aacde7c7c13
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366683923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3366683923
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3557790574
Short name	T905
Test name
Test status
Simulation time	100532042 ps
CPU time	1.17 seconds
Started	Jun 26 04:39:07 PM PDT 24
Finished	Jun 26 04:39:09 PM PDT 24
Peak memory	208896 kb
Host	smart-054f42df-0d8d-4614-8531-2d1a0301dd95
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557790574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3557790574
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1121415802
Short name	T948
Test name
Test status
Simulation time	916348950 ps
CPU time	3.21 seconds
Started	Jun 26 04:39:05 PM PDT 24
Finished	Jun 26 04:39:09 PM PDT 24
Peak memory	221848 kb
Host	smart-98920ed6-3971-4fc4-990f-b5395469042e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112141 5802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1121415802
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3559100596
Short name	T874
Test name
Test status
Simulation time	65055814 ps
CPU time	1.94 seconds
Started	Jun 26 04:39:06 PM PDT 24
Finished	Jun 26 04:39:09 PM PDT 24
Peak memory	208896 kb
Host	smart-54bb4ee5-0697-44dc-87ce-d29001063e01
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559100596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.3559100596
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3784938374
Short name	T966
Test name
Test status
Simulation time	76317034 ps
CPU time	1.03 seconds
Started	Jun 26 04:39:08 PM PDT 24
Finished	Jun 26 04:39:10 PM PDT 24
Peak memory	217144 kb
Host	smart-35e868a2-42ab-41c2-97fd-b25476682ef6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784938374 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3784938374
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.925381242
Short name	T194
Test name
Test status
Simulation time	64767191 ps
CPU time	1.34 seconds
Started	Jun 26 04:39:09 PM PDT 24
Finished	Jun 26 04:39:12 PM PDT 24
Peak memory	208932 kb
Host	smart-88ccf897-e179-4623-9877-08d6c918e2c2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925381242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ same_csr_outstanding.925381242
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.58346184
Short name	T129
Test name
Test status
Simulation time	132287235 ps
CPU time	2.51 seconds
Started	Jun 26 04:39:08 PM PDT 24
Finished	Jun 26 04:39:13 PM PDT 24
Peak memory	217136 kb
Host	smart-01a6cf06-d2f4-45bd-8df9-874b574f39a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58346184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.58346184
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3312166698
Short name	T885
Test name
Test status
Simulation time	69179011 ps
CPU time	1.21 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	208960 kb
Host	smart-ecf91ef2-e80c-4dfd-b9b5-729a907eff0c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312166698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.3312166698
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1311402464
Short name	T884
Test name
Test status
Simulation time	57166119 ps
CPU time	1.38 seconds
Started	Jun 26 04:39:13 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	208936 kb
Host	smart-145607c8-e713-41ae-aecd-b561d96155e8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311402464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.1311402464
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2581468393
Short name	T973
Test name
Test status
Simulation time	63238139 ps
CPU time	1.07 seconds
Started	Jun 26 04:39:13 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	218944 kb
Host	smart-503b2b62-fbb1-45b3-8cbe-4cc52aff765b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581468393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese t.2581468393
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2484427296
Short name	T968
Test name
Test status
Simulation time	29387876 ps
CPU time	2.14 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:17 PM PDT 24
Peak memory	217248 kb
Host	smart-9567a675-1bfe-4143-8496-ce9517c5b409
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484427296 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2484427296
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1651220974
Short name	T954
Test name
Test status
Simulation time	17130782 ps
CPU time	1.12 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:14 PM PDT 24
Peak memory	208924 kb
Host	smart-470846f6-1569-4cd1-9fd2-a832fb759124
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651220974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1651220974
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2589577175
Short name	T923
Test name
Test status
Simulation time	199040799 ps
CPU time	1.46 seconds
Started	Jun 26 04:39:13 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	208788 kb
Host	smart-616ccde8-96ae-4bb8-958a-8b743297d279
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589577175 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2589577175
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2534178879
Short name	T887
Test name
Test status
Simulation time	3243674358 ps
CPU time	5.35 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:18 PM PDT 24
Peak memory	216972 kb
Host	smart-d4df0998-cfc8-4153-a58f-21281e719ac3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534178879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2534178879
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3371457373
Short name	T981
Test name
Test status
Simulation time	422812509 ps
CPU time	5.01 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:18 PM PDT 24
Peak memory	216772 kb
Host	smart-9f6b0d31-f5f4-48be-8b6d-5ef6e51efe9b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371457373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3371457373
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1871773015
Short name	T967
Test name
Test status
Simulation time	289604843 ps
CPU time	1.54 seconds
Started	Jun 26 04:39:09 PM PDT 24
Finished	Jun 26 04:39:12 PM PDT 24
Peak memory	217012 kb
Host	smart-65bca32e-7aa9-4b9b-afe9-a8134d7aa6e0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871773015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1871773015
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3713839934
Short name	T908
Test name
Test status
Simulation time	83870555 ps
CPU time	2.7 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:15 PM PDT 24
Peak memory	219644 kb
Host	smart-c3c6cb51-8ee1-457f-9f0f-9d829b7b60dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371383 9934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3713839934
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2145602600
Short name	T935
Test name
Test status
Simulation time	378863345 ps
CPU time	1.61 seconds
Started	Jun 26 04:39:08 PM PDT 24
Finished	Jun 26 04:39:11 PM PDT 24
Peak memory	208812 kb
Host	smart-bd55d6c1-d31a-49bf-b9e4-a3e4106c6d3e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145602600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.2145602600
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.610224322
Short name	T988
Test name
Test status
Simulation time	87249703 ps
CPU time	1.41 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	217116 kb
Host	smart-6733fcaf-2da0-4da4-8083-7c2f4445167f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610224322 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.610224322
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.249573376
Short name	T156
Test name
Test status
Simulation time	94302455 ps
CPU time	2.11 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:17 PM PDT 24
Peak memory	211092 kb
Host	smart-dea07caa-3376-4f31-a0d7-aa61abfacb9e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249573376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ same_csr_outstanding.249573376
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3559530173
Short name	T998
Test name
Test status
Simulation time	207913412 ps
CPU time	4.03 seconds
Started	Jun 26 04:39:12 PM PDT 24
Finished	Jun 26 04:39:17 PM PDT 24
Peak memory	217100 kb
Host	smart-fbc2ea1d-6abe-4e31-b82d-7716da68972d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559530173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3559530173
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2297076735
Short name	T160
Test name
Test status
Simulation time	25112690 ps
CPU time	1.19 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	217296 kb
Host	smart-ebbde0ce-9870-463f-a431-d049b8ccdae0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297076735 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2297076735
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1521796507
Short name	T991
Test name
Test status
Simulation time	22374325 ps
CPU time	0.9 seconds
Started	Jun 26 04:39:56 PM PDT 24
Finished	Jun 26 04:40:01 PM PDT 24
Peak memory	208948 kb
Host	smart-f49e4850-c8bb-4b33-a5b1-705c5b8bca6d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521796507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1521796507
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3193618909
Short name	T916
Test name
Test status
Simulation time	89058335 ps
CPU time	1.91 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:39:50 PM PDT 24
Peak memory	208948 kb
Host	smart-24eb603e-2e67-4b64-ab81-256216ba7d15
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193618909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.3193618909
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3381509188
Short name	T932
Test name
Test status
Simulation time	32636959 ps
CPU time	1.93 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:39:51 PM PDT 24
Peak memory	217080 kb
Host	smart-2669a3f2-6393-48ed-a12b-739488fcb8d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381509188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3381509188
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2327320065
Short name	T946
Test name
Test status
Simulation time	95476957 ps
CPU time	2.07 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	219140 kb
Host	smart-58fc7754-b87e-4851-b1c3-a407847e888f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327320065 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2327320065
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3459692479
Short name	T872
Test name
Test status
Simulation time	17009001 ps
CPU time	0.87 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:03 PM PDT 24
Peak memory	208948 kb
Host	smart-2e0b96fd-6eb7-4a9a-b019-f581ed0b7d15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459692479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3459692479
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1252075168
Short name	T193
Test name
Test status
Simulation time	36286973 ps
CPU time	1.29 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	217176 kb
Host	smart-8fafaea0-addd-4559-af63-82fddda8eced
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252075168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.1252075168
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4073198498
Short name	T997
Test name
Test status
Simulation time	140808117 ps
CPU time	3.2 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:58 PM PDT 24
Peak memory	217152 kb
Host	smart-764b3ff2-7931-4db8-abc1-ad48a479afaf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073198498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4073198498
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3986119987
Short name	T138
Test name
Test status
Simulation time	47214098 ps
CPU time	1.83 seconds
Started	Jun 26 04:39:50 PM PDT 24
Finished	Jun 26 04:39:54 PM PDT 24
Peak memory	221276 kb
Host	smart-400772b2-08bf-4294-b887-cdcf80a5b55f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986119987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.3986119987
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.7193477
Short name	T906
Test name
Test status
Simulation time	106548593 ps
CPU time	1.69 seconds
Started	Jun 26 04:39:54 PM PDT 24
Finished	Jun 26 04:39:58 PM PDT 24
Peak memory	218320 kb
Host	smart-2dfb930c-74ca-4d10-8a32-24f3c64cf6cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7193477 -assert nopostproc +UVM_TESTNAME=lc _ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.7193477
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1375324762
Short name	T886
Test name
Test status
Simulation time	40002596 ps
CPU time	0.98 seconds
Started	Jun 26 04:39:54 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	208612 kb
Host	smart-f9dad9e7-24ea-4bd6-ae42-31de885bb842
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375324762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1375324762
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4063469414
Short name	T910
Test name
Test status
Simulation time	47146051 ps
CPU time	2.07 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:40:00 PM PDT 24
Peak memory	217152 kb
Host	smart-cae7a8ce-2885-498b-ab95-bb75134de1b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063469414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.4063469414
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.463586460
Short name	T985
Test name
Test status
Simulation time	104406726 ps
CPU time	1.83 seconds
Started	Jun 26 04:39:53 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	217076 kb
Host	smart-7a958fd1-be9a-416c-8c64-c6a289e794a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463586460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.463586460
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3460339227
Short name	T130
Test name
Test status
Simulation time	129600586 ps
CPU time	1.86 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	217356 kb
Host	smart-90c52221-d872-43e8-8126-8e7a06538314
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460339227 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3460339227
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2750257564
Short name	T188
Test name
Test status
Simulation time	46155223 ps
CPU time	0.97 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	208964 kb
Host	smart-3fd2f0c8-556c-4e1c-bd6e-51380248d64f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750257564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2750257564
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.362984914
Short name	T936
Test name
Test status
Simulation time	15210005 ps
CPU time	1.17 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:39:59 PM PDT 24
Peak memory	209064 kb
Host	smart-aadfa817-a741-44a9-8cae-5e0b6ce6328a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362984914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _same_csr_outstanding.362984914
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1054453098
Short name	T898
Test name
Test status
Simulation time	437247075 ps
CPU time	2.07 seconds
Started	Jun 26 04:39:50 PM PDT 24
Finished	Jun 26 04:39:53 PM PDT 24
Peak memory	217116 kb
Host	smart-56ac8b44-2b6c-49d6-bb1b-4d1774e653ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054453098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1054453098
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1878345846
Short name	T939
Test name
Test status
Simulation time	21376132 ps
CPU time	1.11 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:54 PM PDT 24
Peak memory	217604 kb
Host	smart-f1ab339f-d68a-4ec9-94ae-f2ee676a7ddc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878345846 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1878345846
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.879267065
Short name	T994
Test name
Test status
Simulation time	33426864 ps
CPU time	1.31 seconds
Started	Jun 26 04:39:54 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	208980 kb
Host	smart-90b23485-9882-43db-b97d-9d90daa80d7f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879267065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _same_csr_outstanding.879267065
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3667141886
Short name	T926
Test name
Test status
Simulation time	155126633 ps
CPU time	2.59 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	218124 kb
Host	smart-42b06232-e355-494c-8747-248bbe5e1303
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667141886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3667141886
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1951518484
Short name	T1002
Test name
Test status
Simulation time	26569801 ps
CPU time	1.2 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:03 PM PDT 24
Peak memory	221492 kb
Host	smart-6f6cbae5-0bbc-4dd6-ac84-bfc94154c22c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951518484 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1951518484
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.140037620
Short name	T964
Test name
Test status
Simulation time	27319219 ps
CPU time	0.93 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:54 PM PDT 24
Peak memory	208968 kb
Host	smart-660e83f4-d13d-412a-a5a2-ea8d24672979
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140037620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.140037620
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.971712371
Short name	T191
Test name
Test status
Simulation time	82447372 ps
CPU time	1.06 seconds
Started	Jun 26 04:39:56 PM PDT 24
Finished	Jun 26 04:40:00 PM PDT 24
Peak memory	217188 kb
Host	smart-7acb4f58-57c6-4c46-9483-f8ac744d2fea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971712371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _same_csr_outstanding.971712371
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1779959464
Short name	T953
Test name
Test status
Simulation time	22212349 ps
CPU time	1.5 seconds
Started	Jun 26 04:39:54 PM PDT 24
Finished	Jun 26 04:39:57 PM PDT 24
Peak memory	217232 kb
Host	smart-1539474c-5055-4794-9b50-2798bf5b299f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779959464 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1779959464
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1851675456
Short name	T961
Test name
Test status
Simulation time	36513425 ps
CPU time	0.85 seconds
Started	Jun 26 04:39:52 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	208628 kb
Host	smart-321a8728-204e-4568-bddb-a09a89681584
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851675456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1851675456
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3251958035
Short name	T190
Test name
Test status
Simulation time	35585886 ps
CPU time	1.7 seconds
Started	Jun 26 04:39:51 PM PDT 24
Finished	Jun 26 04:39:55 PM PDT 24
Peak memory	208976 kb
Host	smart-4b5216e5-1afa-4bb2-90f1-4d8defb83724
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251958035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.3251958035
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4000733410
Short name	T927
Test name
Test status
Simulation time	332913264 ps
CPU time	3.65 seconds
Started	Jun 26 04:39:54 PM PDT 24
Finished	Jun 26 04:39:59 PM PDT 24
Peak memory	217196 kb
Host	smart-f5c4dda5-66c9-4b26-9d8d-58ed8d75a054
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000733410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4000733410
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2732980326
Short name	T122
Test name
Test status
Simulation time	102299601 ps
CPU time	1.41 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:03 PM PDT 24
Peak memory	217372 kb
Host	smart-62d2f92b-37de-4001-ac8b-ba772d1f1536
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732980326 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2732980326
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3631663649
Short name	T982
Test name
Test status
Simulation time	47100382 ps
CPU time	0.85 seconds
Started	Jun 26 04:39:57 PM PDT 24
Finished	Jun 26 04:40:01 PM PDT 24
Peak memory	208832 kb
Host	smart-b6a2a1ed-cc52-4632-9d16-923c2408bf99
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631663649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3631663649
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1807879855
Short name	T987
Test name
Test status
Simulation time	66455786 ps
CPU time	1.39 seconds
Started	Jun 26 04:39:57 PM PDT 24
Finished	Jun 26 04:40:03 PM PDT 24
Peak memory	208936 kb
Host	smart-e95c1acc-2cea-4b7d-92f1-dae9d1fa9af7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807879855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.1807879855
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1242645474
Short name	T979
Test name
Test status
Simulation time	131106058 ps
CPU time	2.98 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:40:00 PM PDT 24
Peak memory	217116 kb
Host	smart-3308e332-ee5c-496d-851d-1f1854891e32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242645474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1242645474
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.668185055
Short name	T911
Test name
Test status
Simulation time	55483057 ps
CPU time	1.7 seconds
Started	Jun 26 04:39:56 PM PDT 24
Finished	Jun 26 04:40:01 PM PDT 24
Peak memory	223908 kb
Host	smart-1f179bf2-ff9e-4183-a924-505ac06602e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668185055 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.668185055
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1441114492
Short name	T189
Test name
Test status
Simulation time	151097899 ps
CPU time	1.01 seconds
Started	Jun 26 04:39:57 PM PDT 24
Finished	Jun 26 04:40:02 PM PDT 24
Peak memory	208912 kb
Host	smart-b1c26467-66fa-4c8a-a59d-e5dae19edd12
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441114492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1441114492
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.709658591
Short name	T903
Test name
Test status
Simulation time	22192500 ps
CPU time	1.27 seconds
Started	Jun 26 04:39:57 PM PDT 24
Finished	Jun 26 04:40:02 PM PDT 24
Peak memory	217148 kb
Host	smart-62300af2-5557-401c-9e37-36e53def32b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709658591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _same_csr_outstanding.709658591
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2369180616
Short name	T955
Test name
Test status
Simulation time	140234583 ps
CPU time	3.49 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:05 PM PDT 24
Peak memory	217120 kb
Host	smart-82aab1c3-5f5a-4a91-aca8-51e0fe45c747
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369180616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2369180616
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1913641988
Short name	T203
Test name
Test status
Simulation time	808464935 ps
CPU time	2.71 seconds
Started	Jun 26 04:39:59 PM PDT 24
Finished	Jun 26 04:40:06 PM PDT 24
Peak memory	217152 kb
Host	smart-4ab83895-cfc6-40e2-8462-bc92a52dfb8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913641988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.1913641988
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3640173100
Short name	T999
Test name
Test status
Simulation time	123168739 ps
CPU time	2.16 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:05 PM PDT 24
Peak memory	217372 kb
Host	smart-416adea5-7dd5-4a07-90ea-9b85dc738e83
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640173100 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3640173100
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1457565823
Short name	T938
Test name
Test status
Simulation time	14840371 ps
CPU time	0.94 seconds
Started	Jun 26 04:39:58 PM PDT 24
Finished	Jun 26 04:40:04 PM PDT 24
Peak memory	209032 kb
Host	smart-dc3e6d50-f8cf-44ae-a6ac-68cd10b056c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457565823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1457565823
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.976843611
Short name	T155
Test name
Test status
Simulation time	48251759 ps
CPU time	1.46 seconds
Started	Jun 26 04:39:59 PM PDT 24
Finished	Jun 26 04:40:05 PM PDT 24
Peak memory	208960 kb
Host	smart-fa3e6b73-6922-49ff-8944-e1f1c7ae8c71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976843611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _same_csr_outstanding.976843611
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2483480107
Short name	T128
Test name
Test status
Simulation time	238890618 ps
CPU time	2.15 seconds
Started	Jun 26 04:39:59 PM PDT 24
Finished	Jun 26 04:40:06 PM PDT 24
Peak memory	217232 kb
Host	smart-ef665f80-98e3-4e7a-9934-1b5645a457ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483480107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2483480107
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3693493408
Short name	T986
Test name
Test status
Simulation time	17252346 ps
CPU time	1.02 seconds
Started	Jun 26 04:39:25 PM PDT 24
Finished	Jun 26 04:39:28 PM PDT 24
Peak memory	209036 kb
Host	smart-76d3bf08-bf07-483d-82a0-29ad322a9d5b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693493408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.3693493408
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3596517886
Short name	T944
Test name
Test status
Simulation time	41035225 ps
CPU time	1.81 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:30 PM PDT 24
Peak memory	208912 kb
Host	smart-c3acf062-2362-446c-9deb-55bebed39ae4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596517886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.3596517886
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1279877962
Short name	T881
Test name
Test status
Simulation time	100828126 ps
CPU time	1.22 seconds
Started	Jun 26 04:39:19 PM PDT 24
Finished	Jun 26 04:39:21 PM PDT 24
Peak memory	211096 kb
Host	smart-4b1c9a3b-c152-489b-a3f2-63d959406a60
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279877962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.1279877962
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1295260808
Short name	T921
Test name
Test status
Simulation time	228273677 ps
CPU time	1.83 seconds
Started	Jun 26 04:39:27 PM PDT 24
Finished	Jun 26 04:39:31 PM PDT 24
Peak memory	217264 kb
Host	smart-d81cfd6a-7738-46ff-8a9d-38a57510b0a7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295260808 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1295260808
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2503899691
Short name	T893
Test name
Test status
Simulation time	57229642 ps
CPU time	0.9 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:16 PM PDT 24
Peak memory	208792 kb
Host	smart-0f4232ed-18e6-4c6d-a69d-8e079d3ab581
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503899691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2503899691
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1589315096
Short name	T951
Test name
Test status
Simulation time	360618247 ps
CPU time	2.17 seconds
Started	Jun 26 04:39:18 PM PDT 24
Finished	Jun 26 04:39:21 PM PDT 24
Peak memory	208828 kb
Host	smart-60ff2f54-61d6-40b5-a8a6-813c26c01b5c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589315096 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1589315096
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1291728627
Short name	T914
Test name
Test status
Simulation time	1365280396 ps
CPU time	9.89 seconds
Started	Jun 26 04:39:19 PM PDT 24
Finished	Jun 26 04:39:29 PM PDT 24
Peak memory	208540 kb
Host	smart-a130ff16-dcd1-4dfa-9bdb-c8e8ecda3234
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291728627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1291728627
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4176973757
Short name	T892
Test name
Test status
Simulation time	3671046340 ps
CPU time	5.02 seconds
Started	Jun 26 04:39:17 PM PDT 24
Finished	Jun 26 04:39:24 PM PDT 24
Peak memory	208920 kb
Host	smart-0df0b22c-98ea-4f61-8636-f3a8d411b583
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176973757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4176973757
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1057264950
Short name	T147
Test name
Test status
Simulation time	159276293 ps
CPU time	1.5 seconds
Started	Jun 26 04:39:15 PM PDT 24
Finished	Jun 26 04:39:18 PM PDT 24
Peak memory	217096 kb
Host	smart-40725b0a-d07d-4bd3-ae0e-aa62fecd4712
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057264950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1057264950
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4193259784
Short name	T928
Test name
Test status
Simulation time	303757750 ps
CPU time	2.67 seconds
Started	Jun 26 04:39:17 PM PDT 24
Finished	Jun 26 04:39:21 PM PDT 24
Peak memory	218348 kb
Host	smart-ec6dfb91-cf3b-441a-a5cf-4c6ff88cd26b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419325 9784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4193259784
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4011849320
Short name	T920
Test name
Test status
Simulation time	42683115 ps
CPU time	1.35 seconds
Started	Jun 26 04:39:14 PM PDT 24
Finished	Jun 26 04:39:17 PM PDT 24
Peak memory	208944 kb
Host	smart-447ea03b-93be-42d8-87bb-91f172d48cfc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011849320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.4011849320
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3184649344
Short name	T990
Test name
Test status
Simulation time	19601858 ps
CPU time	1.22 seconds
Started	Jun 26 04:39:16 PM PDT 24
Finished	Jun 26 04:39:19 PM PDT 24
Peak memory	208968 kb
Host	smart-ecf99e34-f3b5-4e53-89ac-aee5a9192356
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184649344 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3184649344
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3282921580
Short name	T933
Test name
Test status
Simulation time	89927170 ps
CPU time	1.04 seconds
Started	Jun 26 04:39:25 PM PDT 24
Finished	Jun 26 04:39:28 PM PDT 24
Peak memory	208968 kb
Host	smart-c1ebd125-d117-4596-b4a4-fe6c3bccb16d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282921580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.3282921580
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.699197139
Short name	T978
Test name
Test status
Simulation time	45227502 ps
CPU time	2.45 seconds
Started	Jun 26 04:39:17 PM PDT 24
Finished	Jun 26 04:39:21 PM PDT 24
Peak memory	217172 kb
Host	smart-40e00eb9-4f56-4f91-89e8-65315512902a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699197139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e rr.699197139
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.374634104
Short name	T909
Test name
Test status
Simulation time	25247051 ps
CPU time	1.09 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:29 PM PDT 24
Peak memory	208956 kb
Host	smart-9e1d528a-e933-4ee2-b039-8d4ca0556c51
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374634104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing .374634104
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1088201642
Short name	T896
Test name
Test status
Simulation time	64734664 ps
CPU time	1.98 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:30 PM PDT 24
Peak memory	216860 kb
Host	smart-f254f38f-79b0-49f9-915c-d43f5f66bab3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088201642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.1088201642
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3851386747
Short name	T875
Test name
Test status
Simulation time	49255208 ps
CPU time	1.03 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:29 PM PDT 24
Peak memory	209252 kb
Host	smart-cf3cb796-f373-4d3b-9bbb-ff8c0d6c1b57
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851386747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.3851386747
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4145451523
Short name	T989
Test name
Test status
Simulation time	50075377 ps
CPU time	1.07 seconds
Started	Jun 26 04:39:35 PM PDT 24
Finished	Jun 26 04:39:37 PM PDT 24
Peak memory	217308 kb
Host	smart-36ca3eee-66ec-42dc-80eb-78780c0fe97f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145451523 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4145451523
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2941035922
Short name	T965
Test name
Test status
Simulation time	106872227 ps
CPU time	0.93 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:28 PM PDT 24
Peak memory	208660 kb
Host	smart-fc86cdc6-9835-466f-926d-963ab3e47ab7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941035922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2941035922
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.55793992
Short name	T913
Test name
Test status
Simulation time	129091440 ps
CPU time	1.45 seconds
Started	Jun 26 04:39:25 PM PDT 24
Finished	Jun 26 04:39:28 PM PDT 24
Peak memory	208788 kb
Host	smart-39e6d84c-760c-4c0a-b58e-0d6a3a39ce29
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55793992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_alert_test.55793992
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2520498780
Short name	T941
Test name
Test status
Simulation time	1683977488 ps
CPU time	4.61 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	208576 kb
Host	smart-47b9a669-6cc4-4fbf-a9a3-d56240510738
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520498780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2520498780
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1087102431
Short name	T149
Test name
Test status
Simulation time	9130448234 ps
CPU time	28.38 seconds
Started	Jun 26 04:39:28 PM PDT 24
Finished	Jun 26 04:39:58 PM PDT 24
Peak memory	208900 kb
Host	smart-fa838780-b83f-4429-b5ba-cde99009703f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087102431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1087102431
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3625418173
Short name	T148
Test name
Test status
Simulation time	1086094674 ps
CPU time	2.05 seconds
Started	Jun 26 04:39:28 PM PDT 24
Finished	Jun 26 04:39:31 PM PDT 24
Peak memory	210256 kb
Host	smart-c46e4a05-21f9-476a-98aa-ea45eb4d5a09
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625418173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3625418173
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3231488974
Short name	T924
Test name
Test status
Simulation time	238732580 ps
CPU time	2.78 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:30 PM PDT 24
Peak memory	220420 kb
Host	smart-fce6a21b-3e8e-423f-8cb2-ff9bfb612a92
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323148 8974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3231488974
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1818905273
Short name	T930
Test name
Test status
Simulation time	118503762 ps
CPU time	1.27 seconds
Started	Jun 26 04:39:26 PM PDT 24
Finished	Jun 26 04:39:29 PM PDT 24
Peak memory	208872 kb
Host	smart-8dcafea3-878b-4511-a8e8-e34afbc7bfe3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818905273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.1818905273
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.516948982
Short name	T192
Test name
Test status
Simulation time	143137876 ps
CPU time	1.78 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	209020 kb
Host	smart-9974c18c-e4f0-445d-8b75-5efd4010d1f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516948982 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.516948982
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.502188328
Short name	T942
Test name
Test status
Simulation time	41086724 ps
CPU time	1.35 seconds
Started	Jun 26 04:39:24 PM PDT 24
Finished	Jun 26 04:39:26 PM PDT 24
Peak memory	208936 kb
Host	smart-aa37bead-0d34-4bb2-95be-6e368f4d9972
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502188328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ same_csr_outstanding.502188328
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3453513316
Short name	T983
Test name
Test status
Simulation time	73219723 ps
CPU time	1.62 seconds
Started	Jun 26 04:39:27 PM PDT 24
Finished	Jun 26 04:39:30 PM PDT 24
Peak memory	217360 kb
Host	smart-74c7566f-bdc2-4c28-9a45-2da999b27540
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453513316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3453513316
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.126592987
Short name	T185
Test name
Test status
Simulation time	40094401 ps
CPU time	1.06 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	208980 kb
Host	smart-2aa34b37-acd3-4bc7-a11a-478f84a2e81d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126592987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing .126592987
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2065153363
Short name	T877
Test name
Test status
Simulation time	39205275 ps
CPU time	1.66 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	216880 kb
Host	smart-dfdb20d3-1510-4509-b321-8420bf9b4ddb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065153363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.2065153363
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3366380871
Short name	T184
Test name
Test status
Simulation time	66937469 ps
CPU time	1.27 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	217848 kb
Host	smart-258d1b39-83de-460f-9737-067be8b63308
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366380871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.3366380871
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1751466864
Short name	T159
Test name
Test status
Simulation time	41659717 ps
CPU time	1.41 seconds
Started	Jun 26 04:39:35 PM PDT 24
Finished	Jun 26 04:39:38 PM PDT 24
Peak memory	217232 kb
Host	smart-5e422ae2-c2d4-43d5-a529-b81293e99bf5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751466864 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1751466864
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2541679409
Short name	T876
Test name
Test status
Simulation time	55782349 ps
CPU time	1.14 seconds
Started	Jun 26 04:39:36 PM PDT 24
Finished	Jun 26 04:39:38 PM PDT 24
Peak memory	217168 kb
Host	smart-9f976b2b-71d1-49a8-9369-edcde033e8cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541679409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2541679409
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2449818609
Short name	T879
Test name
Test status
Simulation time	18312987 ps
CPU time	0.95 seconds
Started	Jun 26 04:39:35 PM PDT 24
Finished	Jun 26 04:39:37 PM PDT 24
Peak memory	208268 kb
Host	smart-85df5b47-8527-4986-b462-a33ea2ddfb5a
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449818609 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2449818609
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2837057931
Short name	T900
Test name
Test status
Simulation time	7697045826 ps
CPU time	8.59 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:39 PM PDT 24
Peak memory	208916 kb
Host	smart-2ffa1a8e-5526-409b-8b7e-31208244b5e5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837057931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2837057931
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.42835670
Short name	T977
Test name
Test status
Simulation time	200248945 ps
CPU time	2.48 seconds
Started	Jun 26 04:39:28 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	210340 kb
Host	smart-57eccaa5-a5a7-452d-95e1-de198df8a3e4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.42835670
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2887986139
Short name	T943
Test name
Test status
Simulation time	148819606 ps
CPU time	2.57 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:33 PM PDT 24
Peak memory	217204 kb
Host	smart-e7da0906-46eb-41d2-9dfa-e96da5d6425c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288798 6139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2887986139
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1872322776
Short name	T144
Test name
Test status
Simulation time	56876005 ps
CPU time	1.29 seconds
Started	Jun 26 04:39:30 PM PDT 24
Finished	Jun 26 04:39:32 PM PDT 24
Peak memory	208904 kb
Host	smart-46556904-0d44-4947-9c19-5f513fd50988
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872322776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.1872322776
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.515902518
Short name	T912
Test name
Test status
Simulation time	198320143 ps
CPU time	1.33 seconds
Started	Jun 26 04:39:35 PM PDT 24
Finished	Jun 26 04:39:37 PM PDT 24
Peak memory	217172 kb
Host	smart-f50d5ad0-7bd2-4a21-b1ee-cdeea577cee3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515902518 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.515902518
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1891362446
Short name	T929
Test name
Test status
Simulation time	46906337 ps
CPU time	2.01 seconds
Started	Jun 26 04:39:29 PM PDT 24
Finished	Jun 26 04:39:33 PM PDT 24
Peak memory	211056 kb
Host	smart-d917a003-0b2c-4b27-9129-f6a3717739ff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891362446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.1891362446
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3683039374
Short name	T980
Test name
Test status
Simulation time	342835683 ps
CPU time	4.38 seconds
Started	Jun 26 04:39:32 PM PDT 24
Finished	Jun 26 04:39:37 PM PDT 24
Peak memory	217076 kb
Host	smart-41164902-cba9-4d51-9003-234ccd8cfe12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683039374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3683039374
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1974040818
Short name	T894
Test name
Test status
Simulation time	123499014 ps
CPU time	1.17 seconds
Started	Jun 26 04:39:38 PM PDT 24
Finished	Jun 26 04:39:40 PM PDT 24
Peak memory	218332 kb
Host	smart-303c0988-abc8-4cc4-b3b4-efe1a1d96722
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974040818 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1974040818
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3107918575
Short name	T901
Test name
Test status
Simulation time	43095670 ps
CPU time	1.04 seconds
Started	Jun 26 04:39:36 PM PDT 24
Finished	Jun 26 04:39:39 PM PDT 24
Peak memory	208696 kb
Host	smart-13321960-bd03-4248-9aef-abd71e86219f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107918575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3107918575
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1740397688
Short name	T883
Test name
Test status
Simulation time	37935448 ps
CPU time	1.1 seconds
Started	Jun 26 04:39:37 PM PDT 24
Finished	Jun 26 04:39:39 PM PDT 24
Peak memory	208812 kb
Host	smart-17b13954-d5a6-407b-9ab6-eb6f8ec0112c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740397688 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1740397688
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.47409642
Short name	T937
Test name
Test status
Simulation time	416317865 ps
CPU time	9.46 seconds
Started	Jun 26 04:39:37 PM PDT 24
Finished	Jun 26 04:39:48 PM PDT 24
Peak memory	216748 kb
Host	smart-0cd07340-554c-4e05-b962-d9a8aec37436
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47409642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.lc_ctrl_jtag_csr_aliasing.47409642
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2879218
Short name	T949
Test name
Test status
Simulation time	11071779329 ps
CPU time	19.88 seconds
Started	Jun 26 04:39:31 PM PDT 24
Finished	Jun 26 04:39:52 PM PDT 24
Peak memory	208720 kb
Host	smart-e75482f1-6fdd-4653-9127-0be63d9440ba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base _test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2879218
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.510435342
Short name	T945
Test name
Test status
Simulation time	232860894 ps
CPU time	1.35 seconds
Started	Jun 26 04:39:31 PM PDT 24
Finished	Jun 26 04:39:33 PM PDT 24
Peak memory	210300 kb
Host	smart-64f02337-0822-4136-8e6e-c0ed27039d30
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510435342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.510435342
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4070985200
Short name	T907
Test name
Test status
Simulation time	293371287 ps
CPU time	2.18 seconds
Started	Jun 26 04:39:38 PM PDT 24
Finished	Jun 26 04:39:41 PM PDT 24
Peak memory	217260 kb
Host	smart-bbe35ed3-6234-4148-8cc7-0a4169da6ea2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407098 5200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4070985200
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.42127541
Short name	T972
Test name
Test status
Simulation time	36804062 ps
CPU time	1.09 seconds
Started	Jun 26 04:39:32 PM PDT 24
Finished	Jun 26 04:39:34 PM PDT 24
Peak memory	208804 kb
Host	smart-a0af6543-9fee-4306-97d4-6307500c8eb2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42127541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null - cm_name 5.lc_ctrl_jtag_csr_rw.42127541
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1263087694
Short name	T195
Test name
Test status
Simulation time	25537257 ps
CPU time	1.01 seconds
Started	Jun 26 04:39:36 PM PDT 24
Finished	Jun 26 04:39:39 PM PDT 24
Peak memory	208972 kb
Host	smart-0a90ed79-38e4-4a67-b3a3-e9efd90f21de
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263087694 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1263087694
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2102929892
Short name	T891
Test name
Test status
Simulation time	21660987 ps
CPU time	1.44 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	208972 kb
Host	smart-3fc7d8f5-09dd-4e1a-a122-2b939b8ab178
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102929892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2102929892
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2346837894
Short name	T123
Test name
Test status
Simulation time	134402972 ps
CPU time	2.57 seconds
Started	Jun 26 04:39:36 PM PDT 24
Finished	Jun 26 04:39:40 PM PDT 24
Peak memory	217116 kb
Host	smart-bd037ab0-68d5-44f6-a5fa-839e479ba92c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346837894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2346837894
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2837959886
Short name	T890
Test name
Test status
Simulation time	391172255 ps
CPU time	2 seconds
Started	Jun 26 04:39:38 PM PDT 24
Finished	Jun 26 04:39:41 PM PDT 24
Peak memory	221408 kb
Host	smart-79c8ad85-0b44-4fd4-be82-3aba84ae5318
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837959886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.2837959886
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1098630872
Short name	T1000
Test name
Test status
Simulation time	267699310 ps
CPU time	1.29 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	217244 kb
Host	smart-4627e923-8558-4d33-a6b6-b6b272f1c922
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098630872 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1098630872
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1235464011
Short name	T897
Test name
Test status
Simulation time	19516526 ps
CPU time	0.91 seconds
Started	Jun 26 04:39:43 PM PDT 24
Finished	Jun 26 04:39:45 PM PDT 24
Peak memory	208996 kb
Host	smart-f0925a7f-8cca-41f1-9b7b-18d2f75c7963
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235464011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1235464011
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2175785870
Short name	T922
Test name
Test status
Simulation time	37163987 ps
CPU time	1.55 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:45 PM PDT 24
Peak memory	208804 kb
Host	smart-31d260bf-68e8-4272-8525-b301a03c29a8
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175785870 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2175785870
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1080892114
Short name	T959
Test name
Test status
Simulation time	367631990 ps
CPU time	6 seconds
Started	Jun 26 04:39:40 PM PDT 24
Finished	Jun 26 04:39:47 PM PDT 24
Peak memory	208616 kb
Host	smart-4667cfbd-1bdf-434b-b387-73ee73e0a81a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080892114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1080892114
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4272596545
Short name	T962
Test name
Test status
Simulation time	770463274 ps
CPU time	5.49 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	208884 kb
Host	smart-16237ff0-b9c2-45b8-87fd-573a9923c22a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272596545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4272596545
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4140658475
Short name	T880
Test name
Test status
Simulation time	233038463 ps
CPU time	2 seconds
Started	Jun 26 04:39:40 PM PDT 24
Finished	Jun 26 04:39:43 PM PDT 24
Peak memory	208908 kb
Host	smart-0be739e9-5a75-4ff4-8fdd-6492361b59a2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140658475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4140658475
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3198225431
Short name	T145
Test name
Test status
Simulation time	150890530 ps
CPU time	1.66 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:43 PM PDT 24
Peak memory	217308 kb
Host	smart-096f5891-ed8b-46fa-9495-eaaa6b78b978
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319822 5431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3198225431
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1461693161
Short name	T992
Test name
Test status
Simulation time	53415075 ps
CPU time	1.28 seconds
Started	Jun 26 04:39:37 PM PDT 24
Finished	Jun 26 04:39:39 PM PDT 24
Peak memory	216936 kb
Host	smart-41a256a6-75db-48bd-92a3-af3eeb437edf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461693161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.1461693161
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2722904792
Short name	T899
Test name
Test status
Simulation time	15414940 ps
CPU time	1.02 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	208976 kb
Host	smart-82a74c05-0704-46be-997c-b571da2b5624
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722904792 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2722904792
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.580248642
Short name	T895
Test name
Test status
Simulation time	56296882 ps
CPU time	0.96 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	209084 kb
Host	smart-d2c979ef-2c16-439e-a623-9025e3f6079e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580248642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ same_csr_outstanding.580248642
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2379977263
Short name	T1001
Test name
Test status
Simulation time	105616760 ps
CPU time	3.42 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:46 PM PDT 24
Peak memory	217212 kb
Host	smart-d5fcaa6c-8469-40c5-89e9-793b96a92408
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379977263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2379977263
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1868478090
Short name	T137
Test name
Test status
Simulation time	239034979 ps
CPU time	2.29 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:45 PM PDT 24
Peak memory	217180 kb
Host	smart-9dfe2329-909e-41ef-9bda-6665b8162715
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868478090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.1868478090
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1742892961
Short name	T918
Test name
Test status
Simulation time	79187306 ps
CPU time	1.42 seconds
Started	Jun 26 04:39:39 PM PDT 24
Finished	Jun 26 04:39:42 PM PDT 24
Peak memory	217480 kb
Host	smart-5f0cb4ae-60eb-4de0-96be-48ed841eac4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742892961 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1742892961
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2855730374
Short name	T186
Test name
Test status
Simulation time	14887693 ps
CPU time	0.92 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	208784 kb
Host	smart-05a36419-1425-47a9-99d1-6cbe2773f7d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855730374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2855730374
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3205911576
Short name	T934
Test name
Test status
Simulation time	1259164109 ps
CPU time	1.55 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	208788 kb
Host	smart-83abd289-fe5a-46da-b4dd-bc7934dcdd0f
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205911576 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3205911576
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3728290216
Short name	T197
Test name
Test status
Simulation time	1624874520 ps
CPU time	3.89 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:47 PM PDT 24
Peak memory	208572 kb
Host	smart-8b3fc6e3-f24a-46ae-9bb4-d59d76b739d8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728290216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3728290216
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3156694966
Short name	T919
Test name
Test status
Simulation time	1374226404 ps
CPU time	31.36 seconds
Started	Jun 26 04:39:39 PM PDT 24
Finished	Jun 26 04:40:12 PM PDT 24
Peak memory	208572 kb
Host	smart-0a6d6838-fa39-49f5-9a8f-4fcf4d672fd0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156694966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3156694966
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.307978301
Short name	T873
Test name
Test status
Simulation time	398616013 ps
CPU time	2.96 seconds
Started	Jun 26 04:39:40 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	210560 kb
Host	smart-1cfb538b-9547-47fc-b971-9b3272c1b22a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307978301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.307978301
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1271105040
Short name	T976
Test name
Test status
Simulation time	240576740 ps
CPU time	1.42 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:45 PM PDT 24
Peak memory	217288 kb
Host	smart-0890f829-b9a2-435b-863e-57099d4aeb0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127110 5040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1271105040
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1063263396
Short name	T917
Test name
Test status
Simulation time	146975059 ps
CPU time	1.92 seconds
Started	Jun 26 04:39:43 PM PDT 24
Finished	Jun 26 04:39:47 PM PDT 24
Peak memory	208892 kb
Host	smart-65c04d8e-6d8b-46ec-ad29-8a39c84220f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063263396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.1063263396
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3819659630
Short name	T984
Test name
Test status
Simulation time	74530108 ps
CPU time	1.44 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:44 PM PDT 24
Peak memory	211016 kb
Host	smart-f2ebb76a-e8ec-44a0-b842-f71765df60d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819659630 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3819659630
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.512814281
Short name	T931
Test name
Test status
Simulation time	29690415 ps
CPU time	1.16 seconds
Started	Jun 26 04:39:40 PM PDT 24
Finished	Jun 26 04:39:43 PM PDT 24
Peak memory	208968 kb
Host	smart-fbffbd1a-099f-485c-af38-78b24b56793c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512814281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ same_csr_outstanding.512814281
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1105808644
Short name	T957
Test name
Test status
Simulation time	875629631 ps
CPU time	3.77 seconds
Started	Jun 26 04:39:41 PM PDT 24
Finished	Jun 26 04:39:46 PM PDT 24
Peak memory	217116 kb
Host	smart-f78502ad-b659-46f5-85aa-099ea3a98d70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105808644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1105808644
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.676690590
Short name	T888
Test name
Test status
Simulation time	47492027 ps
CPU time	1.67 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	219132 kb
Host	smart-e16752cc-d5e0-4cff-85ad-aac3cb7d2010
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676690590 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.676690590
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3698317302
Short name	T196
Test name
Test status
Simulation time	14550742 ps
CPU time	1.04 seconds
Started	Jun 26 04:39:45 PM PDT 24
Finished	Jun 26 04:39:48 PM PDT 24
Peak memory	208968 kb
Host	smart-6043b245-53af-4416-807c-51eadfc1bfb7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698317302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3698317302
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1737808666
Short name	T882
Test name
Test status
Simulation time	237629238 ps
CPU time	1.82 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:39:59 PM PDT 24
Peak memory	208792 kb
Host	smart-eaa00c9a-bf22-40b5-836d-9ded1f34b2c5
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737808666 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1737808666
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3084413738
Short name	T956
Test name
Test status
Simulation time	2745947397 ps
CPU time	12.1 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:40:00 PM PDT 24
Peak memory	208964 kb
Host	smart-4f8ad310-5c6b-4782-a31f-4e323040a416
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084413738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3084413738
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.375598106
Short name	T969
Test name
Test status
Simulation time	349145852 ps
CPU time	5.45 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:54 PM PDT 24
Peak memory	208868 kb
Host	smart-d843589a-aed3-419d-b5de-9eab3b7ab8c0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375598106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.375598106
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3965987411
Short name	T146
Test name
Test status
Simulation time	90305167 ps
CPU time	1.8 seconds
Started	Jun 26 04:39:42 PM PDT 24
Finished	Jun 26 04:39:45 PM PDT 24
Peak memory	210360 kb
Host	smart-d152c624-d2f5-4e60-86d3-52e01e3f6240
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965987411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3965987411
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1388455705
Short name	T947
Test name
Test status
Simulation time	102022314 ps
CPU time	3.25 seconds
Started	Jun 26 04:39:45 PM PDT 24
Finished	Jun 26 04:39:50 PM PDT 24
Peak memory	220428 kb
Host	smart-78e154af-a87f-4c39-8728-8bf02417e3d3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138845 5705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1388455705
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3403439344
Short name	T889
Test name
Test status
Simulation time	63417391 ps
CPU time	0.97 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:39:58 PM PDT 24
Peak memory	208880 kb
Host	smart-7a445694-af62-4f1b-8a9e-0e87de60954c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403439344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.3403439344
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3652261466
Short name	T940
Test name
Test status
Simulation time	47574635 ps
CPU time	1.29 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:39:50 PM PDT 24
Peak memory	208964 kb
Host	smart-1216f222-71b8-4ad0-b1b9-22dc9e23638b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652261466 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3652261466
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.797508171
Short name	T975
Test name
Test status
Simulation time	38069275 ps
CPU time	1.94 seconds
Started	Jun 26 04:39:45 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	217144 kb
Host	smart-354750d8-6ea8-4ee6-82b7-c8add3c6d44e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797508171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ same_csr_outstanding.797508171
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3770406803
Short name	T974
Test name
Test status
Simulation time	226145125 ps
CPU time	3.74 seconds
Started	Jun 26 04:39:44 PM PDT 24
Finished	Jun 26 04:39:50 PM PDT 24
Peak memory	217116 kb
Host	smart-895cfeb2-a0d7-4abd-a129-ea33528c8eb1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770406803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3770406803
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2220113381
Short name	T971
Test name
Test status
Simulation time	113333801 ps
CPU time	1.34 seconds
Started	Jun 26 04:39:55 PM PDT 24
Finished	Jun 26 04:39:59 PM PDT 24
Peak memory	217220 kb
Host	smart-1959518c-ae5a-41fc-a549-d605dd0da289
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220113381 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2220113381
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1656564022
Short name	T993
Test name
Test status
Simulation time	18738572 ps
CPU time	0.92 seconds
Started	Jun 26 04:39:45 PM PDT 24
Finished	Jun 26 04:39:47 PM PDT 24
Peak memory	208968 kb
Host	smart-2834fe4c-65b0-4c24-87cf-3a55c32522db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656564022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1656564022
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2393737655
Short name	T915
Test name
Test status
Simulation time	101433895 ps
CPU time	1.6 seconds
Started	Jun 26 04:39:49 PM PDT 24
Finished	Jun 26 04:39:52 PM PDT 24
Peak memory	208252 kb
Host	smart-9e979199-f9c2-40a2-88b7-1dccddec1b3c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393737655 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2393737655
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1246869194
Short name	T960
Test name
Test status
Simulation time	377042025 ps
CPU time	5.09 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:53 PM PDT 24
Peak memory	216664 kb
Host	smart-1888495f-6108-420f-99d1-14d9aa9d53ec
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246869194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1246869194
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.640238469
Short name	T995
Test name
Test status
Simulation time	3428076324 ps
CPU time	56.39 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:40:45 PM PDT 24
Peak memory	208924 kb
Host	smart-b8c73be0-8297-49f6-b411-fa3f9d7c638e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640238469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.640238469
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3433327977
Short name	T996
Test name
Test status
Simulation time	727157723 ps
CPU time	2.82 seconds
Started	Jun 26 04:39:53 PM PDT 24
Finished	Jun 26 04:39:58 PM PDT 24
Peak memory	210360 kb
Host	smart-2111d2eb-e2c4-4ca2-9e45-65b73cf81d9e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433327977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3433327977
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3876542286
Short name	T970
Test name
Test status
Simulation time	241302727 ps
CPU time	2.01 seconds
Started	Jun 26 04:39:49 PM PDT 24
Finished	Jun 26 04:39:53 PM PDT 24
Peak memory	208872 kb
Host	smart-b3557242-bbc4-4ac0-9bee-495333bfe44e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876542286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.3876542286
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2722988393
Short name	T963
Test name
Test status
Simulation time	26633388 ps
CPU time	1.14 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	208900 kb
Host	smart-f6b382f9-dbc0-457c-ac6f-1fa6567f456b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722988393 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2722988393
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1590715381
Short name	T925
Test name
Test status
Simulation time	128782999 ps
CPU time	1.4 seconds
Started	Jun 26 04:39:46 PM PDT 24
Finished	Jun 26 04:39:49 PM PDT 24
Peak memory	208972 kb
Host	smart-a5ab5f6a-f74c-4dda-9a7c-4819159b9c83
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590715381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.1590715381
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.749056947
Short name	T120
Test name
Test status
Simulation time	25064131 ps
CPU time	1.91 seconds
Started	Jun 26 04:39:45 PM PDT 24
Finished	Jun 26 04:39:48 PM PDT 24
Peak memory	218124 kb
Host	smart-0eac7c62-8689-436b-9c24-6ea6171190ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749056947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.749056947
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3500768422
Short name	T135
Test name
Test status
Simulation time	64988890 ps
CPU time	2.08 seconds
Started	Jun 26 04:39:47 PM PDT 24
Finished	Jun 26 04:39:51 PM PDT 24
Peak memory	221368 kb
Host	smart-1528e593-cbfe-443b-8259-4cd383a38288
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500768422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.3500768422
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.1482348708
Short name	T312
Test name
Test status
Simulation time	5586235881 ps
CPU time	12.16 seconds
Started	Jun 26 04:40:33 PM PDT 24
Finished	Jun 26 04:40:49 PM PDT 24
Peak memory	218676 kb
Host	smart-a8865f59-6ab2-4e35-9f6d-c6e85d8c9f51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482348708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1482348708
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.2415192839
Short name	T20
Test name
Test status
Simulation time	137222319 ps
CPU time	2.57 seconds
Started	Jun 26 04:40:35 PM PDT 24
Finished	Jun 26 04:40:44 PM PDT 24
Peak memory	217320 kb
Host	smart-6b3d8886-3bf1-4c22-8c07-0e4f6bd720f1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415192839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2415192839
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.572448232
Short name	T229
Test name
Test status
Simulation time	7410768885 ps
CPU time	57.06 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	226304 kb
Host	smart-b4e89d9f-692e-4609-ad94-0b4807bd214f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572448232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err ors.572448232
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.1318445063
Short name	T684
Test name
Test status
Simulation time	131971983 ps
CPU time	2.36 seconds
Started	Jun 26 04:40:35 PM PDT 24
Finished	Jun 26 04:40:43 PM PDT 24
Peak memory	218012 kb
Host	smart-b94b1858-2e36-44a1-a453-94513439e37f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318445063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1 318445063
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.4143815807
Short name	T323
Test name
Test status
Simulation time	88770961 ps
CPU time	2.56 seconds
Started	Jun 26 04:40:38 PM PDT 24
Finished	Jun 26 04:40:47 PM PDT 24
Peak memory	218472 kb
Host	smart-e97ee387-e943-4cae-9b5d-2d20ff837f8d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143815807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _prog_failure.4143815807
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2876413143
Short name	T681
Test name
Test status
Simulation time	9341204829 ps
CPU time	10.82 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	217920 kb
Host	smart-d67d6ec9-4c52-463a-ac84-c58dd29fef6e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876413143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_regwen_during_op.2876413143
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.2535807815
Short name	T828
Test name
Test status
Simulation time	218981550 ps
CPU time	3.89 seconds
Started	Jun 26 04:40:33 PM PDT 24
Finished	Jun 26 04:40:41 PM PDT 24
Peak memory	217908 kb
Host	smart-d37b7062-8487-4b54-b1e1-c09ccab6e3d0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535807815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 2535807815
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3323742036
Short name	T815
Test name
Test status
Simulation time	1819141110 ps
CPU time	41.98 seconds
Started	Jun 26 04:40:38 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	273424 kb
Host	smart-b62b910c-ab97-4a06-9049-d7b240c94772
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323742036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.3323742036
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2027408357
Short name	T344
Test name
Test status
Simulation time	584554119 ps
CPU time	14.6 seconds
Started	Jun 26 04:40:34 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	251152 kb
Host	smart-f7080f3f-141d-445e-bcf0-162ad7fe842b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027408357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.2027408357
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.3740943890
Short name	T386
Test name
Test status
Simulation time	45967238 ps
CPU time	2.77 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:40:46 PM PDT 24
Peak memory	218500 kb
Host	smart-62e2f97a-9f09-4b17-af21-cc4311adbe20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740943890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3740943890
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.1292447789
Short name	T594
Test name
Test status
Simulation time	1120531173 ps
CPU time	17.71 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:41:00 PM PDT 24
Peak memory	214456 kb
Host	smart-0a063632-b604-4107-88bf-c1038c51d960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292447789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1292447789
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.332996282
Short name	T102
Test name
Test status
Simulation time	341373407 ps
CPU time	38.69 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	284448 kb
Host	smart-ccbce171-c2b8-48f0-be4e-2f6cb21b361b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332996282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.332996282
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.3342802727
Short name	T289
Test name
Test status
Simulation time	1180526850 ps
CPU time	9.87 seconds
Started	Jun 26 04:40:34 PM PDT 24
Finished	Jun 26 04:40:47 PM PDT 24
Peak memory	226300 kb
Host	smart-5cf3d2ef-d010-40db-8e64-c728ea1b0c5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342802727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3342802727
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.807957469
Short name	T171
Test name
Test status
Simulation time	705500792 ps
CPU time	17.46 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:40:59 PM PDT 24
Peak memory	218476 kb
Host	smart-cc12de4a-b27b-45a3-a116-3223d117baf8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807957469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig est.807957469
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.3764379500
Short name	T481
Test name
Test status
Simulation time	1626331148 ps
CPU time	12.46 seconds
Started	Jun 26 04:40:34 PM PDT 24
Finished	Jun 26 04:40:50 PM PDT 24
Peak memory	218472 kb
Host	smart-021874d2-6afb-452b-b787-53ba50a0142c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764379500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3 764379500
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.546846036
Short name	T430
Test name
Test status
Simulation time	921174963 ps
CPU time	5.81 seconds
Started	Jun 26 04:40:32 PM PDT 24
Finished	Jun 26 04:40:40 PM PDT 24
Peak memory	224900 kb
Host	smart-aeb7ca57-2126-44a4-b05a-374329435d20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546846036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.546846036
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.204858003
Short name	T739
Test name
Test status
Simulation time	869951142 ps
CPU time	20.03 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:41:02 PM PDT 24
Peak memory	251312 kb
Host	smart-7ac562dd-382a-4d10-aa1a-6ebc531aa37d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204858003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.204858003
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.359803545
Short name	T266
Test name
Test status
Simulation time	171657920 ps
CPU time	4 seconds
Started	Jun 26 04:40:36 PM PDT 24
Finished	Jun 26 04:40:47 PM PDT 24
Peak memory	223204 kb
Host	smart-8e513216-2743-412d-bab8-84c084e616d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359803545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.359803545
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.3266373566
Short name	T104
Test name
Test status
Simulation time	23384910617 ps
CPU time	82.01 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	244916 kb
Host	smart-4eef4be9-b50b-4eb3-b9a9-01ecfaf042c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266373566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.3266373566
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1753502689
Short name	T223
Test name
Test status
Simulation time	26386409 ps
CPU time	0.8 seconds
Started	Jun 26 04:40:33 PM PDT 24
Finished	Jun 26 04:40:37 PM PDT 24
Peak memory	208288 kb
Host	smart-13d0b3b5-1e13-4920-892b-2a96827c3fb4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753502689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.1753502689
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.2510129928
Short name	T443
Test name
Test status
Simulation time	16541604 ps
CPU time	1.08 seconds
Started	Jun 26 04:40:41 PM PDT 24
Finished	Jun 26 04:40:49 PM PDT 24
Peak memory	209256 kb
Host	smart-e53aba38-b02e-4740-85de-8f5a82bdcf19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510129928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2510129928
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.4270281761
Short name	T322
Test name
Test status
Simulation time	659250008 ps
CPU time	14.61 seconds
Started	Jun 26 04:40:42 PM PDT 24
Finished	Jun 26 04:41:03 PM PDT 24
Peak memory	218520 kb
Host	smart-c6b6c036-2c2b-498b-9e7e-a1121236af39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270281761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4270281761
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.2236303347
Short name	T833
Test name
Test status
Simulation time	462031442 ps
CPU time	10.99 seconds
Started	Jun 26 04:40:45 PM PDT 24
Finished	Jun 26 04:41:02 PM PDT 24
Peak memory	217480 kb
Host	smart-cb8ea137-7a02-4c03-b434-1747351e7852
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236303347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2236303347
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.3583462096
Short name	T314
Test name
Test status
Simulation time	4807036675 ps
CPU time	36.71 seconds
Started	Jun 26 04:40:41 PM PDT 24
Finished	Jun 26 04:41:25 PM PDT 24
Peak memory	218952 kb
Host	smart-a6aa9a62-5cf6-4256-820a-5c31191fc5fb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583462096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.3583462096
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.3229935358
Short name	T482
Test name
Test status
Simulation time	1733666086 ps
CPU time	4.77 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:40:58 PM PDT 24
Peak memory	217988 kb
Host	smart-5f27de6d-2f19-40e5-ab83-dfe53ecfa0e9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229935358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3 229935358
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.701318799
Short name	T655
Test name
Test status
Simulation time	323944775 ps
CPU time	2.99 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:00 PM PDT 24
Peak memory	218448 kb
Host	smart-45206466-62b1-4fee-ad3f-be4d0bf06622
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701318799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ prog_failure.701318799
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3535798951
Short name	T823
Test name
Test status
Simulation time	1438840402 ps
CPU time	11.94 seconds
Started	Jun 26 04:40:42 PM PDT 24
Finished	Jun 26 04:41:01 PM PDT 24
Peak memory	217644 kb
Host	smart-2e662772-9161-4874-b966-721d6da66c66
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535798951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.3535798951
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.428299852
Short name	T678
Test name
Test status
Simulation time	460088988 ps
CPU time	7.54 seconds
Started	Jun 26 04:40:39 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	217872 kb
Host	smart-f50936f3-c8fb-4a5e-b784-a6abbc99918b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428299852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.428299852
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3070063243
Short name	T311
Test name
Test status
Simulation time	2007852262 ps
CPU time	66.09 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	267552 kb
Host	smart-8b650d2d-e7fe-45a1-b9ff-0046f4130959
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070063243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.3070063243
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.977493482
Short name	T831
Test name
Test status
Simulation time	1948356136 ps
CPU time	16.71 seconds
Started	Jun 26 04:40:41 PM PDT 24
Finished	Jun 26 04:41:05 PM PDT 24
Peak memory	251124 kb
Host	smart-10137609-7627-440c-ae8a-1c94928462e6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977493482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j tag_state_post_trans.977493482
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.576536485
Short name	T440
Test name
Test status
Simulation time	80364833 ps
CPU time	2.84 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:40:50 PM PDT 24
Peak memory	218528 kb
Host	smart-4f34026f-97bd-4d05-9940-f4b5651b5c0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576536485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.576536485
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.3206639677
Short name	T279
Test name
Test status
Simulation time	907540214 ps
CPU time	6.11 seconds
Started	Jun 26 04:40:42 PM PDT 24
Finished	Jun 26 04:40:55 PM PDT 24
Peak memory	214264 kb
Host	smart-5d26395c-929d-4852-9ea0-c5232b7033b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206639677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3206639677
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.1989955210
Short name	T50
Test name
Test status
Simulation time	245114041 ps
CPU time	25.67 seconds
Started	Jun 26 04:40:45 PM PDT 24
Finished	Jun 26 04:41:17 PM PDT 24
Peak memory	269836 kb
Host	smart-075c6886-4e05-4d9e-b92f-f211572869dd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989955210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1989955210
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.1287413603
Short name	T319
Test name
Test status
Simulation time	280258837 ps
CPU time	10.67 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:40:58 PM PDT 24
Peak memory	226344 kb
Host	smart-1c9d2b36-7e24-47f8-908c-8de7b43d6f80
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287413603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1287413603
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.1737429248
Short name	T591
Test name
Test status
Simulation time	5870102468 ps
CPU time	18.41 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:16 PM PDT 24
Peak memory	218488 kb
Host	smart-d4c086f6-8132-417a-8c26-7f21e592d4bf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737429248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.1737429248
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.493343867
Short name	T306
Test name
Test status
Simulation time	856112253 ps
CPU time	7.27 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	218412 kb
Host	smart-e663570a-829e-48c4-9a1e-653cd717ce03
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493343867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.493343867
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.337736284
Short name	T204
Test name
Test status
Simulation time	2267754643 ps
CPU time	9.09 seconds
Started	Jun 26 04:40:43 PM PDT 24
Finished	Jun 26 04:40:59 PM PDT 24
Peak memory	226016 kb
Host	smart-43c7cb07-2ca4-4b74-977d-9025b6605f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337736284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.337736284
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.860493290
Short name	T472
Test name
Test status
Simulation time	69641174 ps
CPU time	1.37 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	223128 kb
Host	smart-cdc3c0f2-0c37-4b57-9dd9-627c471c9806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860493290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.860493290
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.2164430021
Short name	T747
Test name
Test status
Simulation time	312178916 ps
CPU time	31.21 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	251188 kb
Host	smart-5ab00a39-6dfb-420f-b08a-cd15d0ef57a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164430021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2164430021
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.353512438
Short name	T777
Test name
Test status
Simulation time	1280343699 ps
CPU time	8.8 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	251228 kb
Host	smart-9a08d971-9308-478c-a4e2-6dc031015a2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353512438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.353512438
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.1458275040
Short name	T53
Test name
Test status
Simulation time	42597981581 ps
CPU time	135.1 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	271688 kb
Host	smart-090dbc47-2067-4ce2-be31-6a0a50e8d182
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458275040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.1458275040
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.588312160
Short name	T354
Test name
Test status
Simulation time	14149714 ps
CPU time	1.08 seconds
Started	Jun 26 04:40:41 PM PDT 24
Finished	Jun 26 04:40:49 PM PDT 24
Peak memory	212192 kb
Host	smart-5bb7c345-d2ce-4789-b64c-f4eaa17242e2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588312160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_volatile_unlock_smoke.588312160
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.4263325006
Short name	T814
Test name
Test status
Simulation time	17536212 ps
CPU time	0.92 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	209392 kb
Host	smart-e5bc1e3c-7392-4a62-b64d-f12b70ea616a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263325006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4263325006
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.2393619245
Short name	T772
Test name
Test status
Simulation time	281190921 ps
CPU time	13.13 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:38 PM PDT 24
Peak memory	218532 kb
Host	smart-2ba69e22-ea51-4a25-b30e-4e26af58f652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393619245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2393619245
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.2811129835
Short name	T508
Test name
Test status
Simulation time	816856876 ps
CPU time	17.8 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	217544 kb
Host	smart-36ab2c9c-701e-4486-9cbb-c4a5ec6e04ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811129835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2811129835
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.3387731511
Short name	T238
Test name
Test status
Simulation time	18835336924 ps
CPU time	56.12 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	220020 kb
Host	smart-11bb547e-790f-4c4a-bcae-6ec5142abb39
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387731511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e rrors.3387731511
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2237106045
Short name	T781
Test name
Test status
Simulation time	1705480604 ps
CPU time	12.23 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:38 PM PDT 24
Peak memory	218464 kb
Host	smart-ee901c6f-77fa-42f5-9010-3e2472d81b74
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237106045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.2237106045
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.2142659995
Short name	T63
Test name
Test status
Simulation time	291307973 ps
CPU time	2.01 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	217880 kb
Host	smart-8c4ff806-91fa-4795-b2f2-0f210977ea78
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142659995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke .2142659995
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.923505074
Short name	T822
Test name
Test status
Simulation time	807932426 ps
CPU time	24.95 seconds
Started	Jun 26 04:41:16 PM PDT 24
Finished	Jun 26 04:41:48 PM PDT 24
Peak memory	251144 kb
Host	smart-d9f3b665-4db0-456f-ad23-c55e0e54a77e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923505074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_state_failure.923505074
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4183777581
Short name	T686
Test name
Test status
Simulation time	903620600 ps
CPU time	13.74 seconds
Started	Jun 26 04:41:21 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	217768 kb
Host	smart-a37b2290-321a-4fdc-ac15-8347fe5c60a3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183777581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.4183777581
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.1532532350
Short name	T398
Test name
Test status
Simulation time	191493354 ps
CPU time	3.31 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	218528 kb
Host	smart-9c7a0b61-9abb-4a6f-9b1d-08337d71a5d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532532350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1532532350
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.2502892370
Short name	T331
Test name
Test status
Simulation time	368876179 ps
CPU time	15.33 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:39 PM PDT 24
Peak memory	226316 kb
Host	smart-081094b6-fe52-4147-890f-f332d2fb590a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502892370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2502892370
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.1354280821
Short name	T109
Test name
Test status
Simulation time	1587364246 ps
CPU time	13.97 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	218488 kb
Host	smart-cf0c7c4d-e0e9-4871-a47d-1f5087e4e3bd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354280821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d igest.1354280821
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.585212999
Short name	T367
Test name
Test status
Simulation time	180093028 ps
CPU time	5.43 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	218464 kb
Host	smart-07a35ddb-784c-426b-9c2c-2c08d8776cd3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585212999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.585212999
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.4004002075
Short name	T656
Test name
Test status
Simulation time	5118333117 ps
CPU time	11.49 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	218688 kb
Host	smart-73116e6a-353b-4e9b-b073-9cae28eba792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004002075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4004002075
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.3830661942
Short name	T335
Test name
Test status
Simulation time	125042896 ps
CPU time	5.79 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	218280 kb
Host	smart-983a3941-152b-472e-ad5c-974b3d848523
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830661942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3830661942
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.1422150967
Short name	T668
Test name
Test status
Simulation time	2348414363 ps
CPU time	32.62 seconds
Started	Jun 26 04:41:15 PM PDT 24
Finished	Jun 26 04:41:55 PM PDT 24
Peak memory	251372 kb
Host	smart-8380dd2b-f389-4db8-a285-9513b02febe5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422150967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1422150967
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.3426708178
Short name	T506
Test name
Test status
Simulation time	81866373 ps
CPU time	7.8 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	251232 kb
Host	smart-608c5b7e-f0ab-43e9-b7a8-3561d54ec79c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426708178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3426708178
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.3753996103
Short name	T835
Test name
Test status
Simulation time	10612106394 ps
CPU time	70 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	226320 kb
Host	smart-d3a73d03-bf90-48eb-8d02-665f567eafcc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753996103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.3753996103
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1640963998
Short name	T54
Test name
Test status
Simulation time	44041931754 ps
CPU time	613.54 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:51:37 PM PDT 24
Peak memory	283860 kb
Host	smart-9a847c74-3e36-430c-9489-46f4934a7335
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1640963998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1640963998
Directory	/workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2967195160
Short name	T64
Test name
Test status
Simulation time	31983361 ps
CPU time	1.3 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	213176 kb
Host	smart-2f921e3d-129e-49b4-b8ff-6997cd4a8325
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967195160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.2967195160
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.2892255723
Short name	T284
Test name
Test status
Simulation time	21060613 ps
CPU time	0.85 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	209264 kb
Host	smart-e691a3aa-f8cd-4e3f-af01-35cf989289b5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892255723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2892255723
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.3446075471
Short name	T728
Test name
Test status
Simulation time	2649583483 ps
CPU time	18.39 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	226408 kb
Host	smart-daa305bc-041f-411c-9c63-2c0533ca4e44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446075471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3446075471
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.1298880173
Short name	T749
Test name
Test status
Simulation time	1336566313 ps
CPU time	4.19 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	217536 kb
Host	smart-a0492887-eee0-44c8-b4d9-da8716c3c337
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298880173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1298880173
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.1382756905
Short name	T616
Test name
Test status
Simulation time	7507304000 ps
CPU time	53.53 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	218508 kb
Host	smart-a9619ad2-21bd-41e8-a29f-fb1ca2fcb5ec
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382756905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.1382756905
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1405573190
Short name	T486
Test name
Test status
Simulation time	428314567 ps
CPU time	6.28 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	218528 kb
Host	smart-cf50c098-0d47-4f31-aa2a-f94163930db7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405573190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_prog_failure.1405573190
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.2903268409
Short name	T166
Test name
Test status
Simulation time	111740030 ps
CPU time	1.37 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:25 PM PDT 24
Peak memory	217844 kb
Host	smart-a406a69c-72a4-42c8-9df8-029a510d4e94
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903268409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .2903268409
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1008438141
Short name	T687
Test name
Test status
Simulation time	5103351222 ps
CPU time	47.84 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	277284 kb
Host	smart-86412be4-8577-4033-82dd-113bb79f06d4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008438141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.1008438141
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.624625038
Short name	T841
Test name
Test status
Simulation time	408910039 ps
CPU time	7.76 seconds
Started	Jun 26 04:41:16 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	223348 kb
Host	smart-994bafc8-ab1b-412c-baf8-351d99e5b517
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624625038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ jtag_state_post_trans.624625038
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.3951609165
Short name	T738
Test name
Test status
Simulation time	277357980 ps
CPU time	2.97 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	218528 kb
Host	smart-cdc1ad20-410b-499a-b67d-1063ce9c4bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951609165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3951609165
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.3878344955
Short name	T464
Test name
Test status
Simulation time	1070919717 ps
CPU time	8.92 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	219196 kb
Host	smart-a86dadb9-1336-4f97-8c6d-9be573b8ef1d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878344955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3878344955
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.1238897967
Short name	T259
Test name
Test status
Simulation time	197275891 ps
CPU time	7.49 seconds
Started	Jun 26 04:41:23 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	218640 kb
Host	smart-33175d22-afe8-4e47-9c9f-7ae8718b2c67
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238897967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.1238897967
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.1702999644
Short name	T605
Test name
Test status
Simulation time	375474073 ps
CPU time	9.5 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	218548 kb
Host	smart-2714fb99-12b9-4277-9571-45068d2f64aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702999644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 1702999644
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.918315970
Short name	T404
Test name
Test status
Simulation time	589574828 ps
CPU time	10.97 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	226416 kb
Host	smart-477b0faf-c7ea-4274-864c-49ad1d16388e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918315970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.918315970
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.4272040238
Short name	T551
Test name
Test status
Simulation time	206180452 ps
CPU time	3.73 seconds
Started	Jun 26 04:41:21 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	217216 kb
Host	smart-3074d054-1130-40e8-81a7-01cf9f523c14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272040238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4272040238
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.1098073340
Short name	T863
Test name
Test status
Simulation time	1012150280 ps
CPU time	28.58 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	251208 kb
Host	smart-fc9d834f-e9dd-4517-b59a-5dccc9ee4ef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098073340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1098073340
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.1150502851
Short name	T332
Test name
Test status
Simulation time	42787159 ps
CPU time	2.97 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	226572 kb
Host	smart-312fffca-9fa7-4539-90a6-fc8ea8aabb29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150502851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1150502851
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.83210031
Short name	T850
Test name
Test status
Simulation time	5947231108 ps
CPU time	63.84 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	267672 kb
Host	smart-a536e20e-ff1d-4d2f-90d1-3619156bbb73
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83210031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.lc_ctrl_stress_all.83210031
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4117510867
Short name	T851
Test name
Test status
Simulation time	18852108 ps
CPU time	1.04 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	217952 kb
Host	smart-f8783baf-c4ae-45de-9563-0a9e926492c9
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117510867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_volatile_unlock_smoke.4117510867
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.668105314
Short name	T172
Test name
Test status
Simulation time	34536962 ps
CPU time	0.86 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:34 PM PDT 24
Peak memory	209276 kb
Host	smart-3d53e18b-f1a8-49d8-b9d9-b744f7f56c55
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668105314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.668105314
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.2370864139
Short name	T757
Test name
Test status
Simulation time	356479270 ps
CPU time	9.26 seconds
Started	Jun 26 04:41:22 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	218540 kb
Host	smart-cf24c8c8-89d7-43eb-b53e-27327732129e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370864139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2370864139
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.874226552
Short name	T702
Test name
Test status
Simulation time	366007276 ps
CPU time	5.39 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	217728 kb
Host	smart-ee964331-0ce0-4a83-89d4-158912c1c5e1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874226552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.874226552
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.728133513
Short name	T270
Test name
Test status
Simulation time	4683667502 ps
CPU time	20.73 seconds
Started	Jun 26 04:41:23 PM PDT 24
Finished	Jun 26 04:41:49 PM PDT 24
Peak memory	218528 kb
Host	smart-18d15155-ebc1-40d2-867e-43a5ce50a9b3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728133513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er rors.728133513
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3789140308
Short name	T474
Test name
Test status
Simulation time	169766622 ps
CPU time	4.06 seconds
Started	Jun 26 04:41:23 PM PDT 24
Finished	Jun 26 04:41:33 PM PDT 24
Peak memory	218460 kb
Host	smart-60afee68-52e7-454e-9711-6b9d852f870b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789140308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.3789140308
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.3337059434
Short name	T621
Test name
Test status
Simulation time	373268167 ps
CPU time	3.4 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	217860 kb
Host	smart-37b151d7-ed62-49f3-a90c-ede8b4edb0fb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337059434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .3337059434
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1594301831
Short name	T282
Test name
Test status
Simulation time	1025420654 ps
CPU time	42.49 seconds
Started	Jun 26 04:41:23 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	251176 kb
Host	smart-474e23b1-e9c9-4647-8edc-d6951aee1d95
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594301831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt ag_state_failure.1594301831
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2993861097
Short name	T358
Test name
Test status
Simulation time	721218144 ps
CPU time	11.89 seconds
Started	Jun 26 04:41:25 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	251468 kb
Host	smart-a3def617-b2cf-48f3-a2b2-36a20dca2b5e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993861097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.2993861097
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.1711555626
Short name	T232
Test name
Test status
Simulation time	626060004 ps
CPU time	3.27 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:33 PM PDT 24
Peak memory	218488 kb
Host	smart-617b4517-1537-44c6-94d9-7e2d644f130a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711555626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1711555626
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.3861684672
Short name	T225
Test name
Test status
Simulation time	397694906 ps
CPU time	18.21 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:48 PM PDT 24
Peak memory	226320 kb
Host	smart-fffe582a-54ac-401a-821d-d2ef380425fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861684672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3861684672
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.3245498165
Short name	T429
Test name
Test status
Simulation time	248383163 ps
CPU time	7.59 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	218540 kb
Host	smart-fad16ac4-db9b-4756-a04f-978aec51d85c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245498165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d igest.3245498165
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.2948867549
Short name	T567
Test name
Test status
Simulation time	935227747 ps
CPU time	10.83 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	218560 kb
Host	smart-a2833336-6276-471e-9269-e1b81dfb014b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948867549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 2948867549
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.906892616
Short name	T507
Test name
Test status
Simulation time	74133104 ps
CPU time	2.35 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	217952 kb
Host	smart-e86b059a-00ef-4a85-8642-78d98a289f1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=906892616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.906892616
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.4093764306
Short name	T214
Test name
Test status
Simulation time	1016936818 ps
CPU time	21.54 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	251200 kb
Host	smart-24dfeaef-9a08-419b-920d-615814ac62bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093764306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.4093764306
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.2649265089
Short name	T840
Test name
Test status
Simulation time	227111805 ps
CPU time	10.14 seconds
Started	Jun 26 04:41:30 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	251188 kb
Host	smart-386d72d5-467d-4034-8efb-c721e41f139a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649265089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2649265089
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.2746246228
Short name	T600
Test name
Test status
Simulation time	14159780501 ps
CPU time	103.62 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	284092 kb
Host	smart-837584d1-abfd-458c-bd9c-417f10110889
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746246228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.2746246228
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3204981692
Short name	T866
Test name
Test status
Simulation time	109576482 ps
CPU time	0.87 seconds
Started	Jun 26 04:41:24 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	212064 kb
Host	smart-c5379931-bbe0-4e70-b0dd-56e7fc648aa7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204981692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.3204981692
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.455211992
Short name	T548
Test name
Test status
Simulation time	77467035 ps
CPU time	0.96 seconds
Started	Jun 26 04:41:36 PM PDT 24
Finished	Jun 26 04:41:39 PM PDT 24
Peak memory	209236 kb
Host	smart-c8d23755-2773-4b4b-a684-99a402ce503b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455211992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.455211992
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.631269134
Short name	T712
Test name
Test status
Simulation time	202426310 ps
CPU time	10.19 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	218516 kb
Host	smart-17a6750b-a446-478b-91b6-0b6f2aed5db6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631269134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.631269134
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.2737484900
Short name	T6
Test name
Test status
Simulation time	640939107 ps
CPU time	3.43 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	217892 kb
Host	smart-c01a5d66-68e0-4666-bb95-2c16d421f63a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737484900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2737484900
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.1880063055
Short name	T812
Test name
Test status
Simulation time	6033608910 ps
CPU time	46.3 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	226304 kb
Host	smart-442fbbee-026b-41c8-9b45-a4d540e50906
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880063055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e rrors.1880063055
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1010146285
Short name	T700
Test name
Test status
Simulation time	864542781 ps
CPU time	7.17 seconds
Started	Jun 26 04:41:31 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	218484 kb
Host	smart-79a636ab-485b-4b05-94a8-9e4aeda33ae5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010146285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_prog_failure.1010146285
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.1300047045
Short name	T436
Test name
Test status
Simulation time	839548591 ps
CPU time	8.54 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	217964 kb
Host	smart-2609ab2e-729d-4eb7-a31a-1f5ba8f9540f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300047045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .1300047045
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1848300010
Short name	T524
Test name
Test status
Simulation time	2854303114 ps
CPU time	48.51 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	275800 kb
Host	smart-4df0fcbc-9c13-4778-b0e0-938ed4f24bb4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848300010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.1848300010
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.972660128
Short name	T449
Test name
Test status
Simulation time	134927990 ps
CPU time	1.95 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:34 PM PDT 24
Peak memory	218572 kb
Host	smart-2284c792-a03e-4ab0-93a0-8e994ee4f6df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=972660128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.972660128
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.2314615099
Short name	T299
Test name
Test status
Simulation time	235917997 ps
CPU time	11.68 seconds
Started	Jun 26 04:41:30 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	226312 kb
Host	smart-4bd7518d-a63a-478f-b472-e4b074996488
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314615099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2314615099
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.833353262
Short name	T230
Test name
Test status
Simulation time	655598808 ps
CPU time	9.29 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	218500 kb
Host	smart-4f623297-675f-405c-8097-bf7871dc9cdc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833353262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di gest.833353262
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.877318206
Short name	T699
Test name
Test status
Simulation time	585055714 ps
CPU time	10 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	226296 kb
Host	smart-6e217820-ee54-4210-a6ee-219b322e94e5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877318206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.877318206
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.4289305609
Short name	T618
Test name
Test status
Simulation time	263825312 ps
CPU time	7.03 seconds
Started	Jun 26 04:41:35 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	226316 kb
Host	smart-e0518b9b-3d9e-4b3d-a594-770bda1d9a7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289305609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4289305609
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.3442207009
Short name	T759
Test name
Test status
Simulation time	556795568 ps
CPU time	3.3 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	214904 kb
Host	smart-436c67c4-a84a-42c4-86d0-ba0e4d96ea5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442207009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3442207009
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.759038516
Short name	T722
Test name
Test status
Simulation time	123020960 ps
CPU time	14.69 seconds
Started	Jun 26 04:41:29 PM PDT 24
Finished	Jun 26 04:41:47 PM PDT 24
Peak memory	251312 kb
Host	smart-d4a3f87e-47b1-4f0f-a468-93d7fedb4f0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759038516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.759038516
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.2164890902
Short name	T791
Test name
Test status
Simulation time	308207900 ps
CPU time	7.34 seconds
Started	Jun 26 04:41:28 PM PDT 24
Finished	Jun 26 04:41:39 PM PDT 24
Peak memory	247676 kb
Host	smart-c0d6c4ac-7518-48d4-9ba4-39e2803ea77b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164890902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2164890902
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.1882034921
Short name	T453
Test name
Test status
Simulation time	19406328401 ps
CPU time	299.28 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:46:38 PM PDT 24
Peak memory	267644 kb
Host	smart-5547674e-b6b3-497f-8bc8-531dc47cc731
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882034921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.1882034921
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1930917012
Short name	T118
Test name
Test status
Simulation time	283944932282 ps
CPU time	8118.35 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 06:56:59 PM PDT 24
Peak memory	644620 kb
Host	smart-d02ab985-5e53-429a-a924-f080ce2e8b0b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1930917012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1930917012
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2345434803
Short name	T221
Test name
Test status
Simulation time	119848039 ps
CPU time	1.03 seconds
Started	Jun 26 04:41:32 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	212244 kb
Host	smart-efd4d68e-6506-46af-bd41-3e8fd4fe9195
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345434803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c trl_volatile_unlock_smoke.2345434803
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.90199536
Short name	T729
Test name
Test status
Simulation time	16550715 ps
CPU time	0.91 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	209276 kb
Host	smart-7cbb5b91-74e0-4f09-b3f8-effa70fa91fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90199536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.90199536
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.3610017573
Short name	T308
Test name
Test status
Simulation time	517537927 ps
CPU time	9 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 04:41:49 PM PDT 24
Peak memory	218528 kb
Host	smart-d779fd59-b62c-4efd-a734-133579be2e98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610017573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3610017573
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.1970690029
Short name	T573
Test name
Test status
Simulation time	1023747467 ps
CPU time	5.99 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	217552 kb
Host	smart-379a097a-ae3c-4e43-a633-fae8a985099d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970690029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1970690029
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.3044382280
Short name	T813
Test name
Test status
Simulation time	36820744622 ps
CPU time	34.41 seconds
Started	Jun 26 04:41:35 PM PDT 24
Finished	Jun 26 04:42:10 PM PDT 24
Peak memory	218956 kb
Host	smart-461f0a64-e06e-455f-99ea-e33698934632
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044382280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e rrors.3044382280
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.366965576
Short name	T701
Test name
Test status
Simulation time	686135567 ps
CPU time	2.41 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	218432 kb
Host	smart-167ff8d0-6247-485a-8245-7a9887916e07
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366965576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag _prog_failure.366965576
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.815133885
Short name	T18
Test name
Test status
Simulation time	379511925 ps
CPU time	12.39 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	217888 kb
Host	smart-1515fad6-3968-48a4-b5c8-5328e14bb1e3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815133885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke. 815133885
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.134942100
Short name	T859
Test name
Test status
Simulation time	3984507816 ps
CPU time	46.45 seconds
Started	Jun 26 04:41:36 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	269124 kb
Host	smart-622329e9-b7d8-45d0-8032-ecbd6c1962b4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134942100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_state_failure.134942100
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1389245831
Short name	T263
Test name
Test status
Simulation time	3005896396 ps
CPU time	10.49 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:51 PM PDT 24
Peak memory	250756 kb
Host	smart-b7caea57-4591-42b6-b810-c2e03c04ed0c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389245831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_state_post_trans.1389245831
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.2502686992
Short name	T504
Test name
Test status
Simulation time	84885038 ps
CPU time	3.76 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	218528 kb
Host	smart-b13eb902-29c9-4047-8129-ea07d1be32c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502686992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2502686992
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.4241232071
Short name	T162
Test name
Test status
Simulation time	3351321118 ps
CPU time	12.12 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	226500 kb
Host	smart-d6750124-0dea-4f36-a842-4f72baaea83a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241232071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4241232071
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.989278240
Short name	T165
Test name
Test status
Simulation time	362773935 ps
CPU time	12.06 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:41:51 PM PDT 24
Peak memory	218580 kb
Host	smart-7c711a8d-b731-413b-a967-c8836058f810
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989278240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di gest.989278240
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.510025533
Short name	T293
Test name
Test status
Simulation time	208924257 ps
CPU time	8.08 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:41:47 PM PDT 24
Peak memory	218384 kb
Host	smart-dbcca9d2-3266-44cd-9266-5907f01c1734
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510025533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.510025533
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.1665586874
Short name	T346
Test name
Test status
Simulation time	346269417 ps
CPU time	13.19 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:54 PM PDT 24
Peak memory	226352 kb
Host	smart-620bdf12-3051-4318-8fd3-ce90594489ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1665586874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1665586874
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.56714998
Short name	T709
Test name
Test status
Simulation time	27576424 ps
CPU time	1.82 seconds
Started	Jun 26 04:41:36 PM PDT 24
Finished	Jun 26 04:41:39 PM PDT 24
Peak memory	214232 kb
Host	smart-bad0a6d3-5ea9-4deb-83ac-f552304c2ead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56714998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.56714998
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.2145153292
Short name	T427
Test name
Test status
Simulation time	4093348216 ps
CPU time	30.51 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:42:11 PM PDT 24
Peak memory	251264 kb
Host	smart-298ff46b-8f5d-4911-bbc4-80ef9666f4a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145153292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2145153292
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.2943266300
Short name	T549
Test name
Test status
Simulation time	813826327 ps
CPU time	3.96 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	221876 kb
Host	smart-ad08d0b5-a28b-4bbe-9184-93f29ab9da23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943266300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2943266300
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.1367430936
Short name	T770
Test name
Test status
Simulation time	3291033871 ps
CPU time	37.94 seconds
Started	Jun 26 04:41:35 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	251276 kb
Host	smart-45d4d69a-54f5-4a78-8b98-30aff61a2345
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367430936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.1367430936
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1574465484
Short name	T572
Test name
Test status
Simulation time	23249097 ps
CPU time	0.93 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:42 PM PDT 24
Peak memory	212160 kb
Host	smart-8e72a541-35e4-48ff-8084-5efc19a5dfde
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574465484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.1574465484
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.3813338442
Short name	T585
Test name
Test status
Simulation time	21608779 ps
CPU time	1.21 seconds
Started	Jun 26 04:41:44 PM PDT 24
Finished	Jun 26 04:41:46 PM PDT 24
Peak memory	209320 kb
Host	smart-b725ae0a-e631-4439-a087-4a6b12c6385b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813338442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3813338442
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.1623691473
Short name	T664
Test name
Test status
Simulation time	615432836 ps
CPU time	10.92 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:55 PM PDT 24
Peak memory	226328 kb
Host	smart-32ec0d6f-9e6e-49d0-8651-3478ea091a53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623691473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1623691473
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.3415642040
Short name	T19
Test name
Test status
Simulation time	294089146 ps
CPU time	8.55 seconds
Started	Jun 26 04:41:44 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	217368 kb
Host	smart-d26d22a5-67d0-4598-a5a1-a0f61ae40687
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415642040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3415642040
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.126669374
Short name	T349
Test name
Test status
Simulation time	1084645942 ps
CPU time	35.36 seconds
Started	Jun 26 04:41:49 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	226376 kb
Host	smart-e8c5126c-dbe5-4b35-8be4-22d6d651ee98
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126669374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er rors.126669374
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1315688347
Short name	T682
Test name
Test status
Simulation time	682360338 ps
CPU time	9.05 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	223516 kb
Host	smart-07ff6a6d-d5ea-45fc-b5a0-24cb724e5e1e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315688347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.1315688347
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.93536917
Short name	T71
Test name
Test status
Simulation time	201801168 ps
CPU time	1.92 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:46 PM PDT 24
Peak memory	217876 kb
Host	smart-7ad4a52e-2521-47e9-97da-ab78e6366733
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93536917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.93536917
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1119193632
Short name	T715
Test name
Test status
Simulation time	2224330599 ps
CPU time	75.97 seconds
Started	Jun 26 04:41:42 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	267616 kb
Host	smart-78ff46ab-75b7-466a-8ad9-7193305a70ee
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119193632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.1119193632
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2194859468
Short name	T441
Test name
Test status
Simulation time	1644714611 ps
CPU time	14.24 seconds
Started	Jun 26 04:41:41 PM PDT 24
Finished	Jun 26 04:41:57 PM PDT 24
Peak memory	251024 kb
Host	smart-1786fc53-e4c1-4e7b-b349-3bd38a60ef6d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194859468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_state_post_trans.2194859468
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.2270102264
Short name	T846
Test name
Test status
Simulation time	212572438 ps
CPU time	3.55 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:48 PM PDT 24
Peak memory	218460 kb
Host	smart-78d95790-2605-4e9a-8abc-258570cc4d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270102264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2270102264
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.4133162152
Short name	T406
Test name
Test status
Simulation time	188527823 ps
CPU time	10.71 seconds
Started	Jun 26 04:41:42 PM PDT 24
Finished	Jun 26 04:41:54 PM PDT 24
Peak memory	226316 kb
Host	smart-48b3b285-1208-40a8-86f8-d3cb7fb168a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133162152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4133162152
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.1411939817
Short name	T368
Test name
Test status
Simulation time	1052097555 ps
CPU time	19.09 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	218464 kb
Host	smart-4f5f97b5-3958-4702-8e02-4a1a65fc60cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411939817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.1411939817
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.2015812691
Short name	T58
Test name
Test status
Simulation time	357090945 ps
CPU time	6.04 seconds
Started	Jun 26 04:41:45 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	226256 kb
Host	smart-350c18f5-8f9e-40e6-a728-7038c24164ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015812691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 2015812691
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.3629450970
Short name	T477
Test name
Test status
Simulation time	558628314 ps
CPU time	3.04 seconds
Started	Jun 26 04:41:39 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	214860 kb
Host	smart-5e2d0bd2-f7dd-4d77-a546-9e568ffbe2d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629450970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3629450970
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.4241362455
Short name	T689
Test name
Test status
Simulation time	279610645 ps
CPU time	28.63 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:42:07 PM PDT 24
Peak memory	251232 kb
Host	smart-de61d771-543d-42f8-b5fa-89df1d2fc8f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241362455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4241362455
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.1266495177
Short name	T654
Test name
Test status
Simulation time	1049840466 ps
CPU time	7.24 seconds
Started	Jun 26 04:41:37 PM PDT 24
Finished	Jun 26 04:41:46 PM PDT 24
Peak memory	251208 kb
Host	smart-988a80a2-c4ff-49c9-812d-695ed19fff69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266495177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1266495177
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.2584780823
Short name	T724
Test name
Test status
Simulation time	7547354782 ps
CPU time	101.98 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	226476 kb
Host	smart-7902a2c0-3109-4239-ab73-45bebe4c3501
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584780823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.2584780823
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4190576925
Short name	T838
Test name
Test status
Simulation time	38580719 ps
CPU time	0.99 seconds
Started	Jun 26 04:41:38 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	212216 kb
Host	smart-98584e7c-2478-47b8-be14-435d3a67b7db
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190576925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.4190576925
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.3436339773
Short name	T730
Test name
Test status
Simulation time	28173528 ps
CPU time	1.09 seconds
Started	Jun 26 04:41:55 PM PDT 24
Finished	Jun 26 04:41:57 PM PDT 24
Peak memory	209276 kb
Host	smart-f68b3f00-8b6c-41a6-bf2c-1b1d8d445304
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436339773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3436339773
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.3001579227
Short name	T856
Test name
Test status
Simulation time	2104025742 ps
CPU time	9.88 seconds
Started	Jun 26 04:41:46 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	226320 kb
Host	smart-7df043b8-76e5-4122-b1fa-a3b4e40d940e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001579227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3001579227
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.3873604091
Short name	T491
Test name
Test status
Simulation time	667476310 ps
CPU time	2.92 seconds
Started	Jun 26 04:41:46 PM PDT 24
Finished	Jun 26 04:41:49 PM PDT 24
Peak memory	217296 kb
Host	smart-d34e358f-0255-42df-88c8-af9eb03a6b53
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873604091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3873604091
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.652557994
Short name	T576
Test name
Test status
Simulation time	2491949039 ps
CPU time	25.95 seconds
Started	Jun 26 04:41:42 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	219332 kb
Host	smart-60d56cc9-2119-416e-a7b0-e29967b8dd10
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652557994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er rors.652557994
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.688559454
Short name	T396
Test name
Test status
Simulation time	583572038 ps
CPU time	2.91 seconds
Started	Jun 26 04:41:42 PM PDT 24
Finished	Jun 26 04:41:46 PM PDT 24
Peak memory	218472 kb
Host	smart-88a62755-37b2-4eac-b6a6-5c999fecbc2d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688559454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag _prog_failure.688559454
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.1124942146
Short name	T76
Test name
Test status
Simulation time	134123407 ps
CPU time	1.64 seconds
Started	Jun 26 04:41:49 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	217464 kb
Host	smart-24b06190-6950-410f-9155-a8bf8294481c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124942146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .1124942146
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.46368624
Short name	T763
Test name
Test status
Simulation time	496416484 ps
CPU time	11.67 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	250388 kb
Host	smart-0ca9f39d-e82a-4e5b-ba93-f3f954892c7f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46368624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_j tag_state_post_trans.46368624
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.2242118596
Short name	T390
Test name
Test status
Simulation time	101057420 ps
CPU time	3.37 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:41:51 PM PDT 24
Peak memory	222944 kb
Host	smart-d1e0352f-bfcd-47c6-838e-399ae5bf065b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242118596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2242118596
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.3663041710
Short name	T455
Test name
Test status
Simulation time	1484764332 ps
CPU time	10.82 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:41:59 PM PDT 24
Peak memory	226332 kb
Host	smart-19946428-4588-41b2-9019-da471e33805d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663041710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3663041710
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.90156921
Short name	T641
Test name
Test status
Simulation time	268947053 ps
CPU time	12.39 seconds
Started	Jun 26 04:41:44 PM PDT 24
Finished	Jun 26 04:41:58 PM PDT 24
Peak memory	218528 kb
Host	smart-3c1cdb57-ce17-409a-95e1-da798cf7fcea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90156921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig est.90156921
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.2136839370
Short name	T847
Test name
Test status
Simulation time	1663086986 ps
CPU time	9.38 seconds
Started	Jun 26 04:41:46 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	218480 kb
Host	smart-aa86acc1-ed19-4cea-83cc-9930ede53195
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136839370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 2136839370
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.1566649516
Short name	T769
Test name
Test status
Simulation time	540290691 ps
CPU time	6.36 seconds
Started	Jun 26 04:41:41 PM PDT 24
Finished	Jun 26 04:41:48 PM PDT 24
Peak memory	218592 kb
Host	smart-41981901-0c07-4917-82be-806f08864297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566649516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1566649516
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.534379428
Short name	T81
Test name
Test status
Simulation time	189712763 ps
CPU time	3.61 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	218040 kb
Host	smart-55dd327b-0990-424d-a3a5-e86c4b31ecef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534379428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.534379428
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.562617905
Short name	T10
Test name
Test status
Simulation time	458228963 ps
CPU time	25.37 seconds
Started	Jun 26 04:41:42 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	251232 kb
Host	smart-9bbcbe86-3b84-412d-9a7e-709833d65ecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562617905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.562617905
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.112254143
Short name	T566
Test name
Test status
Simulation time	86622433 ps
CPU time	7.7 seconds
Started	Jun 26 04:41:43 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	251232 kb
Host	smart-349ee873-4a0a-4f1e-a7d0-41eaf1f34c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112254143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.112254143
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3715438580
Short name	T742
Test name
Test status
Simulation time	22962406285 ps
CPU time	485.4 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:49:55 PM PDT 24
Peak memory	373332 kb
Host	smart-9178cb48-27b1-4510-ba32-95122c94356e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3715438580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3715438580
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1255321544
Short name	T869
Test name
Test status
Simulation time	58600617 ps
CPU time	0.88 seconds
Started	Jun 26 04:41:41 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	212092 kb
Host	smart-ef6270d4-c6e8-4723-a506-b5934aa946e0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255321544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.1255321544
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.4080281611
Short name	T714
Test name
Test status
Simulation time	75737121 ps
CPU time	1.19 seconds
Started	Jun 26 04:41:51 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	209348 kb
Host	smart-be0a7741-a8e8-41b5-9eb6-bb0c99623ca2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080281611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4080281611
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.359625569
Short name	T615
Test name
Test status
Simulation time	360360800 ps
CPU time	12.55 seconds
Started	Jun 26 04:41:50 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	218604 kb
Host	smart-097f469e-6292-4395-8bb4-6db10bf847de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359625569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.359625569
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.3201383229
Short name	T418
Test name
Test status
Simulation time	670168583 ps
CPU time	2.6 seconds
Started	Jun 26 04:41:52 PM PDT 24
Finished	Jun 26 04:41:55 PM PDT 24
Peak memory	217332 kb
Host	smart-b70867ef-99c9-40c3-9ce6-3972df4aa2db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201383229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3201383229
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.1793638299
Short name	T547
Test name
Test status
Simulation time	9482993951 ps
CPU time	51.27 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	219068 kb
Host	smart-fffdb59b-44e3-49c2-af71-dc1a2b287487
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793638299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e rrors.1793638299
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1922556227
Short name	T352
Test name
Test status
Simulation time	870772304 ps
CPU time	6.74 seconds
Started	Jun 26 04:41:50 PM PDT 24
Finished	Jun 26 04:41:57 PM PDT 24
Peak memory	218492 kb
Host	smart-11a33fb9-e569-423e-8d0f-4e5c08abbf75
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922556227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.1922556227
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.2225850333
Short name	T619
Test name
Test status
Simulation time	387149488 ps
CPU time	2.45 seconds
Started	Jun 26 04:41:50 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	217872 kb
Host	smart-7858b671-9063-4024-8d5d-1bb3fad95600
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225850333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke .2225850333
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1512541189
Short name	T794
Test name
Test status
Simulation time	3945776661 ps
CPU time	36.69 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	251648 kb
Host	smart-fa8e79a0-2dc7-49f8-8d6b-d56f98b12221
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512541189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.1512541189
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.1794272732
Short name	T519
Test name
Test status
Simulation time	491304351 ps
CPU time	3.7 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	222736 kb
Host	smart-d14460a0-04e0-4327-98ad-2b8f766d0c77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794272732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1794272732
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.1897650908
Short name	T602
Test name
Test status
Simulation time	790359413 ps
CPU time	13.26 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	219204 kb
Host	smart-66f79041-2bf9-470f-9deb-f0a477807554
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897650908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1897650908
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.1288717325
Short name	T274
Test name
Test status
Simulation time	703490739 ps
CPU time	14.93 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:42:10 PM PDT 24
Peak memory	218500 kb
Host	smart-a69d907d-df70-4778-82c2-da1a6f6eaafc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288717325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.1288717325
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.1669166831
Short name	T494
Test name
Test status
Simulation time	426674969 ps
CPU time	15.34 seconds
Started	Jun 26 04:41:55 PM PDT 24
Finished	Jun 26 04:42:11 PM PDT 24
Peak memory	218596 kb
Host	smart-33706c66-4189-4c10-96a0-9713e8bf2b32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669166831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1669166831
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.1103900162
Short name	T760
Test name
Test status
Simulation time	67735330 ps
CPU time	1.48 seconds
Started	Jun 26 04:41:50 PM PDT 24
Finished	Jun 26 04:41:53 PM PDT 24
Peak memory	217964 kb
Host	smart-003e4eb2-c93d-4d3c-802a-4ee1ce18aeea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103900162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1103900162
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.2263514428
Short name	T8
Test name
Test status
Simulation time	333178059 ps
CPU time	28.38 seconds
Started	Jun 26 04:41:49 PM PDT 24
Finished	Jun 26 04:42:19 PM PDT 24
Peak memory	251232 kb
Host	smart-764e4f4e-e758-440a-9265-cee1168fcc07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263514428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2263514428
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.1362054296
Short name	T432
Test name
Test status
Simulation time	90345232 ps
CPU time	8.03 seconds
Started	Jun 26 04:41:47 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	244024 kb
Host	smart-0db8dcd5-9523-44ed-bd59-4451d4229741
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362054296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1362054296
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.419143508
Short name	T448
Test name
Test status
Simulation time	3554957163 ps
CPU time	36.75 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	251260 kb
Host	smart-1bfbbfc9-37ad-496e-9d52-3ed55ebb3aa8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419143508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.419143508
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2627107710
Short name	T31
Test name
Test status
Simulation time	19014169 ps
CPU time	0.94 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	209356 kb
Host	smart-a9d6f0bd-64f6-4b64-a2dc-673faccb9e51
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627107710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.2627107710
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.3357072755
Short name	T496
Test name
Test status
Simulation time	29194036 ps
CPU time	1.35 seconds
Started	Jun 26 04:41:58 PM PDT 24
Finished	Jun 26 04:42:00 PM PDT 24
Peak memory	209292 kb
Host	smart-870458e3-0c2b-4e71-a696-e48c1c92ba34
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357072755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3357072755
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.411472635
Short name	T294
Test name
Test status
Simulation time	807401398 ps
CPU time	20.58 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	226320 kb
Host	smart-d16014d4-7193-4419-8349-522a4d77f7c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411472635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.411472635
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.3132860221
Short name	T679
Test name
Test status
Simulation time	407646796 ps
CPU time	3.31 seconds
Started	Jun 26 04:41:59 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	217552 kb
Host	smart-834040de-4dbd-4bd8-b38b-357e67fc242a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132860221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3132860221
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.1022209577
Short name	T359
Test name
Test status
Simulation time	23603598092 ps
CPU time	63.45 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:43:01 PM PDT 24
Peak memory	219404 kb
Host	smart-10d6c778-731d-4bc2-bfb1-9d7f8cd6ff0b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022209577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.1022209577
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.127989449
Short name	T861
Test name
Test status
Simulation time	5583601144 ps
CPU time	11.2 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	226432 kb
Host	smart-7cbbf6d1-5749-4609-a7c0-178865d81e6e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127989449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag _prog_failure.127989449
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.2117822216
Short name	T83
Test name
Test status
Simulation time	404973655 ps
CPU time	2.01 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:41:59 PM PDT 24
Peak memory	217852 kb
Host	smart-298c3473-c24a-4e92-8948-e83e482d6e24
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117822216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .2117822216
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.780869720
Short name	T685
Test name
Test status
Simulation time	4866699823 ps
CPU time	55.41 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:54 PM PDT 24
Peak memory	275916 kb
Host	smart-84a35ac3-5699-409f-b0b5-a40c7ac00ee6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780869720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_state_failure.780869720
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1661576992
Short name	T639
Test name
Test status
Simulation time	3227931945 ps
CPU time	18.56 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	251208 kb
Host	smart-3a2c26c3-9ab1-475c-a0d6-b83123e7ef24
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661576992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.1661576992
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.3486722574
Short name	T558
Test name
Test status
Simulation time	1125511018 ps
CPU time	2.71 seconds
Started	Jun 26 04:41:57 PM PDT 24
Finished	Jun 26 04:42:01 PM PDT 24
Peak memory	218520 kb
Host	smart-b9354789-1287-4ac6-829b-e1c8057700b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486722574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3486722574
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.2553825581
Short name	T511
Test name
Test status
Simulation time	1681743372 ps
CPU time	13.77 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	226344 kb
Host	smart-10e7bb49-4ffe-4490-82cb-2f84b478c2f6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553825581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2553825581
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.3439606789
Short name	T560
Test name
Test status
Simulation time	238625962 ps
CPU time	6.86 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	218500 kb
Host	smart-ab8650ab-df29-42b5-814c-510dbeaec037
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439606789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.3439606789
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.2386199864
Short name	T665
Test name
Test status
Simulation time	214265423 ps
CPU time	8.39 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:42:04 PM PDT 24
Peak memory	226280 kb
Host	smart-62d80684-0130-45f6-b2e1-e30fc8a1ffaa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386199864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux. 2386199864
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.4108148820
Short name	T52
Test name
Test status
Simulation time	381385275 ps
CPU time	9.9 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	218604 kb
Host	smart-d8b5c14c-c9d7-492e-84f1-e430aac7787b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108148820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4108148820
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.3723382754
Short name	T234
Test name
Test status
Simulation time	66760819 ps
CPU time	2.42 seconds
Started	Jun 26 04:41:50 PM PDT 24
Finished	Jun 26 04:41:54 PM PDT 24
Peak memory	218040 kb
Host	smart-f509c79f-511e-41a0-a049-d8079dca74e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723382754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3723382754
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.640786585
Short name	T209
Test name
Test status
Simulation time	285153624 ps
CPU time	30.94 seconds
Started	Jun 26 04:41:48 PM PDT 24
Finished	Jun 26 04:42:20 PM PDT 24
Peak memory	251324 kb
Host	smart-620bfc95-212c-4abc-895f-75d71ccdc011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640786585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.640786585
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.2490552197
Short name	T672
Test name
Test status
Simulation time	325828310 ps
CPU time	4.19 seconds
Started	Jun 26 04:41:59 PM PDT 24
Finished	Jun 26 04:42:04 PM PDT 24
Peak memory	222616 kb
Host	smart-321efd36-2a08-433e-ab8c-f9c596885495
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490552197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2490552197
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1919978191
Short name	T252
Test name
Test status
Simulation time	52276219 ps
CPU time	0.94 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:41:56 PM PDT 24
Peak memory	209192 kb
Host	smart-3f442448-30aa-4ec0-8a7b-145e4334c3da
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919978191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.1919978191
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.1501249179
Short name	T694
Test name
Test status
Simulation time	50552926 ps
CPU time	1 seconds
Started	Jun 26 04:42:05 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	209368 kb
Host	smart-d5d6bcf7-014a-425c-afe9-0f0e8e50a561
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501249179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1501249179
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.2626742323
Short name	T550
Test name
Test status
Simulation time	379345049 ps
CPU time	16.45 seconds
Started	Jun 26 04:41:54 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	226332 kb
Host	smart-da8cf8e4-d505-48b0-a930-e040a88e78a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626742323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2626742323
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.498348032
Short name	T25
Test name
Test status
Simulation time	2986089693 ps
CPU time	16.89 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	217956 kb
Host	smart-70120369-2e85-4b4d-8707-ab5916dd540f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498348032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.498348032
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.1300236087
Short name	T525
Test name
Test status
Simulation time	7901068616 ps
CPU time	55.72 seconds
Started	Jun 26 04:42:05 PM PDT 24
Finished	Jun 26 04:43:03 PM PDT 24
Peak memory	219208 kb
Host	smart-9c53d414-cc16-46d4-a8f5-3d81133b4f57
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300236087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.1300236087
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1834318724
Short name	T606
Test name
Test status
Simulation time	3459986178 ps
CPU time	11.72 seconds
Started	Jun 26 04:41:59 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	218460 kb
Host	smart-a2ee564a-6c46-4aab-9986-b63b5c4f1cbb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834318724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.1834318724
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.3675411976
Short name	T318
Test name
Test status
Simulation time	741356363 ps
CPU time	6.08 seconds
Started	Jun 26 04:41:57 PM PDT 24
Finished	Jun 26 04:42:05 PM PDT 24
Peak memory	217884 kb
Host	smart-fa0f84d3-d11a-426d-921a-19d71671be1a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675411976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .3675411976
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.903343945
Short name	T683
Test name
Test status
Simulation time	3974690923 ps
CPU time	126.51 seconds
Started	Jun 26 04:42:00 PM PDT 24
Finished	Jun 26 04:44:08 PM PDT 24
Peak memory	283840 kb
Host	smart-565b29b3-12e6-46ae-88cc-ecfbeb0122f0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903343945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_state_failure.903343945
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2912663662
Short name	T385
Test name
Test status
Simulation time	320851164 ps
CPU time	11.15 seconds
Started	Jun 26 04:41:59 PM PDT 24
Finished	Jun 26 04:42:11 PM PDT 24
Peak memory	226552 kb
Host	smart-42968380-02b8-43fe-a743-448e3fce2648
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912663662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.2912663662
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.4067576354
Short name	T737
Test name
Test status
Simulation time	80367946 ps
CPU time	1.66 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:00 PM PDT 24
Peak memory	218560 kb
Host	smart-6e9ce2b6-07e1-47b7-bec1-926b45773b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067576354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4067576354
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.3811430552
Short name	T297
Test name
Test status
Simulation time	244871638 ps
CPU time	11.53 seconds
Started	Jun 26 04:41:57 PM PDT 24
Finished	Jun 26 04:42:10 PM PDT 24
Peak memory	226348 kb
Host	smart-65f50531-a11a-44cc-8daa-420f24a18128
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811430552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3811430552
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.531707277
Short name	T660
Test name
Test status
Simulation time	273066355 ps
CPU time	11.53 seconds
Started	Jun 26 04:42:05 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	218484 kb
Host	smart-2db8af52-56ed-4185-8abe-e16f8489606a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531707277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di gest.531707277
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.4055765869
Short name	T330
Test name
Test status
Simulation time	227778894 ps
CPU time	7.89 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:11 PM PDT 24
Peak memory	226284 kb
Host	smart-b93c4e22-4c25-4af3-91b5-f98bb17e8254
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055765869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 4055765869
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.2678935425
Short name	T726
Test name
Test status
Simulation time	238533613 ps
CPU time	9.24 seconds
Started	Jun 26 04:41:56 PM PDT 24
Finished	Jun 26 04:42:07 PM PDT 24
Peak memory	218764 kb
Host	smart-e18b8653-0396-4eb1-ba1f-d12f5730a463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678935425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2678935425
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.1886427904
Short name	T254
Test name
Test status
Simulation time	64775529 ps
CPU time	1.19 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	217940 kb
Host	smart-285a3382-04aa-47be-ab0e-38e18e6f3b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886427904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1886427904
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.1767718020
Short name	T588
Test name
Test status
Simulation time	246080870 ps
CPU time	28.74 seconds
Started	Jun 26 04:41:57 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	246592 kb
Host	smart-487bc790-0312-496f-8777-493b8911ac19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767718020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1767718020
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.2459331638
Short name	T565
Test name
Test status
Simulation time	437521274 ps
CPU time	6.1 seconds
Started	Jun 26 04:41:58 PM PDT 24
Finished	Jun 26 04:42:05 PM PDT 24
Peak memory	247240 kb
Host	smart-01c2cecc-f6b1-42b7-a1ad-2b7b195b89e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459331638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2459331638
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3955682864
Short name	T538
Test name
Test status
Simulation time	313102155321 ps
CPU time	2451.86 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 05:22:55 PM PDT 24
Peak memory	947456 kb
Host	smart-742bae23-27af-4eeb-b58c-dbb2c968bf12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3955682864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3955682864
Directory	/workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2832631744
Short name	T84
Test name
Test status
Simulation time	23198714 ps
CPU time	1.04 seconds
Started	Jun 26 04:41:55 PM PDT 24
Finished	Jun 26 04:41:58 PM PDT 24
Peak memory	218096 kb
Host	smart-1aa20abc-a8bc-4981-b88f-f7881ad8076c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832631744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.2832631744
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.1978475741
Short name	T517
Test name
Test status
Simulation time	48032082 ps
CPU time	1.02 seconds
Started	Jun 26 04:40:49 PM PDT 24
Finished	Jun 26 04:40:57 PM PDT 24
Peak memory	209300 kb
Host	smart-a9ecbc07-dcc2-4119-8cd0-1f0c46e3095b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978475741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1978475741
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.1908642760
Short name	T336
Test name
Test status
Simulation time	347780118 ps
CPU time	15.64 seconds
Started	Jun 26 04:40:41 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	218520 kb
Host	smart-5f30fc25-528b-4b86-b330-7661a0616cde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908642760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1908642760
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.1156637892
Short name	T792
Test name
Test status
Simulation time	521081530 ps
CPU time	3.95 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:40:57 PM PDT 24
Peak memory	217404 kb
Host	smart-741226e7-0982-4e0c-91e4-d1af3e0519f3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156637892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1156637892
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.483077182
Short name	T290
Test name
Test status
Simulation time	18825120678 ps
CPU time	64.78 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:41:58 PM PDT 24
Peak memory	226316 kb
Host	smart-d4f99e49-03d9-4f8e-aae9-bbb21ec196bc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483077182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err ors.483077182
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.210816652
Short name	T278
Test name
Test status
Simulation time	318936708 ps
CPU time	6.82 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	217904 kb
Host	smart-f13170a9-7612-4fdf-8058-03467c79af26
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210816652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.210816652
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2170046356
Short name	T403
Test name
Test status
Simulation time	481015493 ps
CPU time	4.74 seconds
Started	Jun 26 04:40:49 PM PDT 24
Finished	Jun 26 04:41:00 PM PDT 24
Peak memory	223104 kb
Host	smart-008cbf8f-6022-4624-8c63-5db6baa11937
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170046356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.2170046356
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2929981086
Short name	T273
Test name
Test status
Simulation time	11311316830 ps
CPU time	27.24 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	217944 kb
Host	smart-bb9c86a6-5e69-47b4-844a-6a124cda47f8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929981086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.2929981086
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.1728429574
Short name	T677
Test name
Test status
Simulation time	425418903 ps
CPU time	1.92 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:40:57 PM PDT 24
Peak memory	217888 kb
Host	smart-39fef922-390f-40ff-a32c-5a289a276627
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728429574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 1728429574
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.908776380
Short name	T647
Test name
Test status
Simulation time	2215813144 ps
CPU time	41.44 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	275848 kb
Host	smart-1a599aaa-9b9a-49ae-ac3c-88a7f88b3371
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908776380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _state_failure.908776380
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2652059110
Short name	T325
Test name
Test status
Simulation time	303151096 ps
CPU time	9.94 seconds
Started	Jun 26 04:40:49 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	246744 kb
Host	smart-a1b2ccac-0dae-4b42-81dd-9450bd961cb2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652059110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.2652059110
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.3419473633
Short name	T830
Test name
Test status
Simulation time	309659719 ps
CPU time	1.94 seconds
Started	Jun 26 04:40:46 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	222336 kb
Host	smart-ddd56e53-6ac5-4110-a0b1-59177d085ad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419473633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3419473633
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.367220478
Short name	T773
Test name
Test status
Simulation time	1433933667 ps
CPU time	20.14 seconds
Started	Jun 26 04:40:49 PM PDT 24
Finished	Jun 26 04:41:16 PM PDT 24
Peak memory	218032 kb
Host	smart-1a177447-7aa9-470f-81ff-f9efa959ceae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367220478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.367220478
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.959782916
Short name	T42
Test name
Test status
Simulation time	281005690 ps
CPU time	9.71 seconds
Started	Jun 26 04:40:54 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	218520 kb
Host	smart-473751a4-9c41-4416-aedc-a31eff70a458
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959782916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.959782916
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.2099405758
Short name	T832
Test name
Test status
Simulation time	1069356963 ps
CPU time	8.71 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	218500 kb
Host	smart-041de9c6-ee9f-4cb1-9815-53d01088427e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099405758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di gest.2099405758
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.177330807
Short name	T864
Test name
Test status
Simulation time	2725714216 ps
CPU time	15.56 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	218544 kb
Host	smart-46caa6ba-445c-4dbc-ac22-0bc32eec2b5b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177330807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.177330807
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.826087378
Short name	T3
Test name
Test status
Simulation time	458833863 ps
CPU time	9.5 seconds
Started	Jun 26 04:40:47 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	226336 kb
Host	smart-0a4b088f-0232-4582-89b8-d6184ef71b5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826087378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.826087378
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.3306944607
Short name	T698
Test name
Test status
Simulation time	361304056 ps
CPU time	2.73 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:00 PM PDT 24
Peak memory	222892 kb
Host	smart-913d4b73-59fd-4285-99f7-6276aba0e22f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306944607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3306944607
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.1531864992
Short name	T341
Test name
Test status
Simulation time	1864852848 ps
CPU time	32.93 seconds
Started	Jun 26 04:40:40 PM PDT 24
Finished	Jun 26 04:41:20 PM PDT 24
Peak memory	251236 kb
Host	smart-751e5566-8bf1-4384-acb7-c2fea9879dab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531864992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1531864992
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.3390967152
Short name	T498
Test name
Test status
Simulation time	58494331 ps
CPU time	2.96 seconds
Started	Jun 26 04:40:44 PM PDT 24
Finished	Jun 26 04:40:53 PM PDT 24
Peak memory	218460 kb
Host	smart-1a177228-99df-4bda-a229-32172ceda0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390967152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3390967152
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.2638603583
Short name	T391
Test name
Test status
Simulation time	1828080216 ps
CPU time	44.99 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:44 PM PDT 24
Peak memory	251220 kb
Host	smart-504f159d-e2dd-4bb7-9241-b5e7b49ea5b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638603583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.2638603583
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1031936548
Short name	T596
Test name
Test status
Simulation time	52205658 ps
CPU time	0.95 seconds
Started	Jun 26 04:40:42 PM PDT 24
Finished	Jun 26 04:40:50 PM PDT 24
Peak memory	209360 kb
Host	smart-8d0f2b71-0ee2-4aef-a058-4059554197c0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031936548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct rl_volatile_unlock_smoke.1031936548
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.941862106
Short name	T721
Test name
Test status
Simulation time	14077829 ps
CPU time	0.84 seconds
Started	Jun 26 04:42:13 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	209056 kb
Host	smart-2a644f2a-cd8f-4d2b-aafd-f2b387603844
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941862106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.941862106
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.1205327446
Short name	T220
Test name
Test status
Simulation time	1921046848 ps
CPU time	13.53 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:29 PM PDT 24
Peak memory	226312 kb
Host	smart-d1e97ab4-5049-4c03-92dc-03972d28ef2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205327446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1205327446
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.3692521386
Short name	T514
Test name
Test status
Simulation time	456255852 ps
CPU time	6.25 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	217564 kb
Host	smart-6b3b012d-4146-4868-aa1d-01981c8322f0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692521386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3692521386
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.3774380206
Short name	T98
Test name
Test status
Simulation time	180913117 ps
CPU time	3.29 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 04:42:06 PM PDT 24
Peak memory	223028 kb
Host	smart-092a960d-f005-402b-a61a-f8f560145025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774380206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3774380206
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.2409383916
Short name	T309
Test name
Test status
Simulation time	2633893023 ps
CPU time	17.09 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 04:42:20 PM PDT 24
Peak memory	220564 kb
Host	smart-d77f781f-15e8-432e-88a4-e35732121ded
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409383916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2409383916
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.768744838
Short name	T371
Test name
Test status
Simulation time	712911851 ps
CPU time	12.35 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:19 PM PDT 24
Peak memory	218492 kb
Host	smart-65f55826-965f-4a66-806e-d1ae818febc8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768744838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di gest.768744838
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.3250117171
Short name	T267
Test name
Test status
Simulation time	921268343 ps
CPU time	9.81 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	218548 kb
Host	smart-5d9dce26-e68f-469a-a7bf-1d7e565eef3e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250117171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 3250117171
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.4258925050
Short name	T170
Test name
Test status
Simulation time	551502424 ps
CPU time	10.76 seconds
Started	Jun 26 04:42:06 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	226412 kb
Host	smart-856b4767-4c25-489f-b16c-c49c2bc58531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258925050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4258925050
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.86171050
Short name	T651
Test name
Test status
Simulation time	95478849 ps
CPU time	3.32 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	214984 kb
Host	smart-d1a1524d-393e-451c-9af6-3bc938f2d53b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86171050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.86171050
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.2420700088
Short name	T85
Test name
Test status
Simulation time	535746628 ps
CPU time	27.3 seconds
Started	Jun 26 04:42:13 PM PDT 24
Finished	Jun 26 04:42:44 PM PDT 24
Peak memory	251196 kb
Host	smart-15743f68-118e-498f-8dad-0912db82ce76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420700088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2420700088
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.3865248855
Short name	T732
Test name
Test status
Simulation time	65879461 ps
CPU time	7.12 seconds
Started	Jun 26 04:42:13 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	250708 kb
Host	smart-c38b16c7-143c-4130-8edd-5611c4ecb68e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865248855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3865248855
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.1500071093
Short name	T500
Test name
Test status
Simulation time	687554058 ps
CPU time	30.72 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	246224 kb
Host	smart-2203f57f-f9c9-46e6-9641-94d0babd1e8e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500071093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.1500071093
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1338996578
Short name	T257
Test name
Test status
Simulation time	30632368 ps
CPU time	0.92 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:17 PM PDT 24
Peak memory	213120 kb
Host	smart-7f9394a2-2b17-43af-913c-08a650d4b3dd
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338996578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.1338996578
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.3165862268
Short name	T163
Test name
Test status
Simulation time	14555823 ps
CPU time	1.06 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:07 PM PDT 24
Peak memory	209308 kb
Host	smart-f7bf70c7-cde4-46b0-b172-bd64159c342b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165862268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3165862268
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.2430130194
Short name	T255
Test name
Test status
Simulation time	1045790080 ps
CPU time	11.33 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:17 PM PDT 24
Peak memory	218536 kb
Host	smart-46f8f7ef-f514-499b-b702-753f599b219c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430130194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2430130194
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.511309388
Short name	T181
Test name
Test status
Simulation time	150113944 ps
CPU time	1.66 seconds
Started	Jun 26 04:42:05 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	217408 kb
Host	smart-538f1f82-6a1c-4af4-af3d-0d3a7947383b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511309388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.511309388
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.3446755419
Short name	T313
Test name
Test status
Simulation time	191802732 ps
CPU time	1.84 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	218488 kb
Host	smart-409f1f89-30a7-4e7a-91e7-16ba265003e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446755419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3446755419
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.3813251820
Short name	T295
Test name
Test status
Simulation time	1658105969 ps
CPU time	14.27 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	226316 kb
Host	smart-30e188a5-516a-4eae-9b4b-f3705b261bc8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813251820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3813251820
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.1230328984
Short name	T378
Test name
Test status
Simulation time	1117637943 ps
CPU time	9.12 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:11 PM PDT 24
Peak memory	218540 kb
Host	smart-e79263cc-5b6f-409b-a7d8-c697d6f0878d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230328984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.1230328984
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.3559372661
Short name	T288
Test name
Test status
Simulation time	1509965794 ps
CPU time	11.31 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:13 PM PDT 24
Peak memory	218472 kb
Host	smart-f96fe28a-79c4-4977-9bc8-6b34398cbf4d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559372661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 3559372661
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.3300361702
Short name	T45
Test name
Test status
Simulation time	725655241 ps
CPU time	9.83 seconds
Started	Jun 26 04:42:04 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	218572 kb
Host	smart-17e3e8a6-1786-47bb-a429-5a27344edc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300361702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3300361702
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.2593529830
Short name	T493
Test name
Test status
Simulation time	499582928 ps
CPU time	6.99 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:13 PM PDT 24
Peak memory	218032 kb
Host	smart-dd68d994-a602-4815-9acb-dc061dc8788e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593529830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2593529830
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.1299005381
Short name	T857
Test name
Test status
Simulation time	607788313 ps
CPU time	37.71 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 04:42:42 PM PDT 24
Peak memory	251544 kb
Host	smart-0d8fa06a-abdb-43e1-816d-dcfdd4260770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299005381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1299005381
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.264614749
Short name	T328
Test name
Test status
Simulation time	398077408 ps
CPU time	8.25 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	251232 kb
Host	smart-9af5915b-9bdc-48d4-b175-58eda9827314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264614749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.264614749
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.352602704
Short name	T388
Test name
Test status
Simulation time	3156315062 ps
CPU time	83.95 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:43:29 PM PDT 24
Peak memory	259472 kb
Host	smart-1b82f0c9-d52e-40c4-9a7b-a9ac8812a615
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352602704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.352602704
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3503078584
Short name	T478
Test name
Test status
Simulation time	11419118 ps
CPU time	0.94 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:05 PM PDT 24
Peak memory	209196 kb
Host	smart-4fd4d646-b1a4-49b7-8292-663c4fdafced
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503078584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.3503078584
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.1242493853
Short name	T362
Test name
Test status
Simulation time	21877217 ps
CPU time	1.23 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	209264 kb
Host	smart-c6ac0293-5ad2-4410-b3c8-7ccdf1fd96fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242493853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1242493853
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.1946864655
Short name	T231
Test name
Test status
Simulation time	273176378 ps
CPU time	11.3 seconds
Started	Jun 26 04:42:02 PM PDT 24
Finished	Jun 26 04:42:15 PM PDT 24
Peak memory	226348 kb
Host	smart-64b5b155-6568-49a9-9521-9a49e904a2fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946864655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1946864655
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.3429742974
Short name	T4
Test name
Test status
Simulation time	1426447929 ps
CPU time	9.27 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	217488 kb
Host	smart-f1aad5b5-cf22-4fda-9fd7-64c663ef4c61
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429742974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3429742974
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.759275731
Short name	T767
Test name
Test status
Simulation time	309407471 ps
CPU time	3.45 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:19 PM PDT 24
Peak memory	222768 kb
Host	smart-cd302a8c-93d2-4dbb-8d50-241240a1d4d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759275731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.759275731
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.4182348176
Short name	T91
Test name
Test status
Simulation time	1415104015 ps
CPU time	14.39 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	218736 kb
Host	smart-31db2f6c-065f-4195-aa46-697046d83f79
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182348176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4182348176
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.1643876936
Short name	T287
Test name
Test status
Simulation time	367473653 ps
CPU time	11.26 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	218500 kb
Host	smart-557bb0c6-bc76-424a-a3ec-d5abe2a8fd32
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643876936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.1643876936
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.109908474
Short name	T545
Test name
Test status
Simulation time	1754179522 ps
CPU time	9.47 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	218584 kb
Host	smart-f8a51cee-5323-468d-95f9-47a50ad9841e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109908474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.109908474
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.670356405
Short name	T46
Test name
Test status
Simulation time	1210073118 ps
CPU time	12.6 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	226344 kb
Host	smart-ee8c3b2f-7b46-4e1b-8525-375814a119b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670356405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.670356405
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.2182325424
Short name	T512
Test name
Test status
Simulation time	285657746 ps
CPU time	3.21 seconds
Started	Jun 26 04:42:05 PM PDT 24
Finished	Jun 26 04:42:10 PM PDT 24
Peak memory	215304 kb
Host	smart-19204295-9a17-462f-b0b6-b69ae8f8c86b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182325424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2182325424
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.4133737586
Short name	T442
Test name
Test status
Simulation time	873648225 ps
CPU time	28.86 seconds
Started	Jun 26 04:42:01 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	251308 kb
Host	smart-4a3d34af-7959-4580-be61-b42368aab3f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133737586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4133737586
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.2588107597
Short name	T780
Test name
Test status
Simulation time	218194617 ps
CPU time	6.3 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	251188 kb
Host	smart-d2725953-6e5d-47e4-acbb-be514cace392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588107597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2588107597
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.350439171
Short name	T244
Test name
Test status
Simulation time	1102361687 ps
CPU time	14.49 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	226336 kb
Host	smart-72cacfdd-0a3f-4f30-91c7-ad6a7f105e83
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350439171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.350439171
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.718550485
Short name	T40
Test name
Test status
Simulation time	21166683 ps
CPU time	0.8 seconds
Started	Jun 26 04:42:03 PM PDT 24
Finished	Jun 26 04:42:06 PM PDT 24
Peak memory	209212 kb
Host	smart-cccd31c3-d653-452a-892f-54de498a2b21
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718550485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct rl_volatile_unlock_smoke.718550485
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.2964906023
Short name	T590
Test name
Test status
Simulation time	20404680 ps
CPU time	1.15 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:12 PM PDT 24
Peak memory	209276 kb
Host	smart-d07ec54d-8894-4dc7-bcbf-276ecdd35116
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964906023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2964906023
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.2331274326
Short name	T652
Test name
Test status
Simulation time	6460871313 ps
CPU time	15.61 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:34 PM PDT 24
Peak memory	219000 kb
Host	smart-4dcb2672-7445-4e40-99ce-59d2d6f475eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331274326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2331274326
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.1772779779
Short name	T395
Test name
Test status
Simulation time	203738482 ps
CPU time	2.39 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	217356 kb
Host	smart-256af73c-7bea-41b9-a94f-eeba9e3f21a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772779779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1772779779
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.2240980168
Short name	T513
Test name
Test status
Simulation time	92351657 ps
CPU time	2.67 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:17 PM PDT 24
Peak memory	218528 kb
Host	smart-b4548781-6dd3-4148-b564-557d6bd83ffe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240980168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2240980168
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.808178201
Short name	T447
Test name
Test status
Simulation time	2173336880 ps
CPU time	13.92 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	218608 kb
Host	smart-06b9bda9-9744-4cce-b2dd-48f14cab5b85
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808178201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.808178201
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1613130393
Short name	T568
Test name
Test status
Simulation time	3323616078 ps
CPU time	15.49 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	218512 kb
Host	smart-70ac7483-9157-4146-bf87-294ba24f01fe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613130393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1613130393
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.309300940
Short name	T241
Test name
Test status
Simulation time	1152336017 ps
CPU time	8.97 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	218480 kb
Host	smart-23cebb3e-fbcf-4540-9011-d5bb49e29b65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309300940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.309300940
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.1981066123
Short name	T628
Test name
Test status
Simulation time	682597025 ps
CPU time	8.42 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:21 PM PDT 24
Peak memory	226708 kb
Host	smart-11cbeaf6-3958-4c8d-8b04-b5e17607e87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981066123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1981066123
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.2996549513
Short name	T412
Test name
Test status
Simulation time	34244925 ps
CPU time	1.56 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	222164 kb
Host	smart-b63683ac-d95c-4215-8fc6-c05fe886f815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996549513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2996549513
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.2605626942
Short name	T581
Test name
Test status
Simulation time	243871988 ps
CPU time	21.66 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	251212 kb
Host	smart-903c1564-4ee3-49da-b534-fa1e6e29723f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605626942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2605626942
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.1683071199
Short name	T552
Test name
Test status
Simulation time	346209701 ps
CPU time	3.6 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:17 PM PDT 24
Peak memory	223104 kb
Host	smart-51e1d203-827f-433e-ae13-d13c5fbfda6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683071199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1683071199
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.4081981782
Short name	T281
Test name
Test status
Simulation time	4316366608 ps
CPU time	37.95 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:49 PM PDT 24
Peak memory	249772 kb
Host	smart-c757ef14-fbd4-438b-abf2-fbebdb0466a1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081981782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.4081981782
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1964127007
Short name	T505
Test name
Test status
Simulation time	22260422928 ps
CPU time	267.79 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:46:43 PM PDT 24
Peak memory	281172 kb
Host	smart-c23a21ac-377f-443c-8df6-48c1da1d3dec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1964127007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1964127007
Directory	/workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3386495308
Short name	T562
Test name
Test status
Simulation time	33004794 ps
CPU time	0.91 seconds
Started	Jun 26 04:42:07 PM PDT 24
Finished	Jun 26 04:42:09 PM PDT 24
Peak memory	209388 kb
Host	smart-9698eaf5-3965-4d26-a5a9-456611314df5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386495308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.3386495308
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.3518732448
Short name	T858
Test name
Test status
Simulation time	38458165 ps
CPU time	0.84 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	209132 kb
Host	smart-d484dd8b-ba24-4ce9-98dd-828aa02f5e25
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518732448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3518732448
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.3469262870
Short name	T226
Test name
Test status
Simulation time	192812008 ps
CPU time	10.01 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	218436 kb
Host	smart-cb3fb7c6-a104-4fe2-abb9-51aa685aba44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469262870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3469262870
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.3861905444
Short name	T544
Test name
Test status
Simulation time	69627183 ps
CPU time	1.4 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	217568 kb
Host	smart-6fb3071f-3464-4cd8-a069-c92e0b09e088
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861905444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3861905444
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.2473847115
Short name	T422
Test name
Test status
Simulation time	360575044 ps
CPU time	4.49 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	218516 kb
Host	smart-e4bd24fd-c49f-4c3b-98b3-0dc40f407142
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473847115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2473847115
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.2952499118
Short name	T510
Test name
Test status
Simulation time	632216572 ps
CPU time	11 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:30 PM PDT 24
Peak memory	218548 kb
Host	smart-95149457-9759-46bf-80d3-4653877d7d7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952499118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2952499118
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.1528546404
Short name	T307
Test name
Test status
Simulation time	2848618379 ps
CPU time	9.82 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	218608 kb
Host	smart-e50e0c46-06cd-4c5c-8d12-4acb653e055a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528546404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d igest.1528546404
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.4273190053
Short name	T842
Test name
Test status
Simulation time	751012569 ps
CPU time	6.46 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:18 PM PDT 24
Peak memory	218480 kb
Host	smart-9f3ca18c-c59a-4bc6-bdc8-4679d94124fe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273190053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux. 4273190053
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.1616898213
Short name	T205
Test name
Test status
Simulation time	3548491531 ps
CPU time	11.12 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:21 PM PDT 24
Peak memory	218656 kb
Host	smart-16d35b25-9a8b-4e6c-8156-73de13c3e6ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616898213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1616898213
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.2528607328
Short name	T348
Test name
Test status
Simulation time	328182881 ps
CPU time	2.95 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	214948 kb
Host	smart-e9ac4008-921c-4d63-b3b1-0c771254681c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528607328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2528607328
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.3515087175
Short name	T855
Test name
Test status
Simulation time	1944822498 ps
CPU time	40.38 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:50 PM PDT 24
Peak memory	251232 kb
Host	smart-6263c83d-4964-4888-8bfa-34fd6cfd1aec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515087175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3515087175
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.1491586706
Short name	T707
Test name
Test status
Simulation time	46350680 ps
CPU time	7.04 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	251220 kb
Host	smart-bb246ffe-1be9-4048-ad6d-baf3b0dc11e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491586706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1491586706
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.3609645683
Short name	T648
Test name
Test status
Simulation time	14985917980 ps
CPU time	95.75 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:43:51 PM PDT 24
Peak memory	252696 kb
Host	smart-97d3f0f7-8ea2-424f-a667-f488c3d7be2f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609645683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.3609645683
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1555474902
Short name	T113
Test name
Test status
Simulation time	38233858304 ps
CPU time	582 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:51:58 PM PDT 24
Peak memory	262376 kb
Host	smart-13976bdc-c3e2-42ea-a614-1383fa5035c3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1555474902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1555474902
Directory	/workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2650038269
Short name	T233
Test name
Test status
Simulation time	61459887 ps
CPU time	0.78 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	207632 kb
Host	smart-b896d2fa-a2f5-4595-8176-2fb52ea32f48
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650038269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.2650038269
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.3088053506
Short name	T827
Test name
Test status
Simulation time	64666337 ps
CPU time	0.84 seconds
Started	Jun 26 04:42:12 PM PDT 24
Finished	Jun 26 04:42:17 PM PDT 24
Peak memory	209092 kb
Host	smart-d9f222ff-3763-473e-8299-27086a6482ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088053506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3088053506
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.2440944243
Short name	T392
Test name
Test status
Simulation time	1231485957 ps
CPU time	14.88 seconds
Started	Jun 26 04:42:13 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	218528 kb
Host	smart-8d44bb87-23e7-4025-925f-891538539c13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440944243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2440944243
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.235375840
Short name	T96
Test name
Test status
Simulation time	700461585 ps
CPU time	9.95 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	217680 kb
Host	smart-0b8680d6-b190-4643-83cd-cc394f47fb9c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235375840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.235375840
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.2455178471
Short name	T561
Test name
Test status
Simulation time	460697188 ps
CPU time	2.81 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	218596 kb
Host	smart-8678a363-2a3d-4cf2-8079-285e09237a15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455178471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2455178471
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.1004978230
Short name	T446
Test name
Test status
Simulation time	668681540 ps
CPU time	10.63 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:25 PM PDT 24
Peak memory	226324 kb
Host	smart-93435169-795e-45f0-ad14-82fb9606656e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004978230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1004978230
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.1674851565
Short name	T756
Test name
Test status
Simulation time	251264857 ps
CPU time	7.04 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:21 PM PDT 24
Peak memory	218480 kb
Host	smart-aa5941f4-40c9-421d-8515-c60096dcc002
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674851565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d igest.1674851565
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.343874792
Short name	T248
Test name
Test status
Simulation time	192120673 ps
CPU time	8.46 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	218480 kb
Host	smart-1968ff70-1543-4420-98ee-1f347e2e1c2a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343874792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.343874792
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.4027201140
Short name	T743
Test name
Test status
Simulation time	2451627788 ps
CPU time	11.77 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	225920 kb
Host	smart-7cceb8d9-b651-4fd7-893a-b60103a63842
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027201140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4027201140
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.2706260568
Short name	T528
Test name
Test status
Simulation time	24822582 ps
CPU time	1.5 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	213912 kb
Host	smart-7143b79a-4f38-4824-9e90-b3a06b3a3b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706260568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2706260568
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.3550663949
Short name	T380
Test name
Test status
Simulation time	290848126 ps
CPU time	26.87 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	251076 kb
Host	smart-731d0373-1a2b-4daf-b9f6-cc781681ea31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550663949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3550663949
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.2874012107
Short name	T592
Test name
Test status
Simulation time	270264708 ps
CPU time	2.81 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	222556 kb
Host	smart-814019d3-9106-4c8d-9f39-1f133cc66f60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874012107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2874012107
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.2456955940
Short name	T557
Test name
Test status
Simulation time	18186044514 ps
CPU time	48.14 seconds
Started	Jun 26 04:42:09 PM PDT 24
Finished	Jun 26 04:43:00 PM PDT 24
Peak memory	251280 kb
Host	smart-23c7ab80-1248-4567-abac-dc682c2e3faa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456955940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.2456955940
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.242854604
Short name	T158
Test name
Test status
Simulation time	151504065184 ps
CPU time	789.54 seconds
Started	Jun 26 04:42:17 PM PDT 24
Finished	Jun 26 04:55:31 PM PDT 24
Peak memory	513504 kb
Host	smart-9f8b7ca3-78ed-4a0d-a462-4e0286e829d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=242854604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.242854604
Directory	/workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2776483776
Short name	T420
Test name
Test status
Simulation time	16257477 ps
CPU time	1.19 seconds
Started	Jun 26 04:42:11 PM PDT 24
Finished	Jun 26 04:42:16 PM PDT 24
Peak memory	212140 kb
Host	smart-e3b43cd8-a35e-45d1-bc48-f80ea6dc080c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776483776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.2776483776
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.2039335048
Short name	T400
Test name
Test status
Simulation time	45145740 ps
CPU time	1.04 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	209268 kb
Host	smart-730cbb2c-f72a-4b12-9422-5cf12ab16e00
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039335048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2039335048
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.803875137
Short name	T612
Test name
Test status
Simulation time	2120728690 ps
CPU time	21.11 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:42:45 PM PDT 24
Peak memory	218452 kb
Host	smart-b490f8e9-093b-4e10-8a6b-26ce03cb55d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803875137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.803875137
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.2343024736
Short name	T593
Test name
Test status
Simulation time	963016149 ps
CPU time	3.8 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	217436 kb
Host	smart-6d16ff67-337a-4c9c-80ff-3a093d9a85ac
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343024736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2343024736
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.2505695066
Short name	T167
Test name
Test status
Simulation time	230502329 ps
CPU time	2.7 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	218596 kb
Host	smart-415e8830-c2bc-4499-afb0-681de0d14424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505695066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2505695066
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.4001445000
Short name	T657
Test name
Test status
Simulation time	355056208 ps
CPU time	15.79 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	218692 kb
Host	smart-c643c21d-47eb-41de-ae4d-2d09664e23e6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001445000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4001445000
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.1385253449
Short name	T622
Test name
Test status
Simulation time	413229621 ps
CPU time	11.2 seconds
Started	Jun 26 04:42:20 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	218568 kb
Host	smart-47d1fd98-c8ca-466a-a3b3-64343f242e8e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385253449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.1385253449
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.1984732162
Short name	T632
Test name
Test status
Simulation time	382222344 ps
CPU time	9.3 seconds
Started	Jun 26 04:42:17 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	218504 kb
Host	smart-7b919beb-9fc1-42df-befb-285541593c23
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984732162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux. 1984732162
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.1924460110
Short name	T275
Test name
Test status
Simulation time	2269818316 ps
CPU time	9.95 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	218652 kb
Host	smart-5590c856-aa23-4aa3-8480-aadc1ceccba4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924460110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1924460110
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.197614118
Short name	T11
Test name
Test status
Simulation time	82441729 ps
CPU time	3.14 seconds
Started	Jun 26 04:42:08 PM PDT 24
Finished	Jun 26 04:42:13 PM PDT 24
Peak memory	217924 kb
Host	smart-05414525-974a-4a5d-a0a3-c6ea8cf306d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197614118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.197614118
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.4106916556
Short name	T727
Test name
Test status
Simulation time	1951434072 ps
CPU time	30.34 seconds
Started	Jun 26 04:42:10 PM PDT 24
Finished	Jun 26 04:42:44 PM PDT 24
Peak memory	251276 kb
Host	smart-4df57b21-023a-4251-a71f-c1154a0742a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106916556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4106916556
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.3896485930
Short name	T783
Test name
Test status
Simulation time	1167446021 ps
CPU time	8.08 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:29 PM PDT 24
Peak memory	251156 kb
Host	smart-c07841ed-3b97-49de-8c81-6d27e0675be7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896485930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3896485930
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.2176082040
Short name	T471
Test name
Test status
Simulation time	3560849880 ps
CPU time	121.06 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:44:22 PM PDT 24
Peak memory	275820 kb
Host	smart-1bfdaf7f-b78f-40b1-8d00-2dae3068e99f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176082040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.2176082040
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.521450088
Short name	T150
Test name
Test status
Simulation time	37273741005 ps
CPU time	219.78 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:46:00 PM PDT 24
Peak memory	422232 kb
Host	smart-b8fad430-bd73-44fc-927c-344b847bf8da
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=521450088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.521450088
Directory	/workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.630919306
Short name	T620
Test name
Test status
Simulation time	14884838 ps
CPU time	1 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:20 PM PDT 24
Peak memory	212048 kb
Host	smart-dbb602ba-8f0a-4a3d-b3ea-edb87fece1a8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630919306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct rl_volatile_unlock_smoke.630919306
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.107843958
Short name	T250
Test name
Test status
Simulation time	57952657 ps
CPU time	1.13 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	209376 kb
Host	smart-c52cbcfa-8d93-4a44-8f0d-d975ae662019
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107843958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.107843958
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.3166265587
Short name	T868
Test name
Test status
Simulation time	371299755 ps
CPU time	16.35 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	218608 kb
Host	smart-8d3b8a02-7db6-46ce-b5d7-cb467f55ce07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166265587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3166265587
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.975792896
Short name	T180
Test name
Test status
Simulation time	4552525482 ps
CPU time	11.22 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:42:34 PM PDT 24
Peak memory	218000 kb
Host	smart-3b8e4b64-2f90-4ba7-a118-f34403a30806
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975792896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.975792896
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.190916526
Short name	T57
Test name
Test status
Simulation time	26277804 ps
CPU time	1.65 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	218672 kb
Host	smart-d597ed41-8c91-480d-8f7c-80c36346f7ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190916526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.190916526
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.2242781887
Short name	T854
Test name
Test status
Simulation time	1226289821 ps
CPU time	15.55 seconds
Started	Jun 26 04:42:17 PM PDT 24
Finished	Jun 26 04:42:38 PM PDT 24
Peak memory	218640 kb
Host	smart-5a44b168-558a-4fc7-90d0-f31d86d2a16d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242781887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2242781887
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.2041655185
Short name	T213
Test name
Test status
Simulation time	924648974 ps
CPU time	14.67 seconds
Started	Jun 26 04:42:17 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	218496 kb
Host	smart-3903bae8-d533-412d-9f50-47aca9ea18ad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041655185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.2041655185
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.235443818
Short name	T316
Test name
Test status
Simulation time	446909430 ps
CPU time	9.75 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	218320 kb
Host	smart-22e993b7-ca2d-49cf-912e-15863aa2029f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235443818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.235443818
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.1418043969
Short name	T716
Test name
Test status
Simulation time	756722240 ps
CPU time	9.91 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:30 PM PDT 24
Peak memory	225784 kb
Host	smart-6c6ac604-78c5-4b2a-9eb1-8313c0bde1b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418043969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1418043969
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.1954989511
Short name	T692
Test name
Test status
Simulation time	52092783 ps
CPU time	3.11 seconds
Started	Jun 26 04:42:13 PM PDT 24
Finished	Jun 26 04:42:20 PM PDT 24
Peak memory	223932 kb
Host	smart-506dca0c-bcc3-4027-9f02-ccee9e191d5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954989511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1954989511
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.2847578343
Short name	T802
Test name
Test status
Simulation time	975604520 ps
CPU time	26.24 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	251208 kb
Host	smart-3432fc3c-958f-423c-8cc3-ccfe39763f8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847578343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2847578343
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.406710047
Short name	T176
Test name
Test status
Simulation time	301609787 ps
CPU time	7.97 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:29 PM PDT 24
Peak memory	251224 kb
Host	smart-ae859aa7-5133-4bb4-94d2-5c63b9330fc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406710047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.406710047
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.4124153319
Short name	T816
Test name
Test status
Simulation time	16094052833 ps
CPU time	275.38 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:46:57 PM PDT 24
Peak memory	283608 kb
Host	smart-352850f4-0e55-41d9-a696-f886c0a32f21
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124153319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.4124153319
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.254315954
Short name	T277
Test name
Test status
Simulation time	34959200 ps
CPU time	0.87 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:20 PM PDT 24
Peak memory	209272 kb
Host	smart-369a56b9-7f3b-4e02-8bcf-7a30a57ccb15
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254315954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct rl_volatile_unlock_smoke.254315954
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.194840512
Short name	T417
Test name
Test status
Simulation time	19333774 ps
CPU time	1.2 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	209336 kb
Host	smart-4ec19f28-4501-47c9-b82b-414b6ef5b147
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194840512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.194840512
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.3953610015
Short name	T300
Test name
Test status
Simulation time	943174570 ps
CPU time	11.99 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	218500 kb
Host	smart-6b96c800-1a0a-41d9-907f-343ee6f359b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953610015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3953610015
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.313768619
Short name	T587
Test name
Test status
Simulation time	999751547 ps
CPU time	6.55 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	217632 kb
Host	smart-1152ef00-7b0c-472d-a749-d169e5bdfdb5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313768619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.313768619
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.1405540698
Short name	T597
Test name
Test status
Simulation time	63067821 ps
CPU time	3.26 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	218504 kb
Host	smart-dbb8ef14-baba-4573-a7c5-e6aed5cc63be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405540698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1405540698
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.2276952944
Short name	T41
Test name
Test status
Simulation time	992619704 ps
CPU time	8.33 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	226336 kb
Host	smart-c84daaf8-9a44-43f2-9be7-e78de38ff891
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276952944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2276952944
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.3521669941
Short name	T310
Test name
Test status
Simulation time	1646671346 ps
CPU time	11.17 seconds
Started	Jun 26 04:42:14 PM PDT 24
Finished	Jun 26 04:42:30 PM PDT 24
Peak memory	218472 kb
Host	smart-cc274af7-db81-49e5-bec4-ec4335f3996c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521669941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.3521669941
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.2020011642
Short name	T421
Test name
Test status
Simulation time	358843007 ps
CPU time	12.5 seconds
Started	Jun 26 04:42:17 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	218408 kb
Host	smart-417af451-321d-41a6-a949-b6b7e7262d79
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020011642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 2020011642
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.2290383062
Short name	T613
Test name
Test status
Simulation time	1717282393 ps
CPU time	12.16 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	226264 kb
Host	smart-d3cf211c-d825-43da-8f08-be08659b0d9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290383062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2290383062
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.6732657
Short name	T320
Test name
Test status
Simulation time	136379762 ps
CPU time	2.47 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	214852 kb
Host	smart-f3950d07-9df7-46da-bfee-13306a2da25e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6732657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.6732657
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.508480291
Short name	T469
Test name
Test status
Simulation time	1218418238 ps
CPU time	26.24 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	251168 kb
Host	smart-f67b48df-b583-4816-ad53-dbdc11aad9bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508480291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.508480291
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.2016621312
Short name	T509
Test name
Test status
Simulation time	233421998 ps
CPU time	6.57 seconds
Started	Jun 26 04:42:20 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	251188 kb
Host	smart-dbb26538-b502-480b-b03c-fc4c44d8a5b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016621312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2016621312
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.2315960028
Short name	T473
Test name
Test status
Simulation time	5144742638 ps
CPU time	80.04 seconds
Started	Jun 26 04:42:15 PM PDT 24
Finished	Jun 26 04:43:40 PM PDT 24
Peak memory	251268 kb
Host	smart-600967f5-1b76-40e2-ad36-9ae5bd02cbba
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315960028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.2315960028
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1950154131
Short name	T154
Test name
Test status
Simulation time	16200914192 ps
CPU time	370.25 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:48:34 PM PDT 24
Peak memory	422276 kb
Host	smart-dc6bf8c4-6954-4697-a6a0-38da026dbc93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1950154131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1950154131
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.593285313
Short name	T637
Test name
Test status
Simulation time	26397293 ps
CPU time	0.98 seconds
Started	Jun 26 04:42:18 PM PDT 24
Finished	Jun 26 04:42:24 PM PDT 24
Peak memory	209212 kb
Host	smart-0b0bf2e4-8c18-4c27-a78f-a2407054a6c8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593285313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct rl_volatile_unlock_smoke.593285313
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.3953029152
Short name	T848
Test name
Test status
Simulation time	84753882 ps
CPU time	1.14 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	209420 kb
Host	smart-ec8c5fc5-d482-4222-9120-cb236ce9dafa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953029152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3953029152
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.2063532193
Short name	T303
Test name
Test status
Simulation time	1096716115 ps
CPU time	13.23 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	218528 kb
Host	smart-6114f591-f804-463d-8077-f1c400cd72c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063532193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2063532193
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.2434406461
Short name	T65
Test name
Test status
Simulation time	200009686 ps
CPU time	2.12 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	217320 kb
Host	smart-69cc852f-2168-43b2-81ca-bebe998b3d68
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434406461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2434406461
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.1266020339
Short name	T650
Test name
Test status
Simulation time	127802077 ps
CPU time	2.26 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	218528 kb
Host	smart-99e91582-ceeb-4748-ab5c-77bd70c6f408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266020339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1266020339
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.2349340564
Short name	T775
Test name
Test status
Simulation time	1720449694 ps
CPU time	14.77 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:42 PM PDT 24
Peak memory	219196 kb
Host	smart-6d7b2491-c34b-40c3-b41d-62acc16be7c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349340564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2349340564
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.1816792533
Short name	T598
Test name
Test status
Simulation time	475073593 ps
CPU time	8.34 seconds
Started	Jun 26 04:42:25 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	218344 kb
Host	smart-5a804547-1040-45b3-8437-08097d488e62
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816792533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.1816792533
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.1422311561
Short name	T451
Test name
Test status
Simulation time	289934352 ps
CPU time	10.7 seconds
Started	Jun 26 04:42:30 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	218476 kb
Host	smart-ff83121b-473c-40a3-ad68-39246b975784
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422311561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 1422311561
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.1985689316
Short name	T844
Test name
Test status
Simulation time	815329050 ps
CPU time	10.74 seconds
Started	Jun 26 04:42:21 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	224912 kb
Host	smart-5ad42017-fb84-442e-ab68-9bbe68b7340c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985689316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1985689316
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.2627415231
Short name	T784
Test name
Test status
Simulation time	51591972 ps
CPU time	3.42 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	218048 kb
Host	smart-2c747b1f-a6d9-46fe-ab7c-b8e6437645f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627415231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2627415231
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.1647588178
Short name	T733
Test name
Test status
Simulation time	1351347614 ps
CPU time	30.48 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:57 PM PDT 24
Peak memory	251236 kb
Host	smart-a7c0025b-6505-4cd0-bfee-27a19906e57d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647588178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1647588178
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.2803571221
Short name	T849
Test name
Test status
Simulation time	380926734 ps
CPU time	9.37 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	251172 kb
Host	smart-94d9f78b-0c60-4869-9404-38de0b92a9ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803571221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2803571221
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.1676028747
Short name	T614
Test name
Test status
Simulation time	5694608310 ps
CPU time	142.98 seconds
Started	Jun 26 04:42:21 PM PDT 24
Finished	Jun 26 04:44:48 PM PDT 24
Peak memory	284000 kb
Host	smart-9d954d72-5e0c-43b6-ba08-9ca113b77174
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676028747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.1676028747
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1062079247
Short name	T425
Test name
Test status
Simulation time	192248277562 ps
CPU time	576.49 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:52:02 PM PDT 24
Peak memory	496092 kb
Host	smart-ff56496a-0671-4128-b832-a4ff2a358807
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1062079247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1062079247
Directory	/workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1991649189
Short name	T584
Test name
Test status
Simulation time	58974267 ps
CPU time	0.74 seconds
Started	Jun 26 04:42:16 PM PDT 24
Finished	Jun 26 04:42:22 PM PDT 24
Peak memory	207264 kb
Host	smart-a12aac27-d392-4bbe-9f43-e218db680501
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991649189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.1991649189
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.1938910278
Short name	T764
Test name
Test status
Simulation time	27935210 ps
CPU time	1.25 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:03 PM PDT 24
Peak memory	209432 kb
Host	smart-b70b3be2-46e5-4693-a26e-638fa59c200a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938910278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1938910278
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.4113576481
Short name	T73
Test name
Test status
Simulation time	12595824 ps
CPU time	1.02 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:40:56 PM PDT 24
Peak memory	209212 kb
Host	smart-a485ffba-5f14-479b-8dc5-ea01238c60c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113576481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.4113576481
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.1552721503
Short name	T280
Test name
Test status
Simulation time	437391237 ps
CPU time	14.31 seconds
Started	Jun 26 04:40:49 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	218536 kb
Host	smart-b7e5ace5-9d15-4461-b039-ca750657089c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552721503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1552721503
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.3387171212
Short name	T645
Test name
Test status
Simulation time	385972439 ps
CPU time	1.81 seconds
Started	Jun 26 04:40:53 PM PDT 24
Finished	Jun 26 04:41:02 PM PDT 24
Peak memory	217252 kb
Host	smart-d404fd22-5636-402a-a0fd-690a22031c4f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387171212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3387171212
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.2210850440
Short name	T237
Test name
Test status
Simulation time	35682501902 ps
CPU time	74.26 seconds
Started	Jun 26 04:40:53 PM PDT 24
Finished	Jun 26 04:42:14 PM PDT 24
Peak memory	226632 kb
Host	smart-9c56d677-b920-4e3b-b115-1500b9c97bf8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210850440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.2210850440
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.463151547
Short name	T853
Test name
Test status
Simulation time	315213914 ps
CPU time	3.14 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:03 PM PDT 24
Peak memory	218012 kb
Host	smart-abbaa7e6-98b2-4d66-b58e-31f8cc24fdba
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463151547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.463151547
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3668309257
Short name	T397
Test name
Test status
Simulation time	314270140 ps
CPU time	4.9 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:08 PM PDT 24
Peak memory	223416 kb
Host	smart-fa357664-ab3b-46b6-9414-87738f402064
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668309257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.3668309257
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2637506754
Short name	T765
Test name
Test status
Simulation time	612471787 ps
CPU time	16.46 seconds
Started	Jun 26 04:40:57 PM PDT 24
Finished	Jun 26 04:41:20 PM PDT 24
Peak memory	217844 kb
Host	smart-220d85c8-134d-48a9-a2dc-42ad9d1a6b51
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637506754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.2637506754
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.2171330281
Short name	T389
Test name
Test status
Simulation time	994417553 ps
CPU time	7.75 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:08 PM PDT 24
Peak memory	217880 kb
Host	smart-93334261-aba2-4e4f-a0a5-b49f9d60ea82
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171330281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke. 2171330281
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2251772725
Short name	T771
Test name
Test status
Simulation time	2155161241 ps
CPU time	32.2 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	251168 kb
Host	smart-b9d5b623-451a-41a7-85cd-1f759800a1e6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251772725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.2251772725
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1648325958
Short name	T710
Test name
Test status
Simulation time	370830919 ps
CPU time	10.69 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:13 PM PDT 24
Peak memory	251100 kb
Host	smart-e8142058-ed36-42f5-aafc-df82c76ddec3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648325958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.1648325958
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.143130699
Short name	T168
Test name
Test status
Simulation time	65374185 ps
CPU time	2.64 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:40:58 PM PDT 24
Peak memory	222604 kb
Host	smart-c4fe03ee-aa4b-4e71-b3cf-e835558e34e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143130699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.143130699
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.1111256437
Short name	T819
Test name
Test status
Simulation time	787281383 ps
CPU time	13.08 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	214904 kb
Host	smart-300eccc7-1fdc-41ee-b2a2-60cdffe4a4ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111256437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1111256437
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.2573082485
Short name	T49
Test name
Test status
Simulation time	247017574 ps
CPU time	35.73 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:38 PM PDT 24
Peak memory	284388 kb
Host	smart-15dcbe10-b7a4-4f0a-8b93-deaddf60eb15
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573082485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2573082485
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.2789689755
Short name	T563
Test name
Test status
Simulation time	285041639 ps
CPU time	12.5 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:12 PM PDT 24
Peak memory	219172 kb
Host	smart-082eb61e-0e12-4283-a8aa-71d13a974518
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789689755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2789689755
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.3414056024
Short name	T468
Test name
Test status
Simulation time	1612459935 ps
CPU time	16.11 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	218524 kb
Host	smart-eab52562-a429-4d55-8944-8f5a3f98d1e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414056024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di gest.3414056024
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.4140948064
Short name	T329
Test name
Test status
Simulation time	805109332 ps
CPU time	9.5 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:14 PM PDT 24
Peak memory	226280 kb
Host	smart-b715ab70-4368-4d1c-8bc9-9c4423eb8a0f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140948064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4 140948064
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.1721016427
Short name	T719
Test name
Test status
Simulation time	270901150 ps
CPU time	6.88 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:41:02 PM PDT 24
Peak memory	224600 kb
Host	smart-d198564c-96f3-47e2-a346-36120ae683d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721016427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1721016427
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.265955754
Short name	T638
Test name
Test status
Simulation time	138316013 ps
CPU time	2.77 seconds
Started	Jun 26 04:40:48 PM PDT 24
Finished	Jun 26 04:40:57 PM PDT 24
Peak memory	215144 kb
Host	smart-b6a6e19f-3a81-4f91-9180-77f30eb7b661
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265955754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.265955754
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.2445304291
Short name	T611
Test name
Test status
Simulation time	2503438082 ps
CPU time	20.99 seconds
Started	Jun 26 04:40:47 PM PDT 24
Finished	Jun 26 04:41:15 PM PDT 24
Peak memory	251392 kb
Host	smart-56eb3155-dd9d-4515-92b8-8f8f21a31e7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445304291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2445304291
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.3751683567
Short name	T810
Test name
Test status
Simulation time	197904300 ps
CPU time	7.64 seconds
Started	Jun 26 04:40:50 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	251300 kb
Host	smart-ee927cb5-88ff-44ca-9f86-4732316d6bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751683567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3751683567
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.1542142261
Short name	T801
Test name
Test status
Simulation time	3589957078 ps
CPU time	74.36 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:42:19 PM PDT 24
Peak memory	251280 kb
Host	smart-dd52f7a9-a680-454d-bfd4-2cf089905ebc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542142261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.1542142261
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3304870344
Short name	T151
Test name
Test status
Simulation time	17925558691 ps
CPU time	467.88 seconds
Started	Jun 26 04:40:57 PM PDT 24
Finished	Jun 26 04:48:51 PM PDT 24
Peak memory	274956 kb
Host	smart-1b7eec69-3216-4a2e-9783-5092e5dfe59e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3304870344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3304870344
Directory	/workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.105149028
Short name	T658
Test name
Test status
Simulation time	14444923 ps
CPU time	0.97 seconds
Started	Jun 26 04:40:47 PM PDT 24
Finished	Jun 26 04:40:54 PM PDT 24
Peak memory	209116 kb
Host	smart-69e25ccf-58f4-417c-a984-dab510062930
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105149028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_volatile_unlock_smoke.105149028
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.3105471517
Short name	T534
Test name
Test status
Simulation time	22735859 ps
CPU time	1.2 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	209216 kb
Host	smart-340c95bf-63d6-44db-9c51-6ca7eadbae76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105471517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3105471517
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.3685489591
Short name	T370
Test name
Test status
Simulation time	900696809 ps
CPU time	8.28 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	218444 kb
Host	smart-932b9d89-9fca-40b1-8e0f-23aa1e87d9d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685489591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3685489591
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.1180433192
Short name	T736
Test name
Test status
Simulation time	225800155 ps
CPU time	5.76 seconds
Started	Jun 26 04:42:31 PM PDT 24
Finished	Jun 26 04:42:38 PM PDT 24
Peak memory	217340 kb
Host	smart-90138085-a396-4bc5-a58b-a634a57c4d66
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180433192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1180433192
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.3622336753
Short name	T428
Test name
Test status
Simulation time	115677590 ps
CPU time	2.12 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	218608 kb
Host	smart-adee36ab-b9e4-44bb-9784-37d22737b63e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622336753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3622336753
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.762218604
Short name	T463
Test name
Test status
Simulation time	308703725 ps
CPU time	12.82 seconds
Started	Jun 26 04:42:31 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	219268 kb
Host	smart-7a873e4c-63a4-447f-9c13-67e752d911ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762218604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.762218604
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.4028702200
Short name	T384
Test name
Test status
Simulation time	265521364 ps
CPU time	10.46 seconds
Started	Jun 26 04:42:24 PM PDT 24
Finished	Jun 26 04:42:38 PM PDT 24
Peak memory	218572 kb
Host	smart-99b51025-42cc-4bb1-a8f1-7b301d002db5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028702200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.4028702200
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.804569929
Short name	T94
Test name
Test status
Simulation time	1744032001 ps
CPU time	7.59 seconds
Started	Jun 26 04:42:25 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	218580 kb
Host	smart-32b49728-f3ba-4d5f-95e8-a2d9339101bd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804569929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.804569929
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.2460298429
Short name	T51
Test name
Test status
Simulation time	265714610 ps
CPU time	10.28 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	226416 kb
Host	smart-dc1c8879-e8a9-4bff-a4bc-298889417fac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460298429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2460298429
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.3067299969
Short name	T476
Test name
Test status
Simulation time	338830451 ps
CPU time	5.42 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	218016 kb
Host	smart-da534b73-526f-46a7-9391-6de90df938c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067299969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3067299969
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.3780229493
Short name	T365
Test name
Test status
Simulation time	367915050 ps
CPU time	30.82 seconds
Started	Jun 26 04:42:31 PM PDT 24
Finished	Jun 26 04:43:04 PM PDT 24
Peak memory	251212 kb
Host	smart-6e66c8f7-1c5d-4d19-854f-0ebcad272d16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780229493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3780229493
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.4050338426
Short name	T206
Test name
Test status
Simulation time	200378210 ps
CPU time	8 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	251224 kb
Host	smart-d702791c-a40a-4892-a039-5de5085fdab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050338426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4050338426
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.3893453424
Short name	T414
Test name
Test status
Simulation time	4093477008 ps
CPU time	94.93 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:44:02 PM PDT 24
Peak memory	284120 kb
Host	smart-de737c70-a604-4432-9eb7-d3bcae225d16
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893453424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.3893453424
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1622407230
Short name	T301
Test name
Test status
Simulation time	21903388 ps
CPU time	0.95 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	209420 kb
Host	smart-7a0567e6-44f1-4303-a250-a1df446e6072
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622407230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c trl_volatile_unlock_smoke.1622407230
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.1558093017
Short name	T617
Test name
Test status
Simulation time	26376642 ps
CPU time	0.87 seconds
Started	Jun 26 04:42:20 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	209092 kb
Host	smart-ff7eadfb-d996-4fcd-bad1-dd02beac2df9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558093017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1558093017
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.2246220925
Short name	T292
Test name
Test status
Simulation time	331440631 ps
CPU time	16.04 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	218456 kb
Host	smart-5e1fa0f0-4d0c-4d06-b87c-c86a7dfcdd43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246220925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2246220925
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.2809317516
Short name	T24
Test name
Test status
Simulation time	1213772758 ps
CPU time	6.6 seconds
Started	Jun 26 04:42:25 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	217460 kb
Host	smart-76d8a43f-fb50-44e9-94a0-c6eb179a37e4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809317516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2809317516
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.3689822300
Short name	T240
Test name
Test status
Simulation time	63608354 ps
CPU time	2.24 seconds
Started	Jun 26 04:42:25 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	218528 kb
Host	smart-0672d2c8-1a94-4116-9f77-19ae48904b21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689822300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3689822300
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.3337474885
Short name	T260
Test name
Test status
Simulation time	314459494 ps
CPU time	9.37 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:36 PM PDT 24
Peak memory	218512 kb
Host	smart-ffa86b2e-afac-4765-9e59-93db965de61c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337474885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3337474885
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3197404707
Short name	T416
Test name
Test status
Simulation time	838248012 ps
CPU time	15.61 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	218476 kb
Host	smart-8ea0a7a1-2ad9-4890-a064-509307446d20
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197404707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.3197404707
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.283998980
Short name	T490
Test name
Test status
Simulation time	397108444 ps
CPU time	9.65 seconds
Started	Jun 26 04:42:21 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	226284 kb
Host	smart-e0159923-0283-4874-b068-81a6a8cabadb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283998980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.283998980
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.3995425026
Short name	T535
Test name
Test status
Simulation time	1284358514 ps
CPU time	13.61 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	225936 kb
Host	smart-3d9b7d13-f9a0-47c2-b024-072f6a3b42a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995425026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3995425026
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.2993656542
Short name	T444
Test name
Test status
Simulation time	45217690 ps
CPU time	2.2 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	214392 kb
Host	smart-f15a4c08-642d-4048-9bcb-0238d6226dc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993656542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2993656542
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.581477350
Short name	T224
Test name
Test status
Simulation time	596472830 ps
CPU time	28.01 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:57 PM PDT 24
Peak memory	251232 kb
Host	smart-ff8405b1-7646-4a5e-8a42-1c1ce308eeb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581477350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.581477350
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.1533339001
Short name	T826
Test name
Test status
Simulation time	143102512 ps
CPU time	7.08 seconds
Started	Jun 26 04:42:22 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	247100 kb
Host	smart-06b39921-c3f1-4f7c-8d2d-1fbc4eb86f9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533339001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1533339001
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.982343629
Short name	T489
Test name
Test status
Simulation time	3856495126 ps
CPU time	65.59 seconds
Started	Jun 26 04:42:20 PM PDT 24
Finished	Jun 26 04:43:30 PM PDT 24
Peak memory	251252 kb
Host	smart-74a5b37a-bb4a-4715-a994-99ba3b8c524b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982343629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.982343629
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3303204286
Short name	T501
Test name
Test status
Simulation time	15906155 ps
CPU time	1.11 seconds
Started	Jun 26 04:42:23 PM PDT 24
Finished	Jun 26 04:42:28 PM PDT 24
Peak memory	212144 kb
Host	smart-a058f2cf-fa15-462b-b0f7-3cbd34d1c9cb
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303204286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.3303204286
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.3115469515
Short name	T271
Test name
Test status
Simulation time	19186633 ps
CPU time	1.15 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	209428 kb
Host	smart-3d496c70-12db-45a2-b492-4920509e245d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115469515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3115469515
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.416426491
Short name	T246
Test name
Test status
Simulation time	825201617 ps
CPU time	9.3 seconds
Started	Jun 26 04:42:31 PM PDT 24
Finished	Jun 26 04:42:42 PM PDT 24
Peak memory	218532 kb
Host	smart-c1e4f32f-767c-4082-b21d-e5bbb8a16983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416426491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.416426491
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.3984431809
Short name	T457
Test name
Test status
Simulation time	2097575922 ps
CPU time	12.38 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	217748 kb
Host	smart-51c42ce8-bd53-4b7a-b19c-d9b97f8430dc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984431809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3984431809
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.1259658375
Short name	T663
Test name
Test status
Simulation time	62291273 ps
CPU time	2.81 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:33 PM PDT 24
Peak memory	218528 kb
Host	smart-1e56a16b-20e4-4a78-855d-8a73aa0d0c0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259658375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1259658375
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.2519888979
Short name	T706
Test name
Test status
Simulation time	948809132 ps
CPU time	11.13 seconds
Started	Jun 26 04:42:30 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	219172 kb
Host	smart-d288cafd-2e17-4f4b-82d9-43cdf75484af
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519888979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2519888979
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.3394502102
Short name	T431
Test name
Test status
Simulation time	542228232 ps
CPU time	9.23 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	218468 kb
Host	smart-2cc57c4d-77ce-441c-9e95-6ce894dd9b1c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394502102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.3394502102
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.3812846565
Short name	T261
Test name
Test status
Simulation time	251519744 ps
CPU time	9.68 seconds
Started	Jun 26 04:42:31 PM PDT 24
Finished	Jun 26 04:42:42 PM PDT 24
Peak memory	218584 kb
Host	smart-d97953b2-b7bd-402b-b8c9-265712d1943a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812846565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 3812846565
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.3009409343
Short name	T796
Test name
Test status
Simulation time	285679597 ps
CPU time	8.55 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:38 PM PDT 24
Peak memory	225292 kb
Host	smart-12023ae6-c550-47b5-9380-32df05b93151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009409343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3009409343
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.1504245753
Short name	T797
Test name
Test status
Simulation time	395492474 ps
CPU time	3.53 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:34 PM PDT 24
Peak memory	217956 kb
Host	smart-8ceab901-98bf-46e5-a07d-5df78ec6750a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504245753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1504245753
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.2685239027
Short name	T90
Test name
Test status
Simulation time	3259414353 ps
CPU time	27.69 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:58 PM PDT 24
Peak memory	251292 kb
Host	smart-1658be5a-bd64-47cb-b6a6-2b3a98c8e013
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685239027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2685239027
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.828426172
Short name	T495
Test name
Test status
Simulation time	131819027 ps
CPU time	7.08 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	247192 kb
Host	smart-72faeac5-9551-4957-96ee-d48bc97f6876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828426172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.828426172
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.2598649449
Short name	T434
Test name
Test status
Simulation time	1338781403 ps
CPU time	55.37 seconds
Started	Jun 26 04:42:32 PM PDT 24
Finished	Jun 26 04:43:28 PM PDT 24
Peak memory	251092 kb
Host	smart-a2b4cca3-e0bf-46e6-b5d8-0591e943d80e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598649449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.2598649449
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2044239278
Short name	T776
Test name
Test status
Simulation time	43952819 ps
CPU time	0.79 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	209316 kb
Host	smart-01e7f877-961c-4b29-80e9-d1502446bc2f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044239278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.2044239278
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.2132652978
Short name	T164
Test name
Test status
Simulation time	16267580 ps
CPU time	0.93 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	209604 kb
Host	smart-281731f0-69bd-4a1b-ac99-29cb9c1a0a3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132652978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2132652978
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.1601336514
Short name	T788
Test name
Test status
Simulation time	1766007083 ps
CPU time	23.83 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:42:53 PM PDT 24
Peak memory	226268 kb
Host	smart-73b937b2-126d-4861-a450-044a9ca18ae9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601336514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1601336514
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.3086983735
Short name	T696
Test name
Test status
Simulation time	1982933730 ps
CPU time	6.27 seconds
Started	Jun 26 04:42:32 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	217444 kb
Host	smart-2d351afd-b04b-4aab-b3f5-909e3706d688
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086983735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3086983735
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.3439589965
Short name	T351
Test name
Test status
Simulation time	28513796 ps
CPU time	1.99 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:32 PM PDT 24
Peak memory	222312 kb
Host	smart-19242b03-32d9-4888-821a-da63d5d3ac96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439589965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3439589965
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.1771261222
Short name	T871
Test name
Test status
Simulation time	284822661 ps
CPU time	9.32 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	226344 kb
Host	smart-04febe69-eb21-4c85-b21b-826c860cd325
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771261222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1771261222
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.1398655063
Short name	T326
Test name
Test status
Simulation time	3802844213 ps
CPU time	8.95 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	217912 kb
Host	smart-10e0c64c-00fe-4147-a473-dc9873269f87
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398655063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.1398655063
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.2918976884
Short name	T247
Test name
Test status
Simulation time	320007342 ps
CPU time	8.42 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	218564 kb
Host	smart-19bbca65-ded5-4e1d-bf0d-32fbf77875b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918976884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 2918976884
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.2155400161
Short name	T546
Test name
Test status
Simulation time	248195239 ps
CPU time	6.59 seconds
Started	Jun 26 04:42:30 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	225260 kb
Host	smart-5c058bb6-f9fd-4042-a2cc-30096e62825e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2155400161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2155400161
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.1583006461
Short name	T363
Test name
Test status
Simulation time	50248152 ps
CPU time	2.94 seconds
Started	Jun 26 04:42:30 PM PDT 24
Finished	Jun 26 04:42:35 PM PDT 24
Peak memory	214916 kb
Host	smart-9dfc936a-0cc8-411e-b250-043cc8348e8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583006461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1583006461
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.3606561248
Short name	T462
Test name
Test status
Simulation time	524254752 ps
CPU time	28 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:58 PM PDT 24
Peak memory	251280 kb
Host	smart-ed3bf692-0aed-44cb-8def-6e1c0a5ccade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606561248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3606561248
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.670343808
Short name	T437
Test name
Test status
Simulation time	292801962 ps
CPU time	9.27 seconds
Started	Jun 26 04:42:29 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	250480 kb
Host	smart-b68c1bfc-0a29-49fb-91ad-04ec8ced44b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670343808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.670343808
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.172043239
Short name	T467
Test name
Test status
Simulation time	17034690286 ps
CPU time	85.92 seconds
Started	Jun 26 04:42:27 PM PDT 24
Finished	Jun 26 04:43:55 PM PDT 24
Peak memory	277800 kb
Host	smart-82dca50c-fc1a-4fb0-9d40-994940141eaf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172043239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.172043239
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3500925882
Short name	T690
Test name
Test status
Simulation time	143196807 ps
CPU time	1.01 seconds
Started	Jun 26 04:42:28 PM PDT 24
Finished	Jun 26 04:42:31 PM PDT 24
Peak memory	212096 kb
Host	smart-b427c87e-2b9e-4018-a907-756887eae9a6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500925882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.3500925882
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.1879851213
Short name	T69
Test name
Test status
Simulation time	20575820 ps
CPU time	0.97 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:37 PM PDT 24
Peak memory	209200 kb
Host	smart-8fcaa26f-a2b2-4360-85f2-dafc6712b9b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879851213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1879851213
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.1050444131
Short name	T334
Test name
Test status
Simulation time	243876756 ps
CPU time	12.31 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:50 PM PDT 24
Peak memory	218528 kb
Host	smart-a67f5ff2-04be-41ce-b869-21ae1dc8edd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050444131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1050444131
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.2949511455
Short name	T659
Test name
Test status
Simulation time	354258290 ps
CPU time	4.11 seconds
Started	Jun 26 04:42:37 PM PDT 24
Finished	Jun 26 04:42:43 PM PDT 24
Peak memory	217568 kb
Host	smart-7d641567-81f3-466d-9228-922acdaad751
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949511455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2949511455
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.2966903526
Short name	T401
Test name
Test status
Simulation time	431774148 ps
CPU time	3.63 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	222584 kb
Host	smart-42f53a59-4b87-4597-9e11-88ef4ddbadbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966903526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2966903526
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.3177801069
Short name	T789
Test name
Test status
Simulation time	550921973 ps
CPU time	8.91 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:42:47 PM PDT 24
Peak memory	218600 kb
Host	smart-08cd7124-493a-44fd-b5cb-fbee55825e78
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177801069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.3177801069
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.1696675695
Short name	T338
Test name
Test status
Simulation time	492000940 ps
CPU time	8.97 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	226360 kb
Host	smart-59f32542-8718-48aa-b6a0-52cd07cb06ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696675695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux. 1696675695
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.3102325602
Short name	T646
Test name
Test status
Simulation time	1445326120 ps
CPU time	8.37 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:44 PM PDT 24
Peak memory	226440 kb
Host	smart-4483e6cd-8cbc-4ddd-ae50-e099688715d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102325602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3102325602
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.1973125013
Short name	T77
Test name
Test status
Simulation time	137948443 ps
CPU time	2.3 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	214736 kb
Host	smart-54081518-d0fb-4bed-8529-3196d2271083
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973125013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1973125013
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.3116971374
Short name	T97
Test name
Test status
Simulation time	1098465372 ps
CPU time	28.33 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	251212 kb
Host	smart-8b822146-d606-418d-86ea-3dca6e678b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116971374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3116971374
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.3878942867
Short name	T845
Test name
Test status
Simulation time	309636682 ps
CPU time	6.84 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:44 PM PDT 24
Peak memory	246856 kb
Host	smart-00036791-34b6-42ca-8150-7727b3bc8460
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878942867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3878942867
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.1397588582
Short name	T675
Test name
Test status
Simulation time	14276930958 ps
CPU time	224.85 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:46:26 PM PDT 24
Peak memory	263628 kb
Host	smart-64edcbb2-d177-4bee-aab5-e54c8dc66558
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397588582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.1397588582
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1269920656
Short name	T177
Test name
Test status
Simulation time	13777490 ps
CPU time	0.94 seconds
Started	Jun 26 04:42:37 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	208464 kb
Host	smart-a11796d7-7d99-43d8-ae80-238ef789c880
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269920656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.1269920656
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.1701495042
Short name	T439
Test name
Test status
Simulation time	149546337 ps
CPU time	0.91 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	209248 kb
Host	smart-422e57db-d522-4c66-8336-8aa35ce098b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701495042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1701495042
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.72679134
Short name	T626
Test name
Test status
Simulation time	221522141 ps
CPU time	9.5 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:47 PM PDT 24
Peak memory	218536 kb
Host	smart-7646833d-1376-4ab4-9438-cb9aeb944f67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72679134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.72679134
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.2368800779
Short name	T452
Test name
Test status
Simulation time	2078477884 ps
CPU time	6.5 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	217676 kb
Host	smart-53de1c16-1730-46af-996b-a1062373aa19
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368800779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2368800779
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.3682745445
Short name	T786
Test name
Test status
Simulation time	83635063 ps
CPU time	3.24 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	218532 kb
Host	smart-2f56d82d-be59-4912-b70f-3855c4978e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682745445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3682745445
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.4227122864
Short name	T35
Test name
Test status
Simulation time	1259180143 ps
CPU time	11.79 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:47 PM PDT 24
Peak memory	219264 kb
Host	smart-2f1a99c6-1956-4241-adb9-ed211350ce77
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227122864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4227122864
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.8934159
Short name	T236
Test name
Test status
Simulation time	938700778 ps
CPU time	10.19 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:42:49 PM PDT 24
Peak memory	218500 kb
Host	smart-b5fd0d8b-cea2-4dbd-88f6-90f1768af814
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8934159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_dige st.8934159
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.3404324136
Short name	T283
Test name
Test status
Simulation time	282575329 ps
CPU time	12.22 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:42:51 PM PDT 24
Peak memory	226284 kb
Host	smart-9fbee0cc-10b7-44e0-9de3-8d71e53e97b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404324136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 3404324136
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.1261340339
Short name	T379
Test name
Test status
Simulation time	460655231 ps
CPU time	14.9 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:51 PM PDT 24
Peak memory	218596 kb
Host	smart-dcda95c8-a7fd-40f0-abad-8e3c9eeea412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261340339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1261340339
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.1306029833
Short name	T68
Test name
Test status
Simulation time	74046360 ps
CPU time	2.51 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	217964 kb
Host	smart-eab25c13-6eda-45e0-81a4-6b8e0b7efc9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306029833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1306029833
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.3736044838
Short name	T520
Test name
Test status
Simulation time	798566824 ps
CPU time	26.39 seconds
Started	Jun 26 04:42:35 PM PDT 24
Finished	Jun 26 04:43:03 PM PDT 24
Peak memory	251248 kb
Host	smart-3938fdf3-7c62-4679-86df-6526a0c62868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736044838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3736044838
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.4192169267
Short name	T570
Test name
Test status
Simulation time	380403364 ps
CPU time	3.62 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:42:40 PM PDT 24
Peak memory	222880 kb
Host	smart-cc9f0fe8-9038-4e53-a9a4-b876efbdbd39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192169267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.4192169267
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.3269551757
Short name	T108
Test name
Test status
Simulation time	41969963333 ps
CPU time	319.41 seconds
Started	Jun 26 04:42:34 PM PDT 24
Finished	Jun 26 04:47:55 PM PDT 24
Peak memory	267752 kb
Host	smart-4eaa3315-ad42-4983-9aaa-f402ba61ca70
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269551757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.3269551757
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2770508997
Short name	T748
Test name
Test status
Simulation time	27767732 ps
CPU time	0.99 seconds
Started	Jun 26 04:42:37 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	209220 kb
Host	smart-81168f2b-50fd-4cd2-921c-251597be47b1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770508997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c trl_volatile_unlock_smoke.2770508997
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.3992725407
Short name	T543
Test name
Test status
Simulation time	54647666 ps
CPU time	1.05 seconds
Started	Jun 26 04:42:44 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	209296 kb
Host	smart-ca1fc40d-98e7-420e-8dca-798969310cfc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992725407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3992725407
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.2830969575
Short name	T276
Test name
Test status
Simulation time	1008785014 ps
CPU time	9.17 seconds
Started	Jun 26 04:42:40 PM PDT 24
Finished	Jun 26 04:42:51 PM PDT 24
Peak memory	226308 kb
Host	smart-4fc7bb16-f8d9-45a6-95ba-2172050ca7df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830969575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2830969575
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.1271206439
Short name	T574
Test name
Test status
Simulation time	2500122489 ps
CPU time	7.11 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:42:48 PM PDT 24
Peak memory	218056 kb
Host	smart-3f899cc3-fed2-4553-80a0-b88dee69a215
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271206439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1271206439
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.2674146556
Short name	T296
Test name
Test status
Simulation time	135913799 ps
CPU time	2.59 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:42:41 PM PDT 24
Peak memory	218520 kb
Host	smart-e7c1eb9c-acaf-4372-b363-a68afb3775f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674146556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2674146556
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.171347103
Short name	T305
Test name
Test status
Simulation time	1858545317 ps
CPU time	18.95 seconds
Started	Jun 26 04:42:39 PM PDT 24
Finished	Jun 26 04:43:00 PM PDT 24
Peak memory	226344 kb
Host	smart-328c8b90-065f-434e-bb35-e42877871aa1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171347103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.171347103
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.2526680534
Short name	T286
Test name
Test status
Simulation time	923193095 ps
CPU time	14.94 seconds
Started	Jun 26 04:42:43 PM PDT 24
Finished	Jun 26 04:43:00 PM PDT 24
Peak memory	218432 kb
Host	smart-fe840093-0c8c-403e-9e78-d4e0f00bf679
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526680534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d igest.2526680534
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.1883448463
Short name	T610
Test name
Test status
Simulation time	1135467327 ps
CPU time	9.73 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:42:51 PM PDT 24
Peak memory	218460 kb
Host	smart-0a6443fa-14d4-49da-9943-48977d93ca65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883448463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 1883448463
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.2025315423
Short name	T785
Test name
Test status
Simulation time	1382682637 ps
CPU time	12.3 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:42:53 PM PDT 24
Peak memory	226336 kb
Host	smart-027b5940-c26b-432d-955f-aa98383a74ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025315423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2025315423
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.2470012122
Short name	T56
Test name
Test status
Simulation time	62204694 ps
CPU time	3.33 seconds
Started	Jun 26 04:42:33 PM PDT 24
Finished	Jun 26 04:42:38 PM PDT 24
Peak memory	215236 kb
Host	smart-75661337-f5b6-428b-8ee7-9d963c27dd21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470012122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2470012122
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.1327071627
Short name	T807
Test name
Test status
Simulation time	360168010 ps
CPU time	33.8 seconds
Started	Jun 26 04:42:38 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	251224 kb
Host	smart-cbdad584-7dae-42bf-bf6e-1b3f930fd651
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327071627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1327071627
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.3691463723
Short name	T372
Test name
Test status
Simulation time	376390389 ps
CPU time	8.17 seconds
Started	Jun 26 04:42:39 PM PDT 24
Finished	Jun 26 04:42:50 PM PDT 24
Peak memory	251184 kb
Host	smart-e57ec3af-43e1-423f-9426-7e5ca1ba7491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691463723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3691463723
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.314018522
Short name	T361
Test name
Test status
Simulation time	6948489596 ps
CPU time	98.11 seconds
Started	Jun 26 04:42:41 PM PDT 24
Finished	Jun 26 04:44:22 PM PDT 24
Peak memory	287948 kb
Host	smart-adc3629c-1a0d-47a2-8347-6aa9b3899cb8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314018522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.314018522
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.221953776
Short name	T117
Test name
Test status
Simulation time	460145214768 ps
CPU time	1587.54 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 05:09:12 PM PDT 24
Peak memory	497152 kb
Host	smart-e02a404f-c7d9-4b08-9583-d883c91310cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=221953776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.221953776
Directory	/workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3543003470
Short name	T523
Test name
Test status
Simulation time	44576074 ps
CPU time	0.81 seconds
Started	Jun 26 04:42:36 PM PDT 24
Finished	Jun 26 04:42:39 PM PDT 24
Peak memory	209208 kb
Host	smart-6af6e9a5-6f9c-4abd-b064-58440afbfc39
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543003470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.3543003470
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.801132420
Short name	T86
Test name
Test status
Simulation time	23242583 ps
CPU time	1 seconds
Started	Jun 26 04:42:44 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	209260 kb
Host	smart-9fea0071-8489-471b-a602-a99f8dec0a66
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801132420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.801132420
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.2468377370
Short name	T207
Test name
Test status
Simulation time	565012222 ps
CPU time	11.57 seconds
Started	Jun 26 04:42:41 PM PDT 24
Finished	Jun 26 04:42:55 PM PDT 24
Peak memory	226348 kb
Host	smart-bbbd210a-ad46-48cc-835f-e641c6504861
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468377370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2468377370
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.2645667183
Short name	T688
Test name
Test status
Simulation time	41350511 ps
CPU time	1.21 seconds
Started	Jun 26 04:42:41 PM PDT 24
Finished	Jun 26 04:42:45 PM PDT 24
Peak memory	217416 kb
Host	smart-d6ee8816-8fe9-44d5-9445-85594608daa0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645667183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2645667183
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.1540379232
Short name	T627
Test name
Test status
Simulation time	135954427 ps
CPU time	2.06 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	218500 kb
Host	smart-762827ac-65e3-4fd0-8752-6518f55851c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540379232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1540379232
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.23741973
Short name	T175
Test name
Test status
Simulation time	1180245514 ps
CPU time	17.39 seconds
Started	Jun 26 04:42:41 PM PDT 24
Finished	Jun 26 04:43:01 PM PDT 24
Peak memory	219196 kb
Host	smart-bb24d836-d44b-43e4-81ec-f9d2f0a7af1d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.23741973
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.1152763930
Short name	T790
Test name
Test status
Simulation time	1023613627 ps
CPU time	24.36 seconds
Started	Jun 26 04:42:40 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	218532 kb
Host	smart-b07aedab-c99e-4845-b6df-678f4e8bcf67
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152763930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.1152763930
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.2942911173
Short name	T539
Test name
Test status
Simulation time	387554422 ps
CPU time	11.59 seconds
Started	Jun 26 04:42:43 PM PDT 24
Finished	Jun 26 04:42:56 PM PDT 24
Peak memory	218504 kb
Host	smart-57fd17ca-9406-40bf-9382-8809da2b7c35
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942911173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 2942911173
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.1728429548
Short name	T47
Test name
Test status
Simulation time	315737582 ps
CPU time	13.06 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 04:42:57 PM PDT 24
Peak memory	226308 kb
Host	smart-186b5601-d367-4975-b8d2-17c43cd051cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728429548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1728429548
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.2954723388
Short name	T72
Test name
Test status
Simulation time	35207112 ps
CPU time	2.45 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 04:42:47 PM PDT 24
Peak memory	214740 kb
Host	smart-ed3e1c5c-af80-4b27-9c73-7693725bea74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954723388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2954723388
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.2641356226
Short name	T624
Test name
Test status
Simulation time	236375079 ps
CPU time	31.81 seconds
Started	Jun 26 04:42:43 PM PDT 24
Finished	Jun 26 04:43:17 PM PDT 24
Peak memory	251236 kb
Host	smart-f929ce64-59aa-4aee-8699-cb0c88b46004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641356226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2641356226
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.3679425756
Short name	T599
Test name
Test status
Simulation time	56146934 ps
CPU time	9.1 seconds
Started	Jun 26 04:42:41 PM PDT 24
Finished	Jun 26 04:42:53 PM PDT 24
Peak memory	251200 kb
Host	smart-9eee6d8f-be9b-46bc-a9b6-f81398db0711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679425756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3679425756
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.807158377
Short name	T36
Test name
Test status
Simulation time	4561176639 ps
CPU time	89.43 seconds
Started	Jun 26 04:42:44 PM PDT 24
Finished	Jun 26 04:44:15 PM PDT 24
Peak memory	251260 kb
Host	smart-84e45ec4-5c19-4b8a-91dc-f09e47c88d14
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807158377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.807158377
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2313051106
Short name	T152
Test name
Test status
Simulation time	79509639930 ps
CPU time	2739.4 seconds
Started	Jun 26 04:42:43 PM PDT 24
Finished	Jun 26 05:28:25 PM PDT 24
Peak memory	693776 kb
Host	smart-1ab01e2a-1e93-425e-a2b2-ff4646b6efb2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2313051106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2313051106
Directory	/workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1019630801
Short name	T603
Test name
Test status
Simulation time	20081636 ps
CPU time	0.94 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 04:42:46 PM PDT 24
Peak memory	218168 kb
Host	smart-baf906f6-5fe9-41fe-a78a-7ea513db70f7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019630801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1019630801
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.1132905763
Short name	T376
Test name
Test status
Simulation time	50477808 ps
CPU time	1.1 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:42:53 PM PDT 24
Peak memory	208448 kb
Host	smart-1946742a-5b44-4ef5-b669-27d45fda5ea3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132905763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1132905763
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.2880259554
Short name	T470
Test name
Test status
Simulation time	290277008 ps
CPU time	13.86 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	218520 kb
Host	smart-f0e2a7c2-9812-411d-b47a-61b43a53d2be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880259554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2880259554
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.898693023
Short name	T22
Test name
Test status
Simulation time	4372378763 ps
CPU time	11.13 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:43:04 PM PDT 24
Peak memory	217976 kb
Host	smart-b6911f5e-8e3c-482a-be6d-1c5741b5acbf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898693023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.898693023
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.124518118
Short name	T834
Test name
Test status
Simulation time	58652852 ps
CPU time	1.83 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:42:58 PM PDT 24
Peak memory	218492 kb
Host	smart-9043c088-b9db-4321-8a90-dad5e857fdef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124518118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.124518118
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.993648296
Short name	T580
Test name
Test status
Simulation time	1166433865 ps
CPU time	12.54 seconds
Started	Jun 26 04:42:47 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	226432 kb
Host	smart-b43464a4-e604-4033-88bc-b9476f4be2bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993648296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.993648296
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.1459963424
Short name	T327
Test name
Test status
Simulation time	351602698 ps
CPU time	11.2 seconds
Started	Jun 26 04:42:50 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	218496 kb
Host	smart-1a4ad708-423e-46ea-ac34-da0b953e50af
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459963424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d igest.1459963424
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.1349922380
Short name	T518
Test name
Test status
Simulation time	409854176 ps
CPU time	13.99 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	218516 kb
Host	smart-0799f3f3-8f42-4ba2-9302-6a5b57f7559d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349922380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 1349922380
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.2357258928
Short name	T235
Test name
Test status
Simulation time	570956884 ps
CPU time	14.47 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	226324 kb
Host	smart-dce7f750-b299-4dec-96e2-29865f936240
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357258928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2357258928
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.851493599
Short name	T731
Test name
Test status
Simulation time	167157029 ps
CPU time	2.26 seconds
Started	Jun 26 04:42:43 PM PDT 24
Finished	Jun 26 04:42:47 PM PDT 24
Peak memory	223072 kb
Host	smart-51185969-4364-424a-b2db-9b20b584b667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851493599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.851493599
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.125270222
Short name	T100
Test name
Test status
Simulation time	249433952 ps
CPU time	33.83 seconds
Started	Jun 26 04:42:46 PM PDT 24
Finished	Jun 26 04:43:22 PM PDT 24
Peak memory	251232 kb
Host	smart-90a7e40e-3f1b-49d1-b448-23df1c9792ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125270222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.125270222
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.633485887
Short name	T497
Test name
Test status
Simulation time	54331569 ps
CPU time	3.26 seconds
Started	Jun 26 04:42:45 PM PDT 24
Finished	Jun 26 04:42:50 PM PDT 24
Peak memory	226652 kb
Host	smart-4986e65a-f1b8-4bc3-95f4-b7e59b060038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633485887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.633485887
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.3460422191
Short name	T583
Test name
Test status
Simulation time	5049286605 ps
CPU time	104.65 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:44:41 PM PDT 24
Peak memory	276464 kb
Host	smart-17c56a81-2e46-4b9f-aaf9-cba125ae5d58
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460422191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.3460422191
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1839169339
Short name	T93
Test name
Test status
Simulation time	170041554564 ps
CPU time	332.08 seconds
Started	Jun 26 04:42:50 PM PDT 24
Finished	Jun 26 04:48:26 PM PDT 24
Peak memory	277796 kb
Host	smart-d12ad57e-d4f2-47e7-b9ae-a705e1ce3043
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1839169339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1839169339
Directory	/workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2792731264
Short name	T839
Test name
Test status
Simulation time	19155164 ps
CPU time	0.92 seconds
Started	Jun 26 04:42:42 PM PDT 24
Finished	Jun 26 04:42:45 PM PDT 24
Peak memory	209356 kb
Host	smart-fdaf586f-ec1d-4c46-a7f0-fb1783a66b9a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792731264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c trl_volatile_unlock_smoke.2792731264
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.3830415334
Short name	T355
Test name
Test status
Simulation time	16106158 ps
CPU time	1.03 seconds
Started	Jun 26 04:42:50 PM PDT 24
Finished	Jun 26 04:42:56 PM PDT 24
Peak memory	209400 kb
Host	smart-5ff0a4e6-0f9c-48ae-b9e6-21989dcd54a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830415334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3830415334
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.1144160188
Short name	T862
Test name
Test status
Simulation time	573597301 ps
CPU time	14.52 seconds
Started	Jun 26 04:42:47 PM PDT 24
Finished	Jun 26 04:43:04 PM PDT 24
Peak memory	218540 kb
Host	smart-8c1d5d8e-cb38-4bde-82e3-ad2bf2f40ead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144160188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1144160188
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.567389264
Short name	T23
Test name
Test status
Simulation time	438468153 ps
CPU time	6.4 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:43:03 PM PDT 24
Peak memory	217668 kb
Host	smart-0efc11bd-9ddc-471a-9106-94657a8029b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567389264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.567389264
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.759393871
Short name	T438
Test name
Test status
Simulation time	71668188 ps
CPU time	2.97 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	218524 kb
Host	smart-012f56f4-5ac8-4ead-9d4c-67bb64a637de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759393871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.759393871
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.2974066282
Short name	T704
Test name
Test status
Simulation time	4027915148 ps
CPU time	12.41 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:04 PM PDT 24
Peak memory	220528 kb
Host	smart-d31ff9bc-766d-47a3-b76a-b68082975d11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974066282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2974066282
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.3937734640
Short name	T161
Test name
Test status
Simulation time	1945571007 ps
CPU time	14.61 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	218484 kb
Host	smart-85dc7488-30f7-479a-b796-35123a3eca33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937734640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d igest.3937734640
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.1756222167
Short name	T264
Test name
Test status
Simulation time	444192084 ps
CPU time	13.83 seconds
Started	Jun 26 04:42:50 PM PDT 24
Finished	Jun 26 04:43:08 PM PDT 24
Peak memory	218448 kb
Host	smart-f4771776-7dd7-4721-9cba-c57c14df1e40
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756222167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 1756222167
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.2136696177
Short name	T836
Test name
Test status
Simulation time	309773282 ps
CPU time	7.55 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:09 PM PDT 24
Peak memory	224860 kb
Host	smart-cc237b7e-8890-4ab2-8d5b-f7bb9091eab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136696177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2136696177
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.703171931
Short name	T768
Test name
Test status
Simulation time	58534024 ps
CPU time	2.13 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:42:54 PM PDT 24
Peak memory	214424 kb
Host	smart-6236d2ba-f249-4e59-ac73-853c8657f4b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703171931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.703171931
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.2704930465
Short name	T644
Test name
Test status
Simulation time	1013587274 ps
CPU time	30.36 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:22 PM PDT 24
Peak memory	251228 kb
Host	smart-e026ebd1-c79c-4175-bc07-d6a3894d88a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704930465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2704930465
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.1398741085
Short name	T394
Test name
Test status
Simulation time	318114340 ps
CPU time	7.57 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	249780 kb
Host	smart-0078e6e8-e1b9-49fa-9017-db1fc9783f8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398741085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1398741085
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.1019593927
Short name	T717
Test name
Test status
Simulation time	4108422053 ps
CPU time	24.92 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:43:17 PM PDT 24
Peak memory	226320 kb
Host	smart-90ed310e-7212-4660-97c6-724fe411c14d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019593927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.1019593927
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.726212087
Short name	T30
Test name
Test status
Simulation time	14270429 ps
CPU time	0.95 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:42:53 PM PDT 24
Peak memory	209236 kb
Host	smart-5b9cc1d7-c5cf-4bd9-be22-d2cdcc1a6203
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726212087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct rl_volatile_unlock_smoke.726212087
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.1876644251
Short name	T541
Test name
Test status
Simulation time	52025493 ps
CPU time	1.04 seconds
Started	Jun 26 04:41:00 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	209252 kb
Host	smart-530cdb0e-b068-4b31-8070-d9e3d6b36b24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876644251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1876644251
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.440764860
Short name	T302
Test name
Test status
Simulation time	31658919 ps
CPU time	0.92 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:01 PM PDT 24
Peak memory	209244 kb
Host	smart-c78163b2-7287-4018-8c77-02cd4a01bf8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440764860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.440764860
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.2770757072
Short name	T227
Test name
Test status
Simulation time	1221397640 ps
CPU time	8.75 seconds
Started	Jun 26 04:41:00 PM PDT 24
Finished	Jun 26 04:41:14 PM PDT 24
Peak memory	218552 kb
Host	smart-2bae5344-a885-4815-a699-02b1b40a3a5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770757072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2770757072
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.4206967667
Short name	T745
Test name
Test status
Simulation time	431950598 ps
CPU time	5.28 seconds
Started	Jun 26 04:40:54 PM PDT 24
Finished	Jun 26 04:41:07 PM PDT 24
Peak memory	217428 kb
Host	smart-938a03a5-cac7-487e-ad28-9978daa5c776
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206967667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4206967667
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.1644247808
Short name	T703
Test name
Test status
Simulation time	1733086228 ps
CPU time	24.91 seconds
Started	Jun 26 04:42:00 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	218468 kb
Host	smart-4a39c1a8-52e5-46a6-ba45-dfd07f5fd379
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644247808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.1644247808
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.1758946601
Short name	T410
Test name
Test status
Simulation time	219166590 ps
CPU time	5.7 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:10 PM PDT 24
Peak memory	217820 kb
Host	smart-18444e86-caf1-4857-9005-a75fdd7e89c5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758946601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1 758946601
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1448914979
Short name	T653
Test name
Test status
Simulation time	121102628 ps
CPU time	4.39 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:41:09 PM PDT 24
Peak memory	218472 kb
Host	smart-7e742bb0-69e7-49c1-8814-d984f2100b87
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448914979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.1448914979
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.315841654
Short name	T556
Test name
Test status
Simulation time	5281465111 ps
CPU time	21.23 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:23 PM PDT 24
Peak memory	217840 kb
Host	smart-da27b961-9015-480d-8924-5706bedb882b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315841654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j tag_regwen_during_op.315841654
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.2949801016
Short name	T17
Test name
Test status
Simulation time	882780175 ps
CPU time	6.44 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:08 PM PDT 24
Peak memory	217784 kb
Host	smart-10604b55-d0b6-4f37-a5bd-c86254b974eb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949801016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 2949801016
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4183424886
Short name	T393
Test name
Test status
Simulation time	1689575075 ps
CPU time	55.64 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:42:00 PM PDT 24
Peak memory	276292 kb
Host	smart-31b59442-a812-4d1d-b98c-1dc19a9300aa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183424886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.4183424886
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2366428824
Short name	T218
Test name
Test status
Simulation time	883071814 ps
CPU time	15.89 seconds
Started	Jun 26 04:40:54 PM PDT 24
Finished	Jun 26 04:41:17 PM PDT 24
Peak memory	246288 kb
Host	smart-3b9eb787-2c83-4911-82d8-09f1bb7e771b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366428824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.2366428824
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.2289802321
Short name	T708
Test name
Test status
Simulation time	26836021 ps
CPU time	1.96 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:05 PM PDT 24
Peak memory	218524 kb
Host	smart-5c154b9a-7141-4021-ad4e-f9e5817fe58b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289802321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2289802321
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.311357560
Short name	T27
Test name
Test status
Simulation time	498349068 ps
CPU time	17.05 seconds
Started	Jun 26 04:40:51 PM PDT 24
Finished	Jun 26 04:41:15 PM PDT 24
Peak memory	217968 kb
Host	smart-985af4f7-f68c-4ab5-a269-a6c40dbe49d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311357560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.311357560
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.3326311082
Short name	T101
Test name
Test status
Simulation time	414890761 ps
CPU time	22.77 seconds
Started	Jun 26 04:41:02 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	269308 kb
Host	smart-cb3043c9-3611-4427-8413-567c07d9b388
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326311082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3326311082
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.2343119690
Short name	T426
Test name
Test status
Simulation time	1282405069 ps
CPU time	13.94 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:16 PM PDT 24
Peak memory	219748 kb
Host	smart-a4a1e248-f050-4cbb-845e-651e201842e4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343119690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2343119690
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.2175365024
Short name	T667
Test name
Test status
Simulation time	773784343 ps
CPU time	16.62 seconds
Started	Jun 26 04:40:56 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	218472 kb
Host	smart-9cf744d2-5e65-42a3-80b2-cd2e6090229f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175365024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.2175365024
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.3198558481
Short name	T629
Test name
Test status
Simulation time	708004149 ps
CPU time	13.2 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:13 PM PDT 24
Peak memory	218488 kb
Host	smart-9bc5e13c-5345-4e4d-ac9c-06c000dda6b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198558481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3 198558481
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.3871217954
Short name	T529
Test name
Test status
Simulation time	496658976 ps
CPU time	9.78 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:41:09 PM PDT 24
Peak memory	226304 kb
Host	smart-988ab634-c089-47ab-96cd-7e039d1d72ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871217954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3871217954
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.3866899365
Short name	T82
Test name
Test status
Simulation time	19148267 ps
CPU time	1.19 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:03 PM PDT 24
Peak memory	217924 kb
Host	smart-32a8029d-787f-464c-aac3-c52a92e4f3d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866899365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3866899365
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.2302949964
Short name	T569
Test name
Test status
Simulation time	937043925 ps
CPU time	25.99 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	251232 kb
Host	smart-7df62b42-3054-4d80-a125-fd3ce85b21b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302949964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2302949964
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.219222157
Short name	T837
Test name
Test status
Simulation time	59700140 ps
CPU time	7.82 seconds
Started	Jun 26 04:40:51 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	251040 kb
Host	smart-cc787d59-512a-4971-9185-628016762a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219222157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.219222157
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.585708640
Short name	T304
Test name
Test status
Simulation time	12043049627 ps
CPU time	109.92 seconds
Started	Jun 26 04:40:52 PM PDT 24
Finished	Jun 26 04:42:50 PM PDT 24
Peak memory	283992 kb
Host	smart-db32f5d5-eb56-490e-8ba1-9c0f151560d2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585708640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.585708640
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.867567814
Short name	T825
Test name
Test status
Simulation time	52054037 ps
CPU time	1.09 seconds
Started	Jun 26 04:40:55 PM PDT 24
Finished	Jun 26 04:41:03 PM PDT 24
Peak memory	212132 kb
Host	smart-0e669966-901b-4bbd-9e1d-701491f6e3cc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867567814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_volatile_unlock_smoke.867567814
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.2282176865
Short name	T829
Test name
Test status
Simulation time	17662414 ps
CPU time	0.91 seconds
Started	Jun 26 04:42:56 PM PDT 24
Finished	Jun 26 04:43:01 PM PDT 24
Peak memory	209272 kb
Host	smart-b1d09d5a-151f-41e1-9b03-66e4b5583105
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282176865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2282176865
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.4015647713
Short name	T222
Test name
Test status
Simulation time	1962324723 ps
CPU time	14.3 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	218532 kb
Host	smart-1b6bd1d7-9172-47cc-b471-c324c054147b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015647713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4015647713
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.2218225825
Short name	T806
Test name
Test status
Simulation time	72634127 ps
CPU time	1.77 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:42:55 PM PDT 24
Peak memory	217324 kb
Host	smart-2d4993cf-7ccf-4cba-944a-047586247687
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218225825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2218225825
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.998740773
Short name	T291
Test name
Test status
Simulation time	602009652 ps
CPU time	3.64 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:42:56 PM PDT 24
Peak memory	218584 kb
Host	smart-ced86add-e7a6-4323-b1c1-0f68d724f389
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998740773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.998740773
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.3894471230
Short name	T407
Test name
Test status
Simulation time	1834811431 ps
CPU time	12.84 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:43:09 PM PDT 24
Peak memory	226368 kb
Host	smart-764d11d1-370d-451f-8d32-0ea47844be5f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894471230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3894471230
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.626085703
Short name	T26
Test name
Test status
Simulation time	5448216381 ps
CPU time	11.91 seconds
Started	Jun 26 04:42:51 PM PDT 24
Finished	Jun 26 04:43:08 PM PDT 24
Peak memory	218548 kb
Host	smart-9bf9ec75-e186-42c4-875d-654037a479d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626085703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di gest.626085703
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.2626157419
Short name	T673
Test name
Test status
Simulation time	1203732807 ps
CPU time	12.5 seconds
Started	Jun 26 04:42:47 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	218584 kb
Host	smart-c23f90a6-fd6b-43ec-b867-22a58644cf27
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626157419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 2626157419
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.320893185
Short name	T595
Test name
Test status
Simulation time	394043778 ps
CPU time	16.3 seconds
Started	Jun 26 04:42:48 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	226476 kb
Host	smart-cdc674b9-0ea0-4751-aa6f-5b9a6f5c5d6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320893185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.320893185
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.4019478114
Short name	T399
Test name
Test status
Simulation time	87046069 ps
CPU time	3.35 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	223420 kb
Host	smart-7ef4676c-1ad8-4bd7-8ac0-09c7ce81deb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019478114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4019478114
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.746229492
Short name	T798
Test name
Test status
Simulation time	655005120 ps
CPU time	19.54 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	251232 kb
Host	smart-853738a5-9212-492d-af54-d6e05cfeebb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746229492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.746229492
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.983325154
Short name	T173
Test name
Test status
Simulation time	177165979 ps
CPU time	8.59 seconds
Started	Jun 26 04:42:49 PM PDT 24
Finished	Jun 26 04:43:01 PM PDT 24
Peak memory	251136 kb
Host	smart-ba83d2ea-713e-4e06-b851-ec77c795d3ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983325154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.983325154
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.4107103047
Short name	T459
Test name
Test status
Simulation time	4126260418 ps
CPU time	114.83 seconds
Started	Jun 26 04:42:58 PM PDT 24
Finished	Jun 26 04:44:57 PM PDT 24
Peak memory	284072 kb
Host	smart-a9c70c05-ab50-423d-a3f4-97809968f9cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107103047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.4107103047
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1953877079
Short name	T818
Test name
Test status
Simulation time	31771978989 ps
CPU time	663.37 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:54:05 PM PDT 24
Peak memory	448152 kb
Host	smart-ef8a6207-48cb-4e5e-9994-997a166a1a05
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1953877079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1953877079
Directory	/workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.811169614
Short name	T456
Test name
Test status
Simulation time	129714084 ps
CPU time	0.8 seconds
Started	Jun 26 04:42:50 PM PDT 24
Finished	Jun 26 04:42:55 PM PDT 24
Peak memory	209044 kb
Host	smart-3072a53c-ad74-4c10-9c6a-d8603fa6ec2c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811169614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct rl_volatile_unlock_smoke.811169614
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.158026713
Short name	T265
Test name
Test status
Simulation time	31785829 ps
CPU time	0.95 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	209244 kb
Host	smart-4345fab9-4800-445e-9689-1ce2fc20f1f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158026713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.158026713
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.2683944914
Short name	T242
Test name
Test status
Simulation time	627822767 ps
CPU time	12.5 seconds
Started	Jun 26 04:42:54 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	218528 kb
Host	smart-ae5e4520-5b08-4f57-a68a-13b3d111e1e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683944914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2683944914
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.866082736
Short name	T347
Test name
Test status
Simulation time	313914582 ps
CPU time	2.34 seconds
Started	Jun 26 04:42:53 PM PDT 24
Finished	Jun 26 04:43:00 PM PDT 24
Peak memory	217628 kb
Host	smart-9ed7a3ac-82d1-422e-aa92-b1f4d12b0c4c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866082736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.866082736
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.4134872208
Short name	T382
Test name
Test status
Simulation time	370891762 ps
CPU time	3.52 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:43:00 PM PDT 24
Peak memory	218460 kb
Host	smart-df8d4b18-6a69-4bd3-853e-e3c54a2a1260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134872208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4134872208
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.1378160705
Short name	T411
Test name
Test status
Simulation time	2479110630 ps
CPU time	11.13 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	220420 kb
Host	smart-c4865ed8-6abf-405c-8642-64743d7f5f67
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378160705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1378160705
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.1406933093
Short name	T540
Test name
Test status
Simulation time	2240957263 ps
CPU time	14.21 seconds
Started	Jun 26 04:42:53 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	218556 kb
Host	smart-b33fdf41-16a9-4ff0-8c09-d472486ca7c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406933093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.1406933093
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.1028311826
Short name	T59
Test name
Test status
Simulation time	420657746 ps
CPU time	11.53 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	218440 kb
Host	smart-819831f7-18db-4265-a829-fe4b390e8b7d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028311826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 1028311826
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.3964185474
Short name	T634
Test name
Test status
Simulation time	3694815330 ps
CPU time	14.02 seconds
Started	Jun 26 04:42:59 PM PDT 24
Finished	Jun 26 04:43:18 PM PDT 24
Peak memory	226200 kb
Host	smart-d2569615-0691-4b23-9bae-83c442cfa7c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964185474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3964185474
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.4066910758
Short name	T800
Test name
Test status
Simulation time	41977498 ps
CPU time	1.74 seconds
Started	Jun 26 04:42:53 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	214320 kb
Host	smart-8fb81642-95ab-4c1a-a20b-fc8cf56a4db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066910758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.4066910758
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.3281674431
Short name	T174
Test name
Test status
Simulation time	668940494 ps
CPU time	26.32 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:43:25 PM PDT 24
Peak memory	251284 kb
Host	smart-6bc7d0c6-e3b3-4c5c-80ab-0769cfaeec2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281674431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3281674431
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.1805449187
Short name	T564
Test name
Test status
Simulation time	1030603202 ps
CPU time	8.01 seconds
Started	Jun 26 04:42:54 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	251224 kb
Host	smart-28e3f900-bc49-4935-9943-1cf35eb86702
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805449187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1805449187
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.1958211996
Short name	T74
Test name
Test status
Simulation time	45334797568 ps
CPU time	338.3 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:48:37 PM PDT 24
Peak memory	275176 kb
Host	smart-05fc5864-7ac8-4c79-94a6-3964093effc2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958211996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.1958211996
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3462749223
Short name	T536
Test name
Test status
Simulation time	12268673 ps
CPU time	1.08 seconds
Started	Jun 26 04:42:58 PM PDT 24
Finished	Jun 26 04:43:03 PM PDT 24
Peak memory	212228 kb
Host	smart-0964ddf0-da47-4837-9ad8-fcf4f665c95e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462749223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.3462749223
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.328482424
Short name	T820
Test name
Test status
Simulation time	22101294 ps
CPU time	1.21 seconds
Started	Jun 26 04:42:56 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	209248 kb
Host	smart-d1294ae4-aaff-4db4-a3ea-3f2138724a9e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328482424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.328482424
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.1531736127
Short name	T662
Test name
Test status
Simulation time	6928980427 ps
CPU time	11.4 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	218656 kb
Host	smart-66152fd4-13fb-4a19-842b-8466fde92fa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531736127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1531736127
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.4034819865
Short name	T531
Test name
Test status
Simulation time	3424508207 ps
CPU time	4.92 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	217924 kb
Host	smart-64b9c0e2-e26c-4438-93ff-1d1e36a116f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034819865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4034819865
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.852038610
Short name	T466
Test name
Test status
Simulation time	121989919 ps
CPU time	3.22 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:43:02 PM PDT 24
Peak memory	218488 kb
Host	smart-397cdb05-1642-494b-a4ea-9e9c6c55a1d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852038610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.852038610
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.868815542
Short name	T475
Test name
Test status
Simulation time	572542181 ps
CPU time	24.1 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	226336 kb
Host	smart-9f3dd0c1-c25b-462c-9906-1d16575d8684
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868815542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.868815542
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.233235496
Short name	T577
Test name
Test status
Simulation time	2010514810 ps
CPU time	12.8 seconds
Started	Jun 26 04:42:54 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	218500 kb
Host	smart-68952aad-cf63-444c-9cf9-9347a37f233c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233235496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di gest.233235496
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.3173238898
Short name	T333
Test name
Test status
Simulation time	625284664 ps
CPU time	11.49 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:12 PM PDT 24
Peak memory	218480 kb
Host	smart-14d9c21e-fa7a-4988-825d-4a4889acb992
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173238898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux. 3173238898
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.2854756168
Short name	T381
Test name
Test status
Simulation time	1034408918 ps
CPU time	10.98 seconds
Started	Jun 26 04:42:53 PM PDT 24
Finished	Jun 26 04:43:08 PM PDT 24
Peak memory	226048 kb
Host	smart-5b921e12-3be9-4dff-8f5a-e99b82ea5082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854756168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2854756168
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.286959997
Short name	T343
Test name
Test status
Simulation time	131387573 ps
CPU time	1.94 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:43:01 PM PDT 24
Peak memory	223548 kb
Host	smart-2cc916cd-734e-422a-9e92-dd45851cd716
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286959997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.286959997
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.3304906291
Short name	T217
Test name
Test status
Simulation time	766266393 ps
CPU time	25.6 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:27 PM PDT 24
Peak memory	251200 kb
Host	smart-c92c9e2f-6910-4738-9d39-b063809df2b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304906291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3304906291
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.25210365
Short name	T256
Test name
Test status
Simulation time	813100283 ps
CPU time	6.45 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:08 PM PDT 24
Peak memory	250740 kb
Host	smart-98e2818c-25e0-4033-a952-127cbfacbc27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25210365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.25210365
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.2766946988
Short name	T795
Test name
Test status
Simulation time	8406244262 ps
CPU time	49.17 seconds
Started	Jun 26 04:42:59 PM PDT 24
Finished	Jun 26 04:43:53 PM PDT 24
Peak memory	251304 kb
Host	smart-395eb896-9f78-4a99-85f5-639ec8ce98e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766946988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.2766946988
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3129179598
Short name	T157
Test name
Test status
Simulation time	20076954060 ps
CPU time	571.77 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:52:33 PM PDT 24
Peak memory	300532 kb
Host	smart-96f582aa-e3d4-497f-aeb2-b16b99a61a01
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3129179598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3129179598
Directory	/workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3653102123
Short name	T317
Test name
Test status
Simulation time	27224168 ps
CPU time	0.95 seconds
Started	Jun 26 04:42:54 PM PDT 24
Finished	Jun 26 04:42:59 PM PDT 24
Peak memory	212120 kb
Host	smart-2b4d09dc-bc88-4b35-a8d3-af122ce9ca8f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653102123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.3653102123
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.4131366360
Short name	T324
Test name
Test status
Simulation time	21191465 ps
CPU time	0.95 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	209248 kb
Host	smart-a0465991-e166-456c-bb63-69d27386f6aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131366360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4131366360
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.2079134054
Short name	T799
Test name
Test status
Simulation time	344940413 ps
CPU time	12.37 seconds
Started	Jun 26 04:42:55 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	218536 kb
Host	smart-c55eb438-e81b-416c-9406-af365e1b77cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079134054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2079134054
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.56950871
Short name	T754
Test name
Test status
Simulation time	157016816 ps
CPU time	2.71 seconds
Started	Jun 26 04:42:56 PM PDT 24
Finished	Jun 26 04:43:03 PM PDT 24
Peak memory	217420 kb
Host	smart-2d692ecd-d622-466d-be16-1ce0d73c5938
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56950871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.56950871
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.1102729872
Short name	T212
Test name
Test status
Simulation time	51953531 ps
CPU time	1.88 seconds
Started	Jun 26 04:42:52 PM PDT 24
Finished	Jun 26 04:42:58 PM PDT 24
Peak memory	218528 kb
Host	smart-7f36d52b-6c63-433c-8381-2cf2914c7f12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102729872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1102729872
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.1272990518
Short name	T413
Test name
Test status
Simulation time	515626205 ps
CPU time	11.28 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	219196 kb
Host	smart-cfc2ed89-4e0b-45bb-86ba-8d51ea76f5e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272990518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1272990518
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.1903313485
Short name	T424
Test name
Test status
Simulation time	1100427565 ps
CPU time	12.74 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	218548 kb
Host	smart-a9bd8f59-582d-480b-834a-48da1b5259fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903313485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.1903313485
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.4105114402
Short name	T268
Test name
Test status
Simulation time	1805689408 ps
CPU time	11.33 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:43:18 PM PDT 24
Peak memory	226352 kb
Host	smart-1b0aca91-329f-4197-b3f6-e7440aa11f32
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105114402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux. 4105114402
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.1916538800
Short name	T821
Test name
Test status
Simulation time	266795943 ps
CPU time	8.36 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:10 PM PDT 24
Peak memory	226344 kb
Host	smart-f4db5f0b-803f-42d4-b091-a835f94c6d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916538800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1916538800
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.3822945151
Short name	T258
Test name
Test status
Simulation time	204996156 ps
CPU time	1.56 seconds
Started	Jun 26 04:42:59 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	223508 kb
Host	smart-029363ce-bc09-4362-bbba-2c9ddb32fe1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822945151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3822945151
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.3765243260
Short name	T554
Test name
Test status
Simulation time	1249304535 ps
CPU time	31.45 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:32 PM PDT 24
Peak memory	251208 kb
Host	smart-b1bce68e-4c61-4fda-a0c7-f7dfad18b685
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765243260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3765243260
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.304424911
Short name	T805
Test name
Test status
Simulation time	49189326 ps
CPU time	3.18 seconds
Started	Jun 26 04:42:57 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	222668 kb
Host	smart-130faa8c-79bb-48c4-9e8b-22b2b9cd1ae3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304424911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.304424911
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.270699632
Short name	T14
Test name
Test status
Simulation time	46648101824 ps
CPU time	307.17 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:48:14 PM PDT 24
Peak memory	272460 kb
Host	smart-57f445e5-d582-4d5a-a3a0-4ab03ccf8945
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270699632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.270699632
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1787297760
Short name	T38
Test name
Test status
Simulation time	12132306 ps
CPU time	1.13 seconds
Started	Jun 26 04:42:53 PM PDT 24
Finished	Jun 26 04:42:58 PM PDT 24
Peak memory	212480 kb
Host	smart-d100ccbb-7cc5-4f45-a08e-d4ee5be24b89
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787297760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.1787297760
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.1067134329
Short name	T285
Test name
Test status
Simulation time	18835133 ps
CPU time	1.2 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	209336 kb
Host	smart-391c91a6-e84d-4233-ba3e-3b28b359a9ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067134329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1067134329
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.2476824213
Short name	T526
Test name
Test status
Simulation time	465620976 ps
CPU time	13.7 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	218468 kb
Host	smart-f299cde5-b88a-4585-a853-6bffd7ec2a13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476824213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2476824213
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.1505333493
Short name	T752
Test name
Test status
Simulation time	54463915 ps
CPU time	1.3 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	217308 kb
Host	smart-f719df83-9206-45bf-8b95-511830d9d03c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505333493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1505333493
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.2746486193
Short name	T537
Test name
Test status
Simulation time	39435903 ps
CPU time	2.48 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	218528 kb
Host	smart-87104721-59ad-4bf6-af32-1ec8f387513d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746486193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2746486193
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.3494418563
Short name	T350
Test name
Test status
Simulation time	254768833 ps
CPU time	11.4 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	219200 kb
Host	smart-b8cdb8ef-683a-4e60-a2c2-e52d46b440a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494418563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3494418563
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.3765913380
Short name	T369
Test name
Test status
Simulation time	1315600602 ps
CPU time	14.22 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	218484 kb
Host	smart-400a2c10-dbff-41ee-880d-becedbe3d48f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765913380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.3765913380
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.3565562249
Short name	T251
Test name
Test status
Simulation time	774558052 ps
CPU time	9.3 seconds
Started	Jun 26 04:42:59 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	218580 kb
Host	smart-8f91247f-4ef6-4610-86ad-877c44110ced
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565562249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux. 3565562249
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.2606541742
Short name	T408
Test name
Test status
Simulation time	1296600495 ps
CPU time	6.05 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:10 PM PDT 24
Peak memory	225044 kb
Host	smart-d1e77b39-d6ef-46b8-ade3-6c2586333ac1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606541742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2606541742
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.464770354
Short name	T735
Test name
Test status
Simulation time	105591668 ps
CPU time	2 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	218268 kb
Host	smart-37efc877-b1e1-4e02-851e-43eaceba022c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464770354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.464770354
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.2092730057
Short name	T480
Test name
Test status
Simulation time	254899969 ps
CPU time	23.16 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:29 PM PDT 24
Peak memory	251216 kb
Host	smart-4a4ba689-3c98-4afe-ac66-b9eeb208610f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092730057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2092730057
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.756003633
Short name	T676
Test name
Test status
Simulation time	128609745 ps
CPU time	7.79 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:12 PM PDT 24
Peak memory	251248 kb
Host	smart-5b565fc6-f7aa-4e5f-992d-b7840fe7abc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756003633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.756003633
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.1769213563
Short name	T95
Test name
Test status
Simulation time	6858199044 ps
CPU time	116.15 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:45:00 PM PDT 24
Peak memory	276976 kb
Host	smart-f3b7b48b-d4e5-4775-9092-f7a2b1a4b4fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769213563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.1769213563
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4152060161
Short name	T43
Test name
Test status
Simulation time	93271804609 ps
CPU time	268.71 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:47:35 PM PDT 24
Peak memory	267788 kb
Host	smart-9f6691fd-2e7f-4317-a31f-743ef6701bab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4152060161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.4152060161
Directory	/workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2781504229
Short name	T625
Test name
Test status
Simulation time	33747133 ps
CPU time	0.89 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	209324 kb
Host	smart-4fc3bd56-ac61-4ebf-90ca-0b3ebabd0da6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781504229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.2781504229
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.3100840237
Short name	T697
Test name
Test status
Simulation time	56270887 ps
CPU time	0.91 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	209060 kb
Host	smart-81684319-b15b-4f91-b87d-702a3775da6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100840237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3100840237
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.454667625
Short name	T575
Test name
Test status
Simulation time	395864669 ps
CPU time	14.24 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	218532 kb
Host	smart-cf0a7d6b-6cf7-4582-97e6-e4eec922263a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454667625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.454667625
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.2660038731
Short name	T553
Test name
Test status
Simulation time	266518822 ps
CPU time	7.79 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	217572 kb
Host	smart-c76a22eb-d3d2-4a2f-95c0-1515a0a40f0c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660038731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2660038731
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.3680518428
Short name	T110
Test name
Test status
Simulation time	14865213 ps
CPU time	1.41 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	218508 kb
Host	smart-f8ff135c-7f36-42f8-bda0-85b1eaa1befb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680518428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3680518428
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.18803672
Short name	T219
Test name
Test status
Simulation time	3405377239 ps
CPU time	14.09 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:18 PM PDT 24
Peak memory	219256 kb
Host	smart-9b0a5ee0-3e49-407e-bcf0-f9cc15010048
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.18803672
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.1484471302
Short name	T867
Test name
Test status
Simulation time	314465749 ps
CPU time	7.72 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:18 PM PDT 24
Peak memory	218452 kb
Host	smart-262b84a4-678b-4ef1-9917-0030001262ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484471302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.1484471302
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.2706421264
Short name	T740
Test name
Test status
Simulation time	411178639 ps
CPU time	9.98 seconds
Started	Jun 26 04:42:59 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	218480 kb
Host	smart-dbc720a0-0f3b-47fc-bf0a-578560fafe1e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706421264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 2706421264
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.2999884276
Short name	T433
Test name
Test status
Simulation time	417257768 ps
CPU time	8.36 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:18 PM PDT 24
Peak memory	218628 kb
Host	smart-eb131f96-1d49-4be5-9084-97830ab3ff0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999884276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2999884276
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.2652879171
Short name	T80
Test name
Test status
Simulation time	19540078 ps
CPU time	1.31 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	217964 kb
Host	smart-0370c6ff-0b20-4ac1-b58f-3cfda449b956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652879171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2652879171
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.3986002424
Short name	T741
Test name
Test status
Simulation time	276994335 ps
CPU time	24.93 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:29 PM PDT 24
Peak memory	251228 kb
Host	smart-e0193ce9-962e-4480-80c8-98c31d9d7b90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986002424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3986002424
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.239225204
Short name	T272
Test name
Test status
Simulation time	77391274 ps
CPU time	7.22 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	250728 kb
Host	smart-af7a0fec-a5e3-4eda-8681-204ba9f26edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=239225204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.239225204
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.1997434075
Short name	T182
Test name
Test status
Simulation time	27796679406 ps
CPU time	458.5 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:50:49 PM PDT 24
Peak memory	421216 kb
Host	smart-b5c5ebcc-f24e-44d5-8acc-ce05d2fb2ad4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997434075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.1997434075
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.622857034
Short name	T357
Test name
Test status
Simulation time	15579440 ps
CPU time	0.97 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:06 PM PDT 24
Peak memory	213172 kb
Host	smart-01b1a49f-41e5-4d24-a1fa-f03f5a93e61d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622857034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct rl_volatile_unlock_smoke.622857034
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.4183617351
Short name	T571
Test name
Test status
Simulation time	26658046 ps
CPU time	0.86 seconds
Started	Jun 26 04:43:10 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	209092 kb
Host	smart-092f3973-30fd-4733-9539-5e80669cb848
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183617351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4183617351
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.3670035681
Short name	T852
Test name
Test status
Simulation time	4889145153 ps
CPU time	17.09 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:28 PM PDT 24
Peak memory	226348 kb
Host	smart-f4561089-a10a-4e54-b671-dd793afecc26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670035681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3670035681
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.2683508745
Short name	T487
Test name
Test status
Simulation time	366895542 ps
CPU time	4.16 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:10 PM PDT 24
Peak memory	217640 kb
Host	smart-8b3ded1e-0784-493c-a8dd-78d7ac338426
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683508745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2683508745
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.1480866177
Short name	T9
Test name
Test status
Simulation time	17863603 ps
CPU time	1.5 seconds
Started	Jun 26 04:43:01 PM PDT 24
Finished	Jun 26 04:43:07 PM PDT 24
Peak memory	222048 kb
Host	smart-141b2bff-5b06-4d09-9329-b02b6d45ec53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480866177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1480866177
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.2662100666
Short name	T720
Test name
Test status
Simulation time	195719949 ps
CPU time	10.58 seconds
Started	Jun 26 04:43:06 PM PDT 24
Finished	Jun 26 04:43:20 PM PDT 24
Peak memory	226312 kb
Host	smart-1bca8797-274e-43bb-9a60-b6cacdddcf25
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662100666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2662100666
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.1112657079
Short name	T249
Test name
Test status
Simulation time	513498020 ps
CPU time	12.73 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:43:27 PM PDT 24
Peak memory	218492 kb
Host	smart-5068d69e-79f2-41fb-b002-326ed35026c1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112657079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d igest.1112657079
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.3362480636
Short name	T521
Test name
Test status
Simulation time	4449618706 ps
CPU time	13.48 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	226340 kb
Host	smart-0bbaed22-bf60-4f39-bb3d-985b82ce3631
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362480636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux. 3362480636
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.631805033
Short name	T92
Test name
Test status
Simulation time	1363919562 ps
CPU time	8.49 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	226320 kb
Host	smart-b7291e75-7895-417e-bff2-946c3f90d960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631805033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.631805033
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.577703098
Short name	T239
Test name
Test status
Simulation time	224578818 ps
CPU time	2.59 seconds
Started	Jun 26 04:43:03 PM PDT 24
Finished	Jun 26 04:43:09 PM PDT 24
Peak memory	217956 kb
Host	smart-2c138f0a-a71b-452e-ae82-e317f4da7885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577703098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.577703098
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.4263518668
Short name	T753
Test name
Test status
Simulation time	906950471 ps
CPU time	24.13 seconds
Started	Jun 26 04:43:02 PM PDT 24
Finished	Jun 26 04:43:30 PM PDT 24
Peak memory	251212 kb
Host	smart-52edbbb2-c185-4376-b809-df3a77047f09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263518668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4263518668
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.2474022313
Short name	T669
Test name
Test status
Simulation time	82439605 ps
CPU time	6.5 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	247076 kb
Host	smart-566c0423-3715-4db4-8a7b-5303f26ecc34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474022313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2474022313
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.3832499213
Short name	T111
Test name
Test status
Simulation time	16420887695 ps
CPU time	88.51 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:44:41 PM PDT 24
Peak memory	284024 kb
Host	smart-8c7d732e-ef87-4116-82a0-ba8feea26a6b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832499213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.3832499213
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3364990519
Short name	T39
Test name
Test status
Simulation time	13091391 ps
CPU time	0.93 seconds
Started	Jun 26 04:43:00 PM PDT 24
Finished	Jun 26 04:43:05 PM PDT 24
Peak memory	209328 kb
Host	smart-fb9016b0-d468-48cb-93e8-07d3227c1ee2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364990519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.3364990519
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.1756589491
Short name	T87
Test name
Test status
Simulation time	15567371 ps
CPU time	0.95 seconds
Started	Jun 26 04:43:13 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	209336 kb
Host	smart-1cec8642-e9a7-460e-a459-3d7e3b2b9550
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756589491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1756589491
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.2027538267
Short name	T12
Test name
Test status
Simulation time	177663415 ps
CPU time	8.69 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	218536 kb
Host	smart-3c525743-1470-4ddf-a147-64ce8d8191dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027538267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2027538267
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.1012497480
Short name	T503
Test name
Test status
Simulation time	17740557 ps
CPU time	1.44 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	222156 kb
Host	smart-99901172-4850-4f1b-b0d8-d10402f4466f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012497480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1012497480
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.175129629
Short name	T734
Test name
Test status
Simulation time	276575190 ps
CPU time	14.54 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:27 PM PDT 24
Peak memory	226324 kb
Host	smart-6be3d9c3-0378-462f-b39d-545402be5974
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175129629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.175129629
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.813397746
Short name	T555
Test name
Test status
Simulation time	428552109 ps
CPU time	16.32 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	218564 kb
Host	smart-db307fcf-9753-49bf-9cd3-f6069f362926
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813397746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di gest.813397746
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.3369018217
Short name	T718
Test name
Test status
Simulation time	1807007819 ps
CPU time	13.85 seconds
Started	Jun 26 04:43:12 PM PDT 24
Finished	Jun 26 04:43:29 PM PDT 24
Peak memory	226280 kb
Host	smart-47cba8a7-49de-4aec-8204-1d1608340ef5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369018217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 3369018217
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.3763316632
Short name	T589
Test name
Test status
Simulation time	369844208 ps
CPU time	10.2 seconds
Started	Jun 26 04:43:10 PM PDT 24
Finished	Jun 26 04:43:24 PM PDT 24
Peak memory	218664 kb
Host	smart-2ad1e1bd-d379-4361-9034-52ad11be2f15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763316632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3763316632
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.1423290428
Short name	T860
Test name
Test status
Simulation time	49153581 ps
CPU time	3.12 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	218044 kb
Host	smart-6a157bff-c97c-482d-b90d-33d0005b527e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423290428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1423290428
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.367569309
Short name	T215
Test name
Test status
Simulation time	476681358 ps
CPU time	26.31 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:39 PM PDT 24
Peak memory	251212 kb
Host	smart-7b22d770-ba50-47da-8a81-d542f86a9534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367569309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.367569309
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.2514764232
Short name	T711
Test name
Test status
Simulation time	76153409 ps
CPU time	3.75 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	222672 kb
Host	smart-4927127d-4330-48b6-9493-58060306d447
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514764232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2514764232
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.347380353
Short name	T179
Test name
Test status
Simulation time	6445733323 ps
CPU time	142.07 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:45:36 PM PDT 24
Peak memory	279080 kb
Host	smart-b6abb241-2e91-410d-8021-43f20f090dbe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347380353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.347380353
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.75399862
Short name	T356
Test name
Test status
Simulation time	36533584 ps
CPU time	0.9 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:13 PM PDT 24
Peak memory	209184 kb
Host	smart-cc6c48f5-2f87-4cd6-b146-4c828e486989
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75399862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctr l_volatile_unlock_smoke.75399862
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.4082405359
Short name	T680
Test name
Test status
Simulation time	28633579 ps
CPU time	1.07 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	209336 kb
Host	smart-c58336aa-d385-47ba-aed8-14a48f7bc06e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082405359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4082405359
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.114131946
Short name	T527
Test name
Test status
Simulation time	429223819 ps
CPU time	16.01 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:27 PM PDT 24
Peak memory	218520 kb
Host	smart-809f4fd7-e9b1-4995-ae47-de4a29325b88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114131946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.114131946
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.4078654751
Short name	T691
Test name
Test status
Simulation time	3255161072 ps
CPU time	8.25 seconds
Started	Jun 26 04:43:10 PM PDT 24
Finished	Jun 26 04:43:22 PM PDT 24
Peak memory	217868 kb
Host	smart-77461e93-9bb1-400e-a53b-d8fa22163567
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078654751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4078654751
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.2718764248
Short name	T758
Test name
Test status
Simulation time	82538342 ps
CPU time	1.98 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	218528 kb
Host	smart-da59a04e-df83-4523-85cd-da3a5e9a0c12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718764248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2718764248
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.1378957274
Short name	T435
Test name
Test status
Simulation time	836848187 ps
CPU time	14.12 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	226344 kb
Host	smart-de927b97-7156-4ecf-800e-7d367b769637
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378957274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1378957274
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.2232606691
Short name	T460
Test name
Test status
Simulation time	3144137126 ps
CPU time	15.06 seconds
Started	Jun 26 04:43:10 PM PDT 24
Finished	Jun 26 04:43:29 PM PDT 24
Peak memory	218552 kb
Host	smart-1568b293-42f6-4672-b94d-a38ce266cfd8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232606691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.2232606691
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.2262064659
Short name	T811
Test name
Test status
Simulation time	5958776581 ps
CPU time	12.16 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	218544 kb
Host	smart-1873fcdd-e4f6-4a4c-8b08-1c423a06973a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262064659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 2262064659
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.3328553952
Short name	T870
Test name
Test status
Simulation time	365668798 ps
CPU time	8.58 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:22 PM PDT 24
Peak memory	218660 kb
Host	smart-67350beb-a7b3-40c1-8708-964936d0af19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328553952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3328553952
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.587860392
Short name	T423
Test name
Test status
Simulation time	325040463 ps
CPU time	2.86 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:14 PM PDT 24
Peak memory	215060 kb
Host	smart-e2ecaae6-46a0-49f4-8e71-66f998a1a907
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587860392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.587860392
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.3061940174
Short name	T582
Test name
Test status
Simulation time	463959338 ps
CPU time	30.94 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:44 PM PDT 24
Peak memory	251236 kb
Host	smart-2da7957b-9b84-47c5-b8b3-ded0df138d78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061940174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3061940174
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.2594746436
Short name	T377
Test name
Test status
Simulation time	118550365 ps
CPU time	7.62 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:17 PM PDT 24
Peak memory	251232 kb
Host	smart-fe66a57d-6272-42ab-9ce9-3dbdc85b4306
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594746436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2594746436
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.1322595298
Short name	T262
Test name
Test status
Simulation time	10998372662 ps
CPU time	67.61 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:44:19 PM PDT 24
Peak memory	226364 kb
Host	smart-b3dece6f-8ee4-46af-8041-2e4a04c2106a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322595298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.1322595298
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.807036478
Short name	T88
Test name
Test status
Simulation time	7858181797 ps
CPU time	136.31 seconds
Started	Jun 26 04:43:11 PM PDT 24
Finished	Jun 26 04:45:31 PM PDT 24
Peak memory	276344 kb
Host	smart-c201ee7e-1b92-4695-aa2d-807416e0d0ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=807036478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.807036478
Directory	/workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1540325066
Short name	T713
Test name
Test status
Simulation time	13293739 ps
CPU time	0.98 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:11 PM PDT 24
Peak memory	209156 kb
Host	smart-17b1927a-ff16-4c81-86a5-d638b274ac5e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540325066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.1540325066
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.2136056805
Short name	T530
Test name
Test status
Simulation time	115640059 ps
CPU time	1.34 seconds
Started	Jun 26 04:43:15 PM PDT 24
Finished	Jun 26 04:43:19 PM PDT 24
Peak memory	209244 kb
Host	smart-76eda14f-2e0c-49ca-892d-4a929f683f40
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136056805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2136056805
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.3437264738
Short name	T211
Test name
Test status
Simulation time	330667083 ps
CPU time	13.74 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	218844 kb
Host	smart-5cd81cc9-7c53-4a21-b36b-116d03f5e7e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437264738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3437264738
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.1494610853
Short name	T604
Test name
Test status
Simulation time	623235357 ps
CPU time	2.14 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:15 PM PDT 24
Peak memory	217300 kb
Host	smart-a85d9b9d-2ac9-4669-aaed-7622ce38c308
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494610853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1494610853
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.3952253771
Short name	T419
Test name
Test status
Simulation time	188964132 ps
CPU time	3.35 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:16 PM PDT 24
Peak memory	222888 kb
Host	smart-6b107190-0755-425b-80a8-c21fe3dd0fc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952253771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3952253771
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.2420774985
Short name	T387
Test name
Test status
Simulation time	1566757039 ps
CPU time	12.43 seconds
Started	Jun 26 04:43:16 PM PDT 24
Finished	Jun 26 04:43:32 PM PDT 24
Peak memory	226268 kb
Host	smart-4347b137-91bb-4acf-bc6a-0fffe23a4e6b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420774985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2420774985
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.2857699071
Short name	T228
Test name
Test status
Simulation time	1478465251 ps
CPU time	10.34 seconds
Started	Jun 26 04:43:14 PM PDT 24
Finished	Jun 26 04:43:27 PM PDT 24
Peak memory	226260 kb
Host	smart-0fb8e350-24c8-4f18-a5cc-5008a945a9cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857699071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.2857699071
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.484185519
Short name	T666
Test name
Test status
Simulation time	792389433 ps
CPU time	7.04 seconds
Started	Jun 26 04:43:15 PM PDT 24
Finished	Jun 26 04:43:26 PM PDT 24
Peak memory	218460 kb
Host	smart-c025dc3e-2273-49af-acda-68ccc3afe78c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484185519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.484185519
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.2582304474
Short name	T623
Test name
Test status
Simulation time	420412888 ps
CPU time	12.78 seconds
Started	Jun 26 04:43:08 PM PDT 24
Finished	Jun 26 04:43:24 PM PDT 24
Peak memory	218652 kb
Host	smart-515c56d7-dee6-4b6f-b520-1c7f5c4629d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582304474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2582304474
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.2997472444
Short name	T695
Test name
Test status
Simulation time	27878401 ps
CPU time	1.84 seconds
Started	Jun 26 04:43:09 PM PDT 24
Finished	Jun 26 04:43:15 PM PDT 24
Peak memory	214464 kb
Host	smart-81d79018-4123-476f-b159-d5171190d3e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997472444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2997472444
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.1643160282
Short name	T253
Test name
Test status
Simulation time	4658828983 ps
CPU time	32.93 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:42 PM PDT 24
Peak memory	251280 kb
Host	smart-ac9e1299-5af9-41a0-a119-922af23f80d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643160282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1643160282
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.3496841659
Short name	T636
Test name
Test status
Simulation time	120075185 ps
CPU time	7.06 seconds
Started	Jun 26 04:43:07 PM PDT 24
Finished	Jun 26 04:43:17 PM PDT 24
Peak memory	243056 kb
Host	smart-3bbd3913-5c23-4358-ae24-0cc6b3fe577a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496841659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3496841659
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.4172233093
Short name	T79
Test name
Test status
Simulation time	57596254542 ps
CPU time	236.63 seconds
Started	Jun 26 04:43:17 PM PDT 24
Finished	Jun 26 04:47:18 PM PDT 24
Peak memory	220268 kb
Host	smart-928e4993-9e89-478c-bbfd-4d2e5fbd3e50
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172233093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.4172233093
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1204236447
Short name	T315
Test name
Test status
Simulation time	26725603 ps
CPU time	0.78 seconds
Started	Jun 26 04:43:10 PM PDT 24
Finished	Jun 26 04:43:15 PM PDT 24
Peak memory	209108 kb
Host	smart-10f2d3a0-7d27-4e8a-bcb4-3277ffd2440d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204236447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.1204236447
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.3755037839
Short name	T461
Test name
Test status
Simulation time	22216052 ps
CPU time	0.86 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:21 PM PDT 24
Peak memory	209072 kb
Host	smart-82b4d41d-e947-41e4-99ae-4a97f95b2f47
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755037839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3755037839
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.3462126146
Short name	T415
Test name
Test status
Simulation time	37138517 ps
CPU time	0.92 seconds
Started	Jun 26 04:40:57 PM PDT 24
Finished	Jun 26 04:41:04 PM PDT 24
Peak memory	209220 kb
Host	smart-7009efdf-bc85-41c1-997a-dd9e146075c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462126146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3462126146
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.2183019303
Short name	T542
Test name
Test status
Simulation time	381276336 ps
CPU time	7.9 seconds
Started	Jun 26 04:41:00 PM PDT 24
Finished	Jun 26 04:41:13 PM PDT 24
Peak memory	218536 kb
Host	smart-280924e5-0b65-4bbf-8514-64b15d66e509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183019303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2183019303
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.1723228125
Short name	T373
Test name
Test status
Simulation time	1149569259 ps
CPU time	14.3 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:18 PM PDT 24
Peak memory	217628 kb
Host	smart-d8c63ab5-bac7-4d15-b9e3-5261a175b8d0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723228125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1723228125
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.3568318980
Short name	T479
Test name
Test status
Simulation time	5266567237 ps
CPU time	21.19 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:38 PM PDT 24
Peak memory	219168 kb
Host	smart-10d6e4c9-c2cb-4d80-8a2a-a23800df2320
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568318980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er rors.3568318980
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.1521955306
Short name	T750
Test name
Test status
Simulation time	63482331 ps
CPU time	1.6 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:41:06 PM PDT 24
Peak memory	217564 kb
Host	smart-71c83638-2979-40ed-a570-a3fccc29fecf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521955306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1 521955306
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.616570345
Short name	T649
Test name
Test status
Simulation time	457256459 ps
CPU time	4.81 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:09 PM PDT 24
Peak memory	218564 kb
Host	smart-e2585ee2-0fe3-4e86-bdbc-85c7ea99e1d3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616570345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ prog_failure.616570345
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.347328868
Short name	T532
Test name
Test status
Simulation time	3102469006 ps
CPU time	25.25 seconds
Started	Jun 26 04:41:05 PM PDT 24
Finished	Jun 26 04:41:34 PM PDT 24
Peak memory	218024 kb
Host	smart-056a5be2-c980-4a09-af13-9dbce418cf43
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347328868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j tag_regwen_during_op.347328868
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.1057336324
Short name	T488
Test name
Test status
Simulation time	435896042 ps
CPU time	2.98 seconds
Started	Jun 26 04:41:03 PM PDT 24
Finished	Jun 26 04:41:10 PM PDT 24
Peak memory	217960 kb
Host	smart-7332b9e1-52ff-4d5f-bf1d-76a69b8161da
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057336324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 1057336324
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2403935604
Short name	T808
Test name
Test status
Simulation time	1414586528 ps
CPU time	39.22 seconds
Started	Jun 26 04:41:07 PM PDT 24
Finished	Jun 26 04:41:50 PM PDT 24
Peak memory	272764 kb
Host	smart-467a710e-3298-46e7-9878-71ad18fb9f28
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403935604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.2403935604
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1450730601
Short name	T607
Test name
Test status
Simulation time	2627756508 ps
CPU time	11.58 seconds
Started	Jun 26 04:41:00 PM PDT 24
Finished	Jun 26 04:41:17 PM PDT 24
Peak memory	243108 kb
Host	smart-85509264-03d6-41c9-947f-5ba0571c9778
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450730601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.1450730601
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.473037561
Short name	T492
Test name
Test status
Simulation time	33622854 ps
CPU time	2.26 seconds
Started	Jun 26 04:41:02 PM PDT 24
Finished	Jun 26 04:41:09 PM PDT 24
Peak memory	218608 kb
Host	smart-3cdb77d0-ecfd-4a00-94f6-0b32e02f64e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473037561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.473037561
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.545826095
Short name	T61
Test name
Test status
Simulation time	560819756 ps
CPU time	6.74 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	217964 kb
Host	smart-39b42e6d-2b50-4613-a5a5-e47306389983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545826095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.545826095
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.3921675456
Short name	T342
Test name
Test status
Simulation time	1134567859 ps
CPU time	13.2 seconds
Started	Jun 26 04:41:00 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	226424 kb
Host	smart-9de11271-b2cb-4d6f-9b0a-7ca1d4b6d67a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921675456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3921675456
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.2536044401
Short name	T751
Test name
Test status
Simulation time	1105134616 ps
CPU time	11.89 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	218496 kb
Host	smart-f68067a3-cb18-4d93-becc-d5f92d8c2564
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536044401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.2536044401
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.2090945988
Short name	T533
Test name
Test status
Simulation time	312483029 ps
CPU time	10.6 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	218472 kb
Host	smart-eb8f03d0-e0de-477c-a5e4-c302dbdaff33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090945988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2 090945988
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.1222474530
Short name	T515
Test name
Test status
Simulation time	1668793164 ps
CPU time	11.19 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:15 PM PDT 24
Peak memory	226400 kb
Host	smart-02d03beb-1898-49f8-b4d4-94ced5b7d4ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222474530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1222474530
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.2791795587
Short name	T55
Test name
Test status
Simulation time	19440428 ps
CPU time	1.41 seconds
Started	Jun 26 04:41:04 PM PDT 24
Finished	Jun 26 04:41:09 PM PDT 24
Peak memory	214148 kb
Host	smart-47d3735d-452d-459c-84eb-fad88bd912de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791795587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2791795587
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.3043785928
Short name	T725
Test name
Test status
Simulation time	1427354110 ps
CPU time	21.82 seconds
Started	Jun 26 04:40:58 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	245888 kb
Host	smart-8835c461-557d-418b-a17d-d5e9a5c97bd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043785928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3043785928
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.4097375254
Short name	T761
Test name
Test status
Simulation time	260169668 ps
CPU time	6.21 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	246596 kb
Host	smart-5835b1df-48c6-4b36-8d0c-257b9f12573d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097375254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4097375254
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.3529682418
Short name	T16
Test name
Test status
Simulation time	5068142982 ps
CPU time	104.07 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:43:08 PM PDT 24
Peak memory	283076 kb
Host	smart-226a4003-3d00-425d-9659-43519d2f701b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529682418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.3529682418
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2470069720
Short name	T245
Test name
Test status
Simulation time	100498232 ps
CPU time	0.82 seconds
Started	Jun 26 04:40:59 PM PDT 24
Finished	Jun 26 04:41:05 PM PDT 24
Peak memory	209092 kb
Host	smart-b2721c90-cb38-4b4a-8ed2-4fd7f62c3361
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470069720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.2470069720
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.1618094372
Short name	T705
Test name
Test status
Simulation time	26126497 ps
CPU time	0.86 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:41:11 PM PDT 24
Peak memory	209304 kb
Host	smart-71c05843-1b2d-43e2-a7e8-193bbde2ad99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618094372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1618094372
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.56084393
Short name	T803
Test name
Test status
Simulation time	14117248 ps
CPU time	1.01 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	209260 kb
Host	smart-ec130704-4196-432c-a08f-384418df8def
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56084393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.56084393
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.3488331078
Short name	T105
Test name
Test status
Simulation time	245689717 ps
CPU time	8.75 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:41:18 PM PDT 24
Peak memory	226344 kb
Host	smart-266dca8e-ac9e-4f07-8b03-c09effd8ef86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488331078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3488331078
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.3219432472
Short name	T298
Test name
Test status
Simulation time	91027441 ps
CPU time	1.54 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:22 PM PDT 24
Peak memory	217420 kb
Host	smart-d86ec58e-88f3-4b2e-a283-523f608fd845
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219432472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3219432472
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.1993117206
Short name	T762
Test name
Test status
Simulation time	9369554653 ps
CPU time	53.18 seconds
Started	Jun 26 04:41:04 PM PDT 24
Finished	Jun 26 04:42:01 PM PDT 24
Peak memory	220000 kb
Host	smart-3240a11f-2247-42a1-af57-062939c88f9d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993117206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.1993117206
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.4250625306
Short name	T630
Test name
Test status
Simulation time	279728527 ps
CPU time	7.48 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:41:17 PM PDT 24
Peak memory	217992 kb
Host	smart-4fc6af7a-31ba-4c6f-bbc5-49e3dc71dad6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250625306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4 250625306
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.496073072
Short name	T608
Test name
Test status
Simulation time	1715653468 ps
CPU time	6.19 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	218452 kb
Host	smart-21527173-814c-4824-8f89-60e80a3639fc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496073072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ prog_failure.496073072
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2093253191
Short name	T243
Test name
Test status
Simulation time	685109853 ps
CPU time	20.39 seconds
Started	Jun 26 04:41:09 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	217884 kb
Host	smart-c372cf12-01e6-4f51-844a-53a2c42d3252
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093253191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.2093253191
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.1272234996
Short name	T671
Test name
Test status
Simulation time	661708142 ps
CPU time	7.79 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:28 PM PDT 24
Peak memory	217868 kb
Host	smart-75e7a530-15f8-4e84-95f7-202c27e494e1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272234996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 1272234996
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1882588264
Short name	T216
Test name
Test status
Simulation time	2897499746 ps
CPU time	44.33 seconds
Started	Jun 26 04:41:09 PM PDT 24
Finished	Jun 26 04:41:58 PM PDT 24
Peak memory	269784 kb
Host	smart-6a7097fe-ddf9-44fc-a002-6671d374f9f5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882588264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.1882588264
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1831157261
Short name	T458
Test name
Test status
Simulation time	2940284610 ps
CPU time	12.89 seconds
Started	Jun 26 04:41:09 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	251284 kb
Host	smart-55290294-2e84-4b9f-b380-5c3ebd722e82
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831157261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.1831157261
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.33758879
Short name	T824
Test name
Test status
Simulation time	76715655 ps
CPU time	2.91 seconds
Started	Jun 26 04:41:05 PM PDT 24
Finished	Jun 26 04:41:12 PM PDT 24
Peak memory	222892 kb
Host	smart-0b1928d0-ad5c-4a67-acfc-18a2e5355cf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33758879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.33758879
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.2376279318
Short name	T66
Test name
Test status
Simulation time	681403276 ps
CPU time	17.78 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:43 PM PDT 24
Peak memory	218032 kb
Host	smart-5de80faf-9bef-4f14-9bfd-6a6cdae716e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376279318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2376279318
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.1302122633
Short name	T779
Test name
Test status
Simulation time	676928735 ps
CPU time	7.35 seconds
Started	Jun 26 04:41:14 PM PDT 24
Finished	Jun 26 04:41:28 PM PDT 24
Peak memory	218536 kb
Host	smart-f0c415df-795f-438b-98cf-959dc8303bd6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302122633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1302122633
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.841567625
Short name	T337
Test name
Test status
Simulation time	2187565958 ps
CPU time	12.69 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	218628 kb
Host	smart-e066a160-4bd2-4d1c-a3a2-0ab3d7186421
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841567625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig est.841567625
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.1249717458
Short name	T723
Test name
Test status
Simulation time	2124449457 ps
CPU time	12.66 seconds
Started	Jun 26 04:41:09 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	226280 kb
Host	smart-58dea092-4b48-4327-a953-5d9d48b2f392
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249717458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1 249717458
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.3271998165
Short name	T465
Test name
Test status
Simulation time	230135827 ps
CPU time	6.51 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	225160 kb
Host	smart-5df9a049-aea4-4613-a735-ea3dcfa53111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271998165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3271998165
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.2961147865
Short name	T746
Test name
Test status
Simulation time	34474807 ps
CPU time	2.85 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:22 PM PDT 24
Peak memory	215020 kb
Host	smart-3b25cf3c-b624-474a-b00d-82d20cfee959
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961147865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2961147865
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.771700941
Short name	T375
Test name
Test status
Simulation time	271157017 ps
CPU time	30.59 seconds
Started	Jun 26 04:41:04 PM PDT 24
Finished	Jun 26 04:41:39 PM PDT 24
Peak memory	251236 kb
Host	smart-040d3d35-e464-4ccb-8bed-e8b6ac15d552
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771700941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.771700941
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.1827277555
Short name	T32
Test name
Test status
Simulation time	112507957 ps
CPU time	5.8 seconds
Started	Jun 26 04:41:09 PM PDT 24
Finished	Jun 26 04:41:21 PM PDT 24
Peak memory	247156 kb
Host	smart-1213a1bc-f133-456d-9e7f-91a1b4e764e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827277555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1827277555
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.1296089635
Short name	T44
Test name
Test status
Simulation time	13067230313 ps
CPU time	62.69 seconds
Started	Jun 26 04:41:14 PM PDT 24
Finished	Jun 26 04:42:23 PM PDT 24
Peak memory	251248 kb
Host	smart-fcfd2a8b-38a0-4a6a-b96b-d1ce6dcebe86
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296089635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.1296089635
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3695504176
Short name	T153
Test name
Test status
Simulation time	41335982548 ps
CPU time	231.76 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:45:01 PM PDT 24
Peak memory	281464 kb
Host	smart-24ff51a5-9383-4afa-bee2-0dc5496b8cc5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3695504176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3695504176
Directory	/workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3692228935
Short name	T693
Test name
Test status
Simulation time	16265918 ps
CPU time	0.95 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	209380 kb
Host	smart-83a4cd75-8f12-4af3-81ca-4e7d06a94a1e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692228935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_volatile_unlock_smoke.3692228935
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.38083366
Short name	T345
Test name
Test status
Simulation time	19462413 ps
CPU time	0.85 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:21 PM PDT 24
Peak memory	209088 kb
Host	smart-6399d297-90ce-45b0-ba4d-3770a48aa24c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38083366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.38083366
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.2313451565
Short name	T201
Test name
Test status
Simulation time	42479776 ps
CPU time	0.97 seconds
Started	Jun 26 04:41:07 PM PDT 24
Finished	Jun 26 04:41:12 PM PDT 24
Peak memory	209252 kb
Host	smart-fc6d5090-be7e-44d4-90e7-ad70106cb621
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313451565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2313451565
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.3125492446
Short name	T99
Test name
Test status
Simulation time	2069093471 ps
CPU time	21.93 seconds
Started	Jun 26 04:41:07 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	218496 kb
Host	smart-ac9cfc4c-b001-40fe-8e78-7fee11a93687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125492446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3125492446
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.3320986501
Short name	T21
Test name
Test status
Simulation time	3136574513 ps
CPU time	6.33 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:25 PM PDT 24
Peak memory	217760 kb
Host	smart-27feeaeb-04a7-48e1-826f-4d78e548b291
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320986501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3320986501
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.1411261381
Short name	T586
Test name
Test status
Simulation time	17690849759 ps
CPU time	58.64 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	219912 kb
Host	smart-539e2886-a389-4a81-99a9-56a139beafb3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411261381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.1411261381
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.2513887182
Short name	T502
Test name
Test status
Simulation time	1009901520 ps
CPU time	4.74 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	217820 kb
Host	smart-51ee855f-8335-499b-9fd6-4269986a502f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513887182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2 513887182
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.670666711
Short name	T405
Test name
Test status
Simulation time	378534333 ps
CPU time	11.85 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	218452 kb
Host	smart-43df415d-2b77-4adb-8418-7020c8c0d4ad
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670666711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ prog_failure.670666711
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2360196583
Short name	T78
Test name
Test status
Simulation time	5577157691 ps
CPU time	34.9 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:52 PM PDT 24
Peak memory	218252 kb
Host	smart-02702a8f-a6b1-4f15-bea1-444e960e3fbf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360196583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.2360196583
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.1392858428
Short name	T793
Test name
Test status
Simulation time	143735552 ps
CPU time	4.57 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	217872 kb
Host	smart-71d1c4a8-2423-470e-89c1-1b453ffd80ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392858428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 1392858428
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2451415932
Short name	T106
Test name
Test status
Simulation time	14715767417 ps
CPU time	70.87 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:42:27 PM PDT 24
Peak memory	284032 kb
Host	smart-c5a4ead7-17ff-4f84-a24d-8554bd7cc484
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451415932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.2451415932
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2349787032
Short name	T670
Test name
Test status
Simulation time	864193750 ps
CPU time	23.21 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	247692 kb
Host	smart-6c54a288-aa76-420c-8a99-13ec2b78e66f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349787032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_state_post_trans.2349787032
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.1375724926
Short name	T578
Test name
Test status
Simulation time	90996010 ps
CPU time	1.5 seconds
Started	Jun 26 04:41:05 PM PDT 24
Finished	Jun 26 04:41:10 PM PDT 24
Peak memory	218480 kb
Host	smart-017fb497-c7c7-4bc5-abed-bd0d64a83262
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1375724926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1375724926
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.3790363445
Short name	T674
Test name
Test status
Simulation time	237096281 ps
CPU time	15.68 seconds
Started	Jun 26 04:41:07 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	214840 kb
Host	smart-5f9367d9-0aa6-4b98-bb28-07e47177ae76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790363445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3790363445
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.3503536025
Short name	T364
Test name
Test status
Simulation time	706675314 ps
CPU time	16.8 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	226316 kb
Host	smart-14f04e55-79d7-4f74-a348-0afc70ddf61a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503536025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3503536025
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.2773796064
Short name	T782
Test name
Test status
Simulation time	660088251 ps
CPU time	10.16 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:28 PM PDT 24
Peak memory	218484 kb
Host	smart-f661c72d-5adc-40a8-916a-69b5543fd30b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773796064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.2773796064
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.3973320245
Short name	T366
Test name
Test status
Simulation time	724365918 ps
CPU time	15.11 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	226280 kb
Host	smart-a05e77b3-cfb8-46ab-9e27-49fed433a6e8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973320245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3 973320245
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.3382803828
Short name	T635
Test name
Test status
Simulation time	749237317 ps
CPU time	11.81 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:37 PM PDT 24
Peak memory	218656 kb
Host	smart-b7cab420-add9-41fe-a5dc-d74d4037e142
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382803828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3382803828
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.3211228896
Short name	T169
Test name
Test status
Simulation time	107494835 ps
CPU time	2.21 seconds
Started	Jun 26 04:41:07 PM PDT 24
Finished	Jun 26 04:41:12 PM PDT 24
Peak memory	214504 kb
Host	smart-d4999adb-9e7a-48f0-897e-48e498f37cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211228896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3211228896
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.3058066610
Short name	T402
Test name
Test status
Simulation time	618379622 ps
CPU time	20.82 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:40 PM PDT 24
Peak memory	251220 kb
Host	smart-f845c9ac-0972-4906-9ba4-7e684226c08f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058066610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3058066610
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.1200294421
Short name	T787
Test name
Test status
Simulation time	185297116 ps
CPU time	4.6 seconds
Started	Jun 26 04:41:05 PM PDT 24
Finished	Jun 26 04:41:13 PM PDT 24
Peak memory	218632 kb
Host	smart-3ce82ff8-8d28-4277-843a-9632ec6284ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200294421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1200294421
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.1837798988
Short name	T744
Test name
Test status
Simulation time	27157106978 ps
CPU time	238.84 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:45:19 PM PDT 24
Peak memory	316776 kb
Host	smart-73e42b78-d6f7-43b0-a323-92fda9a12726
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837798988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.1837798988
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1901744040
Short name	T28
Test name
Test status
Simulation time	13970337 ps
CPU time	0.94 seconds
Started	Jun 26 04:41:06 PM PDT 24
Finished	Jun 26 04:41:10 PM PDT 24
Peak memory	212204 kb
Host	smart-bdc51e37-7fc5-4300-a857-e2bb0e38139e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901744040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.1901744040
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.3650565939
Short name	T450
Test name
Test status
Simulation time	64540463 ps
CPU time	1.08 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	209344 kb
Host	smart-de9b507c-97fb-4cdb-9ca4-3e26a1099760
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650565939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3650565939
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.2156030893
Short name	T200
Test name
Test status
Simulation time	112543202 ps
CPU time	0.91 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:20 PM PDT 24
Peak memory	209268 kb
Host	smart-9fc21648-f70d-43a8-b4cf-6aa3fd7365fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156030893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2156030893
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.3366400003
Short name	T843
Test name
Test status
Simulation time	772157302 ps
CPU time	10.31 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:29 PM PDT 24
Peak memory	226324 kb
Host	smart-9b9cafdc-cc47-48ca-b101-5d44e64a6bf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366400003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3366400003
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.4290369474
Short name	T766
Test name
Test status
Simulation time	340913018 ps
CPU time	9.1 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	217644 kb
Host	smart-f30dbdf2-d29b-4254-b112-9221779670bf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290369474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4290369474
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.3956433025
Short name	T340
Test name
Test status
Simulation time	1173951241 ps
CPU time	37.67 seconds
Started	Jun 26 04:41:15 PM PDT 24
Finished	Jun 26 04:41:59 PM PDT 24
Peak memory	226268 kb
Host	smart-a116ab9c-0451-40ff-986e-26bc9beb6919
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956433025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.3956433025
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.2490535054
Short name	T755
Test name
Test status
Simulation time	267521330 ps
CPU time	3.69 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	218068 kb
Host	smart-4332241d-e2dd-4c1f-abff-0a11f55bef2a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490535054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2 490535054
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3723719921
Short name	T103
Test name
Test status
Simulation time	613810475 ps
CPU time	15.86 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	218548 kb
Host	smart-2c28a504-27e3-4ca2-8ff6-90c808b83ccd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723719921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.3723719921
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3362240900
Short name	T339
Test name
Test status
Simulation time	800804569 ps
CPU time	13.82 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:33 PM PDT 24
Peak memory	217888 kb
Host	smart-20081c33-5bc8-46d8-803b-8605e284d542
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362240900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.3362240900
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.2309841864
Short name	T321
Test name
Test status
Simulation time	292940221 ps
CPU time	4.23 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	217884 kb
Host	smart-ba6cc6b8-ba0b-474b-9e09-131f4bf3b81c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309841864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 2309841864
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.207689960
Short name	T865
Test name
Test status
Simulation time	1370542189 ps
CPU time	46.69 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:42:03 PM PDT 24
Peak memory	267552 kb
Host	smart-a08e9854-3906-405d-8352-7d268ffa8a8e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207689960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _state_failure.207689960
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1389452704
Short name	T778
Test name
Test status
Simulation time	500702152 ps
CPU time	14.41 seconds
Started	Jun 26 04:41:10 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	251188 kb
Host	smart-3c4cc1e7-64b5-418b-9064-2dff4547f8b2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389452704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.1389452704
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.3965307597
Short name	T601
Test name
Test status
Simulation time	44968223 ps
CPU time	2.3 seconds
Started	Jun 26 04:41:15 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	218500 kb
Host	smart-e71d9302-b1f8-48af-8626-365677c5ab11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965307597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3965307597
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.3472598518
Short name	T75
Test name
Test status
Simulation time	1388526680 ps
CPU time	12.91 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	217888 kb
Host	smart-3812eff4-3bf3-417d-a2aa-7df21be95b8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472598518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3472598518
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.38663831
Short name	T60
Test name
Test status
Simulation time	1543344873 ps
CPU time	13.27 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	226324 kb
Host	smart-a28be102-8af4-4dc1-bba2-c5b3245dd2d0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.38663831
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.3054905210
Short name	T640
Test name
Test status
Simulation time	211530302 ps
CPU time	9.71 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	218540 kb
Host	smart-ecffd8a8-159c-47d6-8e08-1d49f969a9aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054905210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.3054905210
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.2732847449
Short name	T484
Test name
Test status
Simulation time	357451385 ps
CPU time	11.62 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:31 PM PDT 24
Peak memory	218484 kb
Host	smart-bdde243b-2a9d-4807-8350-77879036407e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732847449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2 732847449
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.1638565270
Short name	T445
Test name
Test status
Simulation time	6352558861 ps
CPU time	14.08 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:33 PM PDT 24
Peak memory	226400 kb
Host	smart-66152aa1-e700-4f72-8751-ed076590a09f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638565270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1638565270
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.2910883937
Short name	T642
Test name
Test status
Simulation time	33262058 ps
CPU time	2.57 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:19 PM PDT 24
Peak memory	217936 kb
Host	smart-f337547c-ba46-48cf-8643-b32bfe6a022e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910883937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2910883937
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.2942066889
Short name	T516
Test name
Test status
Simulation time	770641077 ps
CPU time	25.03 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	251204 kb
Host	smart-9eab6915-5e1f-4473-a289-003f6ed26fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942066889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2942066889
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.2384533985
Short name	T661
Test name
Test status
Simulation time	153391691 ps
CPU time	6.48 seconds
Started	Jun 26 04:41:14 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	250724 kb
Host	smart-59b1bf48-f419-4938-9d6a-d6978c8f8b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384533985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2384533985
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.283430058
Short name	T178
Test name
Test status
Simulation time	27755818960 ps
CPU time	149.99 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:43:50 PM PDT 24
Peak memory	279052 kb
Host	smart-db782ca0-4236-47f7-a6de-b5799a328429
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283430058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.283430058
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3477380266
Short name	T409
Test name
Test status
Simulation time	19741622883 ps
CPU time	404.97 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:48:11 PM PDT 24
Peak memory	276076 kb
Host	smart-9addd806-5ee7-4c17-90da-861f36e99b09
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3477380266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3477380266
Directory	/workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.4065502043
Short name	T631
Test name
Test status
Simulation time	44962071 ps
CPU time	0.93 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	209352 kb
Host	smart-44ac1013-e80e-4ec2-a497-ca8a0758ab5d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065502043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4065502043
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.3445462494
Short name	T353
Test name
Test status
Simulation time	24847487 ps
CPU time	1.02 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:18 PM PDT 24
Peak memory	209592 kb
Host	smart-7854972c-bdb9-46bf-afa3-355fe55d8667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445462494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3445462494
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.2187214741
Short name	T499
Test name
Test status
Simulation time	399162691 ps
CPU time	13.25 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:32 PM PDT 24
Peak memory	218524 kb
Host	smart-fafe19d9-23a0-4b53-a6fc-c09a944669ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187214741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2187214741
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.23733795
Short name	T809
Test name
Test status
Simulation time	578129308 ps
CPU time	15.08 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:40 PM PDT 24
Peak memory	217796 kb
Host	smart-f73d60a5-83e1-4f9d-820f-8521a19c02b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23733795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.23733795
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.2382626808
Short name	T633
Test name
Test status
Simulation time	1711453737 ps
CPU time	47.96 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:42:08 PM PDT 24
Peak memory	218572 kb
Host	smart-5124cf96-53b8-454d-8f78-8e6e14c10a01
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382626808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.2382626808
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.1100770664
Short name	T374
Test name
Test status
Simulation time	381854535 ps
CPU time	2.84 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:22 PM PDT 24
Peak memory	218016 kb
Host	smart-76b1e11e-5df5-4061-900f-a1d1886d5978
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100770664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1 100770664
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2840350116
Short name	T208
Test name
Test status
Simulation time	1323649886 ps
CPU time	6.06 seconds
Started	Jun 26 04:41:14 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	218448 kb
Host	smart-b47e78a1-f64e-41ec-8f7d-95f5dc1f55e5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840350116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.2840350116
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.946658825
Short name	T483
Test name
Test status
Simulation time	705937394 ps
CPU time	10.59 seconds
Started	Jun 26 04:41:18 PM PDT 24
Finished	Jun 26 04:41:35 PM PDT 24
Peak memory	217888 kb
Host	smart-e76c7b51-7026-44df-9ad6-ebe7636f0988
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946658825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_regwen_during_op.946658825
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.1974869383
Short name	T559
Test name
Test status
Simulation time	4861501322 ps
CPU time	11.27 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:28 PM PDT 24
Peak memory	217908 kb
Host	smart-3b730944-2fa4-486e-84f2-ec8fcf0ee029
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974869383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 1974869383
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1930452094
Short name	T454
Test name
Test status
Simulation time	9470976070 ps
CPU time	64.77 seconds
Started	Jun 26 04:41:15 PM PDT 24
Finished	Jun 26 04:42:26 PM PDT 24
Peak memory	267600 kb
Host	smart-fcc8a6ac-d352-4da5-9509-2b24ea5ecba0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930452094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.1930452094
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2185189822
Short name	T643
Test name
Test status
Simulation time	321792724 ps
CPU time	10.32 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	250600 kb
Host	smart-e07b5b1c-3f24-4077-99e1-14ba8978f5bc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185189822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.2185189822
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.2943463271
Short name	T360
Test name
Test status
Simulation time	101785588 ps
CPU time	3.47 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:23 PM PDT 24
Peak memory	218444 kb
Host	smart-5df572ef-8423-4436-a289-d8d8823fb9f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943463271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2943463271
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.1639762457
Short name	T67
Test name
Test status
Simulation time	3508363823 ps
CPU time	9.16 seconds
Started	Jun 26 04:41:12 PM PDT 24
Finished	Jun 26 04:41:27 PM PDT 24
Peak memory	215656 kb
Host	smart-d3b96b8c-fbc9-4c21-b1ea-2591c501ae4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639762457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1639762457
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.3368490399
Short name	T269
Test name
Test status
Simulation time	747454382 ps
CPU time	21.86 seconds
Started	Jun 26 04:41:16 PM PDT 24
Finished	Jun 26 04:41:45 PM PDT 24
Peak memory	226444 kb
Host	smart-c0cf0d98-c3f9-4cd2-8e64-548bcc3713fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368490399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3368490399
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.1935143361
Short name	T522
Test name
Test status
Simulation time	1262724762 ps
CPU time	8.81 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:34 PM PDT 24
Peak memory	218576 kb
Host	smart-cc4ccf45-e60f-4df7-9bcd-eb00c8807f3b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935143361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.1935143361
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.878847165
Short name	T485
Test name
Test status
Simulation time	737464898 ps
CPU time	6.44 seconds
Started	Jun 26 04:41:17 PM PDT 24
Finished	Jun 26 04:41:30 PM PDT 24
Peak memory	218480 kb
Host	smart-40ba7d9f-4652-405b-aefe-d9b7aa91dc12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878847165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.878847165
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.4236076437
Short name	T817
Test name
Test status
Simulation time	1762594739 ps
CPU time	11.07 seconds
Started	Jun 26 04:41:19 PM PDT 24
Finished	Jun 26 04:41:36 PM PDT 24
Peak memory	225248 kb
Host	smart-f7a9b047-2e3c-4d4e-948b-3d1d7d0dd58e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236076437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4236076437
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.1107294089
Short name	T609
Test name
Test status
Simulation time	1329894644 ps
CPU time	7.18 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:24 PM PDT 24
Peak memory	217960 kb
Host	smart-7f198047-9eed-45e0-a777-2f5d620a3160
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107294089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1107294089
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.2293735679
Short name	T210
Test name
Test status
Simulation time	437002216 ps
CPU time	19.14 seconds
Started	Jun 26 04:41:15 PM PDT 24
Finished	Jun 26 04:41:41 PM PDT 24
Peak memory	251220 kb
Host	smart-52919004-1919-4e8f-ab71-ec361db280b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293735679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2293735679
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.2146493321
Short name	T804
Test name
Test status
Simulation time	81468344 ps
CPU time	9.39 seconds
Started	Jun 26 04:41:11 PM PDT 24
Finished	Jun 26 04:41:26 PM PDT 24
Peak memory	251220 kb
Host	smart-8c3ea38e-175d-4f66-857f-fb0df549be1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146493321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2146493321
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.484007940
Short name	T774
Test name
Test status
Simulation time	17014397120 ps
CPU time	301.63 seconds
Started	Jun 26 04:41:20 PM PDT 24
Finished	Jun 26 04:46:27 PM PDT 24
Peak memory	247424 kb
Host	smart-7a0456fd-1cd3-4cb1-9065-25940d70d47d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484007940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.484007940
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.690063128
Short name	T579
Test name
Test status
Simulation time	52604683 ps
CPU time	1.11 seconds
Started	Jun 26 04:41:13 PM PDT 24
Finished	Jun 26 04:41:21 PM PDT 24
Peak memory	213184 kb
Host	smart-d4f46036-3c44-43be-bb9b-214311c39b05
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690063128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_volatile_unlock_smoke.690063128
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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