Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1651452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1872027

1

T1

528

T2

13

T3

1137

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3178889	1			T1	406		T2	5		T3	930
values[0x0]	172147	1			T1	212		T2	7		T3	376
values[0x1]	172443	1			T1	196		T2	8		T3	384

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1311945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2211534

1

T1

595

T2

13

T3

1271

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11389	1			T1	4		T3	1		T4	1
valid_sources[0x01]	13199	1			T1	3		T3	3		T4	5
valid_sources[0x02]	12540	1			T1	2		T3	6		T4	2
valid_sources[0x03]	11829	1			T1	2		T3	12		T4	1
valid_sources[0x04]	11671	1			T1	2		T2	6		T3	7
valid_sources[0x05]	11216	1			T1	3		T3	4		T4	8
valid_sources[0x06]	14819	1			T1	6		T3	10		T4	2
valid_sources[0x07]	11974	1			T1	4		T3	7		T4	1
valid_sources[0x08]	12014	1			T1	3		T3	5		T14	4
valid_sources[0x09]	11351	1			T1	6		T3	6		T4	1
valid_sources[0x0a]	11496	1			T1	1		T3	14		T4	2
valid_sources[0x0b]	11549	1			T1	3		T2	2		T3	3
valid_sources[0x0c]	12823	1			T1	1		T3	8		T4	1
valid_sources[0x0d]	12110	1			T1	5		T3	1		T4	2
valid_sources[0x0e]	37666	1			T1	7		T3	5		T4	3
valid_sources[0x0f]	11829	1			T1	2		T3	3		T4	2
valid_sources[0x10]	12715	1			T1	1		T3	2		T4	5
valid_sources[0x11]	11401	1			T1	2		T3	5		T4	2
valid_sources[0x12]	12064	1			T1	5		T3	6		T4	3
valid_sources[0x13]	13280	1			T1	4		T3	1		T4	5
valid_sources[0x14]	11917	1			T1	3		T3	1		T4	5
valid_sources[0x15]	11630	1			T1	4		T3	8		T4	4
valid_sources[0x16]	12873	1			T1	1		T3	5		T4	2
valid_sources[0x17]	11809	1			T1	1		T3	9		T4	1
valid_sources[0x18]	11807	1			T1	3		T3	5		T4	1
valid_sources[0x19]	11688	1			T1	1		T3	2		T4	2
valid_sources[0x1a]	12819	1			T1	2		T3	2		T4	4
valid_sources[0x1b]	11549	1			T1	2		T3	19		T4	6
valid_sources[0x1c]	14263	1			T1	4		T3	8		T4	4
valid_sources[0x1d]	11653	1			T1	5		T3	25		T4	4
valid_sources[0x1e]	11818	1			T1	4		T3	8		T14	7
valid_sources[0x1f]	11465	1			T1	2		T3	3		T4	3
valid_sources[0x20]	12161	1			T1	7		T3	3		T4	4
valid_sources[0x21]	12890	1			T1	3		T3	6		T4	5
valid_sources[0x22]	12096	1			T1	5		T3	16		T4	2
valid_sources[0x23]	24474	1			T1	4		T3	2		T4	1
valid_sources[0x24]	12930	1			T1	4		T3	9		T4	3
valid_sources[0x25]	13436	1			T1	2		T3	8		T4	4
valid_sources[0x26]	11389	1			T1	1		T3	5		T4	4
valid_sources[0x27]	12891	1			T1	3		T3	3		T4	5
valid_sources[0x28]	11827	1			T1	1		T3	17		T4	1
valid_sources[0x29]	11627	1			T1	2		T3	10		T4	2
valid_sources[0x2a]	11666	1			T1	4		T3	6		T4	2
valid_sources[0x2b]	13560	1			T1	3		T3	1		T11	3
valid_sources[0x2c]	11786	1			T1	1		T3	11		T4	2
valid_sources[0x2d]	11629	1			T1	3		T3	3		T4	5
valid_sources[0x2e]	11603	1			T1	5		T3	7		T4	2
valid_sources[0x2f]	14106	1			T1	6		T3	1		T4	2
valid_sources[0x30]	11738	1			T1	6		T4	5		T14	4
valid_sources[0x31]	11531	1			T1	5		T3	17		T4	1
valid_sources[0x32]	11878	1			T1	1		T3	1		T4	1
valid_sources[0x33]	14547	1			T1	4		T3	14		T4	1
valid_sources[0x34]	13113	1			T1	2		T3	9		T4	1
valid_sources[0x35]	13779	1			T1	3		T3	12		T4	1
valid_sources[0x36]	11477	1			T1	2		T3	5		T4	5
valid_sources[0x37]	11760	1			T1	2		T3	7		T14	9
valid_sources[0x38]	11865	1			T1	3		T3	15		T4	4
valid_sources[0x39]	15262	1			T1	4		T3	3		T4	2
valid_sources[0x3a]	13339	1			T1	4		T3	7		T4	2
valid_sources[0x3b]	11706	1			T1	7		T3	4		T4	5
valid_sources[0x3c]	11609	1			T1	3		T3	5		T4	1
valid_sources[0x3d]	11948	1			T1	3		T3	6		T4	5
valid_sources[0x3e]	12167	1			T1	2		T3	8		T4	4
valid_sources[0x3f]	11545	1			T1	7		T4	1		T14	5
valid_sources[0x40]	11200	1			T1	3		T3	2		T4	7
valid_sources[0x41]	12621	1			T1	5		T3	17		T4	5
valid_sources[0x42]	11927	1			T1	4		T3	12		T4	7
valid_sources[0x43]	11109	1			T1	2		T3	10		T4	3
valid_sources[0x44]	11574	1			T1	2		T3	10		T4	4
valid_sources[0x45]	12032	1			T1	2		T3	10		T4	5
valid_sources[0x46]	11929	1			T1	7		T3	5		T4	4
valid_sources[0x47]	68774	1			T1	5		T3	2		T4	7
valid_sources[0x48]	12611	1			T1	3		T3	10		T4	1
valid_sources[0x49]	15244	1			T1	1		T3	11		T4	4
valid_sources[0x4a]	11984	1			T1	3		T3	10		T14	12
valid_sources[0x4b]	13103	1			T1	5		T4	4		T14	7
valid_sources[0x4c]	13956	1			T1	8		T3	2		T4	7
valid_sources[0x4d]	11427	1			T1	3		T3	10		T4	3
valid_sources[0x4e]	12999	1			T1	5		T3	4		T4	3
valid_sources[0x4f]	11482	1			T1	2		T3	11		T4	5
valid_sources[0x50]	11423	1			T1	2		T3	6		T4	4
valid_sources[0x51]	15808	1			T1	6		T3	4		T4	2
valid_sources[0x52]	12641	1			T1	8		T3	3		T4	1
valid_sources[0x53]	13925	1			T1	1		T3	10		T4	3
valid_sources[0x54]	11598	1			T1	2		T3	7		T4	2
valid_sources[0x55]	11645	1			T1	3		T2	2		T3	4
valid_sources[0x56]	11437	1			T1	3		T3	1		T4	1
valid_sources[0x57]	11677	1			T3	11		T4	2		T12	27
valid_sources[0x58]	34065	1			T1	3		T3	8		T4	3
valid_sources[0x59]	14550	1			T1	6		T3	3		T14	5
valid_sources[0x5a]	11690	1			T1	2		T3	8		T4	2
valid_sources[0x5b]	11301	1			T1	2		T3	4		T4	1
valid_sources[0x5c]	11240	1			T3	13		T4	4		T14	11
valid_sources[0x5d]	11856	1			T1	3		T3	17		T4	7
valid_sources[0x5e]	11473	1			T1	1		T3	1		T4	2
valid_sources[0x5f]	13754	1			T1	5		T3	6		T4	2
valid_sources[0x60]	12149	1			T1	3		T3	3		T4	6
valid_sources[0x61]	11553	1			T3	5		T4	4		T14	14
valid_sources[0x62]	13093	1			T1	4		T3	5		T4	2
valid_sources[0x63]	13240	1			T1	6		T3	11		T4	4
valid_sources[0x64]	11943	1			T1	4		T3	9		T4	2
valid_sources[0x65]	13543	1			T1	1		T3	7		T4	1
valid_sources[0x66]	12171	1			T1	4		T3	1		T4	5
valid_sources[0x67]	12418	1			T1	3		T3	2		T4	4
valid_sources[0x68]	11785	1			T1	2		T3	4		T4	8
valid_sources[0x69]	11347	1			T1	5		T2	5		T3	2
valid_sources[0x6a]	48151	1			T1	2		T3	1		T4	1
valid_sources[0x6b]	11545	1			T1	3		T3	5		T4	7
valid_sources[0x6c]	12121	1			T1	2		T3	11		T4	8
valid_sources[0x6d]	13423	1			T1	1		T3	8		T4	5
valid_sources[0x6e]	12925	1			T1	2		T3	11		T4	4
valid_sources[0x6f]	12756	1			T1	3		T3	14		T4	2
valid_sources[0x70]	11394	1			T1	4		T3	1		T4	3
valid_sources[0x71]	11769	1			T1	1		T3	3		T4	2
valid_sources[0x72]	11746	1			T1	6		T3	7		T4	4
valid_sources[0x73]	12161	1			T1	5		T3	5		T4	3
valid_sources[0x74]	12760	1			T1	8		T2	1		T3	4
valid_sources[0x75]	11504	1			T1	2		T3	1		T4	2
valid_sources[0x76]	13175	1			T1	5		T3	3		T4	1
valid_sources[0x77]	12616	1			T1	2		T2	1		T3	14
valid_sources[0x78]	29566	1			T1	3		T3	18		T4	2
valid_sources[0x79]	11510	1			T1	2		T3	9		T4	1
valid_sources[0x7a]	11674	1			T1	6		T3	7		T4	1
valid_sources[0x7b]	12073	1			T1	4		T3	10		T4	5
valid_sources[0x7c]	11471	1			T1	6		T3	5		T4	4
valid_sources[0x7d]	11846	1			T1	2		T3	2		T4	3
valid_sources[0x7e]	11251	1			T1	5		T3	5		T4	6
valid_sources[0x7f]	12607	1			T1	2		T3	9		T4	3
valid_sources[0x80]	12091	1			T1	2		T3	7		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1575063

1

T1

175

T2

2

T3

476

values[0x0]

all_enables

biggest_size

149349

1

T1

176

T2

6

T3

334

values[0x1]

all_enables

biggest_size

147615

1

T1

177

T2

5

T3

327