Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	96550987	14905	0	0
claim_transition_if_regwen_rd_A	96550987	950	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96550987	14905	0	0
T6	288972	1	0	0
T7	364682	0	0	0
T17	14101	0	0	0
T18	141767	2	0	0
T19	656681	0	0	0
T20	132035	0	0	0
T41	1368	0	0	0
T43	4956	0	0	0
T59	0	2	0	0
T60	0	5	0	0
T65	28436	0	0	0
T66	1937	0	0	0
T88	0	2	0	0
T103	0	12	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	15	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96550987	950	0	0
T18	141767	3	0	0
T19	656681	0	0	0
T20	132035	0	0	0
T41	1368	0	0	0
T43	4956	0	0	0
T44	32447	0	0	0
T66	1937	0	0	0
T75	0	1	0	0
T77	4722	0	0	0
T88	0	6	0	0
T92	2732	0	0	0
T112	0	9	0	0
T131	0	8	0	0
T140	0	11	0	0
T148	0	8	0	0
T150	0	3	0	0
T151	0	11	0	0
T152	0	261	0	0
T153	16364	0	0	0