Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96794704

1

T1

124329

T2

1035

T3

19738

auto[1]

1404004

1

T4

11901

T13

792

T7

2940

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96817457

1

T1

124329

T2

1035

T3

19738

auto[1]

1381251

1

T4

10691

T13

396

T7

2450

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7421829	1			T1	116		T2	70		T3	5730
auto[IdleSt]	21019391	1			T1	124213		T2	50		T3	1982
auto[ClkMuxSt]	33613	1			T3	62		T4	68		T5	69
auto[CntIncrSt]	33261	1			T3	62		T4	68		T5	69
auto[CntProgSt]	1593003	1			T3	1607		T4	13396		T5	1171
auto[TransCheckSt]	25943	1			T3	62		T4	37		T5	69
auto[TokenHashSt]	36698440	1			T3	789		T4	1118		T5	752
auto[FlashRmaSt]	27044	1			T3	30		T4	34		T12	41
auto[TokenCheck0St]	12131	1			T3	30		T4	24		T12	21
auto[TokenCheck1St]	9105	1			T3	7		T4	24		T12	7
auto[TransProgSt]	408504	1			T4	552		T13	43		T15	50
auto[PostTransSt]	11595385	1			T2	915		T3	9377		T4	6
auto[ScrapSt]	203521	1			T10	19		T35	3		T36	3
auto[EscalateSt]	6804152	1			T4	16728		T13	1648		T7	30205
auto[InvalidSt]	12311422	1			T7	104644		T15	1726		T10	137429

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1964	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12311422	1			T7	104644		T15	1726		T10	137429
EscalateSt	6804152	1			T4	16728		T13	1648		T7	30205
ScrapSt	203521	1			T10	19		T35	3		T36	3
PostTransSt	11595385	1			T2	915		T3	9377		T4	6
TransProgSt	408504	1			T4	552		T13	43		T15	50
TokenCheck1St	9105	1			T3	7		T4	24		T12	7
TokenCheck0St	12131	1			T3	30		T4	24		T12	21
FlashRmaSt	27044	1			T3	30		T4	34		T12	41
TokenHashSt	36698440	1			T3	789		T4	1118		T5	752
TransCheckSt	25943	1			T3	62		T4	37		T5	69
CntProgSt	1593003	1			T3	1607		T4	13396		T5	1171
CntIncrSt	33261	1			T3	62		T4	68		T5	69
ClkMuxSt	33613	1			T3	62		T4	68		T5	69
IdleSt	21019391	1			T1	124213		T2	50		T3	1982
ResetSt	7421829	1			T1	116		T2	70		T3	5730
arcs[ResetSt=>IdleSt]	52169	1			T1	1		T2	1		T3	63
arcs[IdleSt=>ScrapSt]	291	1			T10	1		T35	2		T36	1
arcs[IdleSt=>ClkMuxSt]	33317	1			T3	62		T4	68		T5	69
arcs[ClkMuxSt=>CntIncrSt]	33261	1			T3	62		T4	68		T5	69
arcs[CntIncrSt=>PostTransSt]	1682	1			T13	12		T16	6		T10	14
arcs[CntIncrSt=>CntProgSt]	31534	1			T3	62		T4	68		T5	69
arcs[CntProgSt=>PostTransSt]	4462	1			T13	12		T15	16		T16	8
arcs[CntProgSt=>TransCheckSt]	25943	1			T3	62		T4	37		T5	69
arcs[TransCheckSt=>PostTransSt]	3530	1			T3	25		T12	32		T13	12
arcs[TransCheckSt=>TokenHashSt]	22331	1			T3	37		T4	37		T5	69
arcs[TokenHashSt=>PostTransSt]	9536	1			T3	7		T5	69		T12	11
arcs[TokenHashSt=>FlashRmaSt]	12228	1			T3	30		T4	26		T12	21
arcs[FlashRmaSt=>TokenCheck0St]	12131	1			T3	30		T4	24		T12	21
arcs[TokenCheck0St=>PostTransSt]	2997	1			T3	23		T12	14		T13	12
arcs[TokenCheck0St=>TokenCheck1St]	9105	1			T3	7		T4	24		T12	7
arcs[TokenCheck1St=>PostTransSt]	630	1			T3	7		T12	7		T13	1
arcs[TransProgSt=>PostTransSt]	7529	1			T4	2		T13	8		T15	25
arcs[IdleSt=>EscalateSt]	218	1			T4	6		T36	11		T50	9
arcs[ClkMuxSt=>EscalateSt]	56	1			T36	4		T48	1		T49	1
arcs[CntIncrSt=>EscalateSt]	45	1			T36	1		T48	1		T49	1
arcs[CntProgSt=>EscalateSt]	1129	1			T4	31		T36	29		T50	34
arcs[TransCheckSt=>EscalateSt]	82	1			T49	2		T53	11		T54	4
arcs[TokenHashSt=>EscalateSt]	567	1			T4	11		T36	12		T50	6
arcs[FlashRmaSt=>EscalateSt]	97	1			T4	2		T36	1		T50	4
arcs[TokenCheck0St=>EscalateSt]	29	1			T36	1		T48	2		T49	1
arcs[TokenCheck1St=>EscalateSt]	143	1			T4	3		T36	3		T50	2
arcs[TransProgSt=>EscalateSt]	803	1			T4	19		T36	19		T50	22
arcs[PostTransSt=>EscalateSt]	4668	1			T4	2		T13	12		T15	16
arcs[InvalidSt=>EscalateSt]	14239	1			T7	55		T15	22		T10	174

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7421642	1			T1	116		T2	70		T3	5730
auto[0]	auto[IdleSt]	21019251	1			T1	124213		T2	50		T3	1982
auto[0]	auto[ClkMuxSt]	33578	1			T3	62		T4	68		T5	69
auto[0]	auto[CntIncrSt]	33237	1			T3	62		T4	68		T5	69
auto[0]	auto[CntProgSt]	1592244	1			T3	1607		T4	13374		T5	1171
auto[0]	auto[TransCheckSt]	25882	1			T3	62		T4	37		T5	69
auto[0]	auto[TokenHashSt]	36698050	1			T3	789		T4	1109		T5	752
auto[0]	auto[FlashRmaSt]	26989	1			T3	30		T4	33		T12	41
auto[0]	auto[TokenCheck0St]	12111	1			T3	30		T4	24		T12	21
auto[0]	auto[TokenCheck1St]	9003	1			T3	7		T4	22		T12	7
auto[0]	auto[TransProgSt]	407976	1			T4	542		T13	43		T15	50
auto[0]	auto[PostTransSt]	11593012	1			T2	915		T3	9377		T4	5
auto[0]	auto[ScrapSt]	203480	1			T10	19		T35	3		T36	3
auto[0]	auto[EscalateSt]	5412020	1			T4	4882		T13	864		T7	27295
auto[0]	auto[InvalidSt]	12304265	1			T7	104614		T15	1712		T10	137349
auto[1]	auto[ResetSt]	187	1			T4	5		T36	1		T50	4
auto[1]	auto[IdleSt]	140	1			T4	5		T36	7		T50	7
auto[1]	auto[ClkMuxSt]	35	1			T36	1		T208	1		T54	1
auto[1]	auto[CntIncrSt]	24	1			T36	1		T48	1		T49	1
auto[1]	auto[CntProgSt]	759	1			T4	22		T36	14		T50	27
auto[1]	auto[TransCheckSt]	61	1			T53	9		T54	4		T209	6
auto[1]	auto[TokenHashSt]	390	1			T4	9		T36	7		T50	6
auto[1]	auto[FlashRmaSt]	55	1			T4	1		T36	1		T50	3
auto[1]	auto[TokenCheck0St]	20	1			T36	1		T48	2		T208	1
auto[1]	auto[TokenCheck1St]	102	1			T4	2		T36	2		T50	2
auto[1]	auto[TransProgSt]	528	1			T4	10		T36	13		T50	14
auto[1]	auto[PostTransSt]	2373	1			T4	1		T13	8		T15	9
auto[1]	auto[ScrapSt]	41	1			T50	2		T49	1		T53	2
auto[1]	auto[EscalateSt]	1392132	1			T4	11846		T13	784		T7	2910
auto[1]	auto[InvalidSt]	7157	1			T7	30		T15	14		T10	80

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7421652	1			T1	116		T2	70		T3	5730
auto[0]	auto[IdleSt]	21019251	1			T1	124213		T2	50		T3	1982
auto[0]	auto[ClkMuxSt]	33577	1			T3	62		T4	68		T5	69
auto[0]	auto[CntIncrSt]	33231	1			T3	62		T4	68		T5	69
auto[0]	auto[CntProgSt]	1592255	1			T3	1607		T4	13377		T5	1171
auto[0]	auto[TransCheckSt]	25885	1			T3	62		T4	37		T5	69
auto[0]	auto[TokenHashSt]	36698072	1			T3	789		T4	1108		T5	752
auto[0]	auto[FlashRmaSt]	26976	1			T3	30		T4	32		T12	41
auto[0]	auto[TokenCheck0St]	12113	1			T3	30		T4	24		T12	21
auto[0]	auto[TokenCheck1St]	9010	1			T3	7		T4	23		T12	7
auto[0]	auto[TransProgSt]	407989	1			T4	539		T13	43		T15	50
auto[0]	auto[PostTransSt]	11593034	1			T2	915		T3	9377		T4	4
auto[0]	auto[ScrapSt]	203485	1			T10	19		T35	3		T36	2
auto[0]	auto[EscalateSt]	5434623	1			T4	6088		T13	1256		T7	27780
auto[0]	auto[InvalidSt]	12304340	1			T7	104619		T15	1718		T10	137335
auto[1]	auto[ResetSt]	177	1			T4	2		T36	3		T50	6
auto[1]	auto[IdleSt]	140	1			T4	2		T36	6		T50	6
auto[1]	auto[ClkMuxSt]	36	1			T36	4		T48	1		T49	1
auto[1]	auto[CntIncrSt]	30	1			T36	1		T49	1		T53	1
auto[1]	auto[CntProgSt]	748	1			T4	19		T36	20		T50	22
auto[1]	auto[TransCheckSt]	58	1			T49	2		T53	7		T54	2
auto[1]	auto[TokenHashSt]	368	1			T4	10		T36	10		T50	2
auto[1]	auto[FlashRmaSt]	68	1			T4	2		T50	2		T48	3
auto[1]	auto[TokenCheck0St]	18	1			T36	1		T49	1		T208	1
auto[1]	auto[TokenCheck1St]	95	1			T4	1		T36	3		T50	2
auto[1]	auto[TransProgSt]	515	1			T4	13		T36	11		T50	13
auto[1]	auto[PostTransSt]	2351	1			T4	2		T13	4		T15	7
auto[1]	auto[ScrapSt]	36	1			T36	1		T50	4		T49	1
auto[1]	auto[EscalateSt]	1369529	1			T4	10640		T13	392		T7	2425
auto[1]	auto[InvalidSt]	7082	1			T7	25		T15	8		T10	94