Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.99 95.59 93.38 100.00 98.55 99.00 96.11


Total test records in report: 1000
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T166 /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.497445272 Jun 28 07:43:28 PM PDT 24 Jun 28 07:56:54 PM PDT 24 101770578468 ps
T809 /workspace/coverage/default/41.lc_ctrl_prog_failure.1675344182 Jun 28 07:43:08 PM PDT 24 Jun 28 07:43:16 PM PDT 24 64572843 ps
T810 /workspace/coverage/default/43.lc_ctrl_stress_all.1994336500 Jun 28 07:43:11 PM PDT 24 Jun 28 07:44:26 PM PDT 24 4378509137 ps
T811 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2646543645 Jun 28 07:41:34 PM PDT 24 Jun 28 07:42:18 PM PDT 24 413364463 ps
T812 /workspace/coverage/default/14.lc_ctrl_security_escalation.1960552047 Jun 28 07:40:58 PM PDT 24 Jun 28 07:41:38 PM PDT 24 3864757140 ps
T813 /workspace/coverage/default/28.lc_ctrl_errors.3712164874 Jun 28 07:42:00 PM PDT 24 Jun 28 07:42:50 PM PDT 24 1165005259 ps
T814 /workspace/coverage/default/6.lc_ctrl_alert_test.3220230314 Jun 28 07:40:16 PM PDT 24 Jun 28 07:40:43 PM PDT 24 66436169 ps
T815 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1594862365 Jun 28 07:42:04 PM PDT 24 Jun 28 07:42:51 PM PDT 24 621557827 ps
T816 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2069997171 Jun 28 07:43:07 PM PDT 24 Jun 28 07:43:18 PM PDT 24 570363987 ps
T118 /workspace/coverage/default/45.lc_ctrl_stress_all.3775286502 Jun 28 07:43:16 PM PDT 24 Jun 28 07:44:36 PM PDT 24 2258688216 ps
T817 /workspace/coverage/default/7.lc_ctrl_stress_all.4276444547 Jun 28 07:40:16 PM PDT 24 Jun 28 07:41:11 PM PDT 24 1102218938 ps
T818 /workspace/coverage/default/47.lc_ctrl_security_escalation.972186793 Jun 28 07:43:16 PM PDT 24 Jun 28 07:43:39 PM PDT 24 1149922885 ps
T819 /workspace/coverage/default/13.lc_ctrl_stress_all.1810768749 Jun 28 07:40:59 PM PDT 24 Jun 28 07:43:22 PM PDT 24 27139864631 ps
T820 /workspace/coverage/default/21.lc_ctrl_alert_test.166619924 Jun 28 07:41:18 PM PDT 24 Jun 28 07:42:01 PM PDT 24 57414955 ps
T821 /workspace/coverage/default/15.lc_ctrl_jtag_access.1343123487 Jun 28 07:41:01 PM PDT 24 Jun 28 07:41:43 PM PDT 24 901143558 ps
T822 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1736776455 Jun 28 07:40:39 PM PDT 24 Jun 28 07:41:14 PM PDT 24 571264578 ps
T823 /workspace/coverage/default/19.lc_ctrl_state_failure.1674594213 Jun 28 07:41:11 PM PDT 24 Jun 28 07:42:11 PM PDT 24 267009683 ps
T824 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.353911632 Jun 28 07:40:23 PM PDT 24 Jun 28 07:40:57 PM PDT 24 293229732 ps
T825 /workspace/coverage/default/40.lc_ctrl_state_post_trans.3565546036 Jun 28 07:43:09 PM PDT 24 Jun 28 07:43:17 PM PDT 24 182007061 ps
T826 /workspace/coverage/default/14.lc_ctrl_jtag_access.4165600672 Jun 28 07:41:02 PM PDT 24 Jun 28 07:41:39 PM PDT 24 264008866 ps
T827 /workspace/coverage/default/2.lc_ctrl_sec_mubi.19782247 Jun 28 07:39:37 PM PDT 24 Jun 28 07:40:04 PM PDT 24 349671547 ps
T828 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.352917207 Jun 28 07:42:02 PM PDT 24 Jun 28 07:42:48 PM PDT 24 638379054 ps
T829 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1114071709 Jun 28 07:42:14 PM PDT 24 Jun 28 07:42:54 PM PDT 24 337965129 ps
T830 /workspace/coverage/default/49.lc_ctrl_sec_mubi.1158791874 Jun 28 07:43:29 PM PDT 24 Jun 28 07:43:49 PM PDT 24 279465020 ps
T831 /workspace/coverage/default/33.lc_ctrl_prog_failure.3482596128 Jun 28 07:42:13 PM PDT 24 Jun 28 07:42:44 PM PDT 24 603620185 ps
T832 /workspace/coverage/default/8.lc_ctrl_stress_all.1145721785 Jun 28 07:40:15 PM PDT 24 Jun 28 07:54:06 PM PDT 24 26828388589 ps
T833 /workspace/coverage/default/37.lc_ctrl_security_escalation.515109035 Jun 28 07:42:44 PM PDT 24 Jun 28 07:43:07 PM PDT 24 2511999785 ps
T834 /workspace/coverage/default/3.lc_ctrl_state_failure.1264045593 Jun 28 07:39:39 PM PDT 24 Jun 28 07:40:14 PM PDT 24 1138805016 ps
T835 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2316713811 Jun 28 07:40:23 PM PDT 24 Jun 28 07:41:01 PM PDT 24 575124834 ps
T836 /workspace/coverage/default/19.lc_ctrl_jtag_errors.2170517609 Jun 28 07:41:17 PM PDT 24 Jun 28 07:42:40 PM PDT 24 2562185309 ps
T837 /workspace/coverage/default/11.lc_ctrl_jtag_errors.846104015 Jun 28 07:40:40 PM PDT 24 Jun 28 07:42:11 PM PDT 24 27121811416 ps
T838 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3417072234 Jun 28 07:41:44 PM PDT 24 Jun 28 07:42:25 PM PDT 24 32771319 ps
T839 /workspace/coverage/default/0.lc_ctrl_jtag_priority.1013423539 Jun 28 07:39:34 PM PDT 24 Jun 28 07:40:12 PM PDT 24 6266955944 ps
T840 /workspace/coverage/default/6.lc_ctrl_errors.2873133294 Jun 28 07:40:11 PM PDT 24 Jun 28 07:40:53 PM PDT 24 1246312902 ps
T841 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2685852797 Jun 28 07:43:29 PM PDT 24 Jun 28 07:43:46 PM PDT 24 551974512 ps
T842 /workspace/coverage/default/6.lc_ctrl_stress_all.2178588500 Jun 28 07:40:16 PM PDT 24 Jun 28 07:42:53 PM PDT 24 4575574674 ps
T843 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1865556403 Jun 28 07:39:41 PM PDT 24 Jun 28 07:39:57 PM PDT 24 248057081 ps
T844 /workspace/coverage/default/26.lc_ctrl_jtag_access.1270887542 Jun 28 07:42:01 PM PDT 24 Jun 28 07:42:38 PM PDT 24 597603276 ps
T845 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.95059512 Jun 28 07:40:16 PM PDT 24 Jun 28 07:41:42 PM PDT 24 2620784054 ps
T203 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1811714386 Jun 28 07:39:33 PM PDT 24 Jun 28 07:39:41 PM PDT 24 21833190 ps
T846 /workspace/coverage/default/2.lc_ctrl_jtag_access.504193474 Jun 28 07:39:34 PM PDT 24 Jun 28 07:39:54 PM PDT 24 5463505017 ps
T847 /workspace/coverage/default/28.lc_ctrl_state_post_trans.4015989168 Jun 28 07:42:07 PM PDT 24 Jun 28 07:42:46 PM PDT 24 415575383 ps
T848 /workspace/coverage/default/43.lc_ctrl_jtag_access.2540797988 Jun 28 07:43:12 PM PDT 24 Jun 28 07:43:25 PM PDT 24 838980547 ps
T849 /workspace/coverage/default/20.lc_ctrl_prog_failure.2300784926 Jun 28 07:41:17 PM PDT 24 Jun 28 07:42:02 PM PDT 24 100192805 ps
T850 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3742085199 Jun 28 07:40:21 PM PDT 24 Jun 28 07:41:02 PM PDT 24 716837046 ps
T851 /workspace/coverage/default/1.lc_ctrl_alert_test.1294420752 Jun 28 07:39:39 PM PDT 24 Jun 28 07:39:52 PM PDT 24 51531772 ps
T852 /workspace/coverage/default/37.lc_ctrl_prog_failure.1131132542 Jun 28 07:42:46 PM PDT 24 Jun 28 07:43:00 PM PDT 24 88427462 ps
T853 /workspace/coverage/default/17.lc_ctrl_state_failure.2120165418 Jun 28 07:41:04 PM PDT 24 Jun 28 07:42:01 PM PDT 24 780520843 ps
T854 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4292152255 Jun 28 07:43:20 PM PDT 24 Jun 28 07:43:31 PM PDT 24 29088890 ps
T855 /workspace/coverage/default/40.lc_ctrl_alert_test.794510765 Jun 28 07:43:09 PM PDT 24 Jun 28 07:43:14 PM PDT 24 16354280 ps
T856 /workspace/coverage/default/39.lc_ctrl_state_failure.1020470853 Jun 28 07:42:48 PM PDT 24 Jun 28 07:43:30 PM PDT 24 355312917 ps
T857 /workspace/coverage/default/7.lc_ctrl_prog_failure.348128762 Jun 28 07:40:23 PM PDT 24 Jun 28 07:40:54 PM PDT 24 113644913 ps
T858 /workspace/coverage/default/33.lc_ctrl_security_escalation.231616369 Jun 28 07:42:23 PM PDT 24 Jun 28 07:42:53 PM PDT 24 308220485 ps
T859 /workspace/coverage/default/2.lc_ctrl_prog_failure.3909153169 Jun 28 07:39:43 PM PDT 24 Jun 28 07:39:58 PM PDT 24 294933943 ps
T860 /workspace/coverage/default/31.lc_ctrl_prog_failure.946860212 Jun 28 07:42:04 PM PDT 24 Jun 28 07:42:42 PM PDT 24 82378617 ps
T205 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.229828662 Jun 28 07:40:06 PM PDT 24 Jun 28 07:40:21 PM PDT 24 67742560 ps
T861 /workspace/coverage/default/36.lc_ctrl_state_failure.3202811494 Jun 28 07:42:14 PM PDT 24 Jun 28 07:43:01 PM PDT 24 215931264 ps
T862 /workspace/coverage/default/5.lc_ctrl_errors.494515161 Jun 28 07:40:06 PM PDT 24 Jun 28 07:40:31 PM PDT 24 604076744 ps
T863 /workspace/coverage/default/19.lc_ctrl_prog_failure.3883727888 Jun 28 07:41:01 PM PDT 24 Jun 28 07:41:36 PM PDT 24 47870351 ps
T864 /workspace/coverage/default/0.lc_ctrl_errors.2957617695 Jun 28 07:39:33 PM PDT 24 Jun 28 07:39:55 PM PDT 24 379717714 ps
T865 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2986716901 Jun 28 07:39:36 PM PDT 24 Jun 28 07:39:56 PM PDT 24 211297271 ps
T866 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1867884460 Jun 28 07:40:59 PM PDT 24 Jun 28 08:12:44 PM PDT 24 98990765507 ps
T867 /workspace/coverage/default/11.lc_ctrl_alert_test.2498317379 Jun 28 07:40:43 PM PDT 24 Jun 28 07:41:10 PM PDT 24 63319417 ps
T868 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1725808468 Jun 28 07:40:23 PM PDT 24 Jun 28 07:41:07 PM PDT 24 362877157 ps
T869 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3824209023 Jun 28 07:43:26 PM PDT 24 Jun 28 07:43:45 PM PDT 24 5814385657 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.978693900 Jun 28 07:48:54 PM PDT 24 Jun 28 07:49:01 PM PDT 24 16764689 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3828100638 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:38 PM PDT 24 188446373 ps
T132 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3535728690 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:45 PM PDT 24 11711366 ps
T152 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.797052776 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:54 PM PDT 24 82098551 ps
T123 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.243399794 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:44 PM PDT 24 101637293 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2134171479 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:34 PM PDT 24 24985796 ps
T173 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4272666303 Jun 28 07:50:18 PM PDT 24 Jun 28 07:50:23 PM PDT 24 103397222 ps
T120 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3824605660 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:39 PM PDT 24 213984186 ps
T150 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1434800470 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:41 PM PDT 24 552122879 ps
T151 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3715415118 Jun 28 07:48:44 PM PDT 24 Jun 28 07:49:02 PM PDT 24 1248464863 ps
T148 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3255846024 Jun 28 07:48:54 PM PDT 24 Jun 28 07:49:02 PM PDT 24 101862620 ps
T121 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1324143829 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:39 PM PDT 24 179717435 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1107474671 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:46 PM PDT 24 219813444 ps
T870 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.743498042 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 150996806 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1969301061 Jun 28 07:48:48 PM PDT 24 Jun 28 07:49:17 PM PDT 24 6319603050 ps
T167 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2937595416 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:32 PM PDT 24 26611285 ps
T124 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.431528031 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:48 PM PDT 24 551207862 ps
T125 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2878269910 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 273250728 ps
T149 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2406839023 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:45 PM PDT 24 813892793 ps
T168 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1795956351 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:36 PM PDT 24 105620915 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2145838589 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:54 PM PDT 24 557016745 ps
T169 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3036448048 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:46 PM PDT 24 170434660 ps
T126 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2277845919 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 156423214 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1530265879 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:40 PM PDT 24 124606072 ps
T137 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.400931195 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:30 PM PDT 24 121007567 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1790462832 Jun 28 07:49:35 PM PDT 24 Jun 28 07:49:44 PM PDT 24 32665658 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3164688977 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:50 PM PDT 24 132338098 ps
T147 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2922890703 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:45 PM PDT 24 53511134 ps
T143 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.180487095 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:40 PM PDT 24 77436477 ps
T875 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1199334142 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:57 PM PDT 24 31634068 ps
T135 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1348615358 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:39 PM PDT 24 65416124 ps
T876 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1392307817 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 112913699 ps
T185 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.761943138 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:34 PM PDT 24 165270113 ps
T141 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1153846272 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 267094315 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2214707703 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:53 PM PDT 24 1386469986 ps
T140 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3922966228 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:41 PM PDT 24 272070552 ps
T878 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.732182103 Jun 28 07:50:25 PM PDT 24 Jun 28 07:50:46 PM PDT 24 55115004 ps
T133 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.107895403 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:58 PM PDT 24 106392786 ps
T879 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.937396640 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 86527027 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2321128192 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:44 PM PDT 24 121886679 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2309592294 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:39 PM PDT 24 32048927 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1378732054 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:55 PM PDT 24 257662148 ps
T197 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1342743696 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:39 PM PDT 24 67769971 ps
T186 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3248810096 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:34 PM PDT 24 33250080 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1995644511 Jun 28 07:50:16 PM PDT 24 Jun 28 07:50:20 PM PDT 24 72579345 ps
T198 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.243054422 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 69152332 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3737107069 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:53 PM PDT 24 38340393 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1775409231 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:44 PM PDT 24 57440126 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4009341173 Jun 28 07:48:55 PM PDT 24 Jun 28 07:49:02 PM PDT 24 387820923 ps
T885 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3994086191 Jun 28 07:50:17 PM PDT 24 Jun 28 07:50:20 PM PDT 24 46350968 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.839737085 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:55 PM PDT 24 2055219560 ps
T145 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3057579940 Jun 28 07:50:18 PM PDT 24 Jun 28 07:50:24 PM PDT 24 101110620 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2236986982 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:37 PM PDT 24 434257266 ps
T199 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2433361055 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:56 PM PDT 24 282076744 ps
T888 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1838204788 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 40891171 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1283509058 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:27 PM PDT 24 91870309 ps
T890 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3456866002 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 217908567 ps
T891 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3266521709 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 50202591 ps
T188 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3094225120 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:41 PM PDT 24 42972761 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4163618815 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 175813113 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1612707330 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:35 PM PDT 24 64058205 ps
T893 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1167927883 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:34 PM PDT 24 18627587 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1516874722 Jun 28 07:48:48 PM PDT 24 Jun 28 07:48:58 PM PDT 24 103515799 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.704712346 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:54 PM PDT 24 1295007927 ps
T189 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4256108491 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 41503017 ps
T207 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.665060391 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:36 PM PDT 24 96491853 ps
T896 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3177550 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 14209838 ps
T897 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3158911814 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:50 PM PDT 24 2245505692 ps
T898 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.237769060 Jun 28 07:50:18 PM PDT 24 Jun 28 07:50:22 PM PDT 24 31599279 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2776122570 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:44 PM PDT 24 14680544 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2382058211 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:32 PM PDT 24 35895468 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2967430403 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:37 PM PDT 24 129909004 ps
T902 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2857767515 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 112057269 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.403997718 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:41 PM PDT 24 240054467 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3544531965 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:57 PM PDT 24 94138802 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3859016873 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:38 PM PDT 24 189113859 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1077630616 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 54813262 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.634167936 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:40 PM PDT 24 160505868 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2647021705 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 46150570 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3702630433 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:34 PM PDT 24 20934081 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1633911845 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:42 PM PDT 24 93029989 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4158577886 Jun 28 07:49:30 PM PDT 24 Jun 28 07:50:18 PM PDT 24 3856949300 ps
T911 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1301164948 Jun 28 07:49:33 PM PDT 24 Jun 28 07:50:09 PM PDT 24 25885904515 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.674774337 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 130711287 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2711728093 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:43 PM PDT 24 154787179 ps
T914 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2446189554 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:39 PM PDT 24 224965525 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3615223176 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:40 PM PDT 24 134004036 ps
T190 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1261796295 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 84737487 ps
T916 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3557630556 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 308981997 ps
T917 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4150473073 Jun 28 07:48:47 PM PDT 24 Jun 28 07:48:57 PM PDT 24 22861415 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1964843065 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:50 PM PDT 24 28537782 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3345425532 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:40 PM PDT 24 227628541 ps
T920 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1588476530 Jun 28 07:48:42 PM PDT 24 Jun 28 07:48:52 PM PDT 24 2615838919 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2486672478 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:55 PM PDT 24 26014114 ps
T922 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1712737735 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:39 PM PDT 24 86024290 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2847378132 Jun 28 07:48:51 PM PDT 24 Jun 28 07:49:10 PM PDT 24 969949993 ps
T924 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2046610603 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 200303789 ps
T925 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3806440077 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:39 PM PDT 24 115966477 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1619680640 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:36 PM PDT 24 49976686 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.817327404 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:57 PM PDT 24 205334720 ps
T928 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3256076581 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:35 PM PDT 24 42320222 ps
T929 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.592251005 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 53334867 ps
T930 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1298371111 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 74660070 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4198391698 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:55 PM PDT 24 44571894 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3447649850 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:32 PM PDT 24 32905954 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1361393913 Jun 28 07:49:34 PM PDT 24 Jun 28 07:50:00 PM PDT 24 1746643485 ps
T934 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3552611418 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 39565472 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1784239315 Jun 28 07:48:51 PM PDT 24 Jun 28 07:49:03 PM PDT 24 573015321 ps
T936 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2898007538 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:39 PM PDT 24 19308183 ps
T191 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2054569109 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:38 PM PDT 24 15784843 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2263810724 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 122460136 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2439774414 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:54 PM PDT 24 3024121306 ps
T130 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3831419159 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:40 PM PDT 24 206982796 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2084981912 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 37445633 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4021059529 Jun 28 07:50:18 PM PDT 24 Jun 28 07:50:23 PM PDT 24 51385003 ps
T941 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3611767693 Jun 28 07:50:19 PM PDT 24 Jun 28 07:50:31 PM PDT 24 39703848 ps
T942 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4183552433 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:59 PM PDT 24 1100267472 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.815845781 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:54 PM PDT 24 508847004 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3398023741 Jun 28 07:50:18 PM PDT 24 Jun 28 07:50:26 PM PDT 24 160778251 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1501281410 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:56 PM PDT 24 36607651 ps
T946 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3321938070 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:38 PM PDT 24 143060898 ps
T947 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1181394002 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:43 PM PDT 24 40256881 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.455087647 Jun 28 07:49:35 PM PDT 24 Jun 28 07:49:45 PM PDT 24 58839581 ps
T949 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1442168468 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:39 PM PDT 24 24710923 ps
T192 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2450782635 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:33 PM PDT 24 38509303 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.551259693 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 55923299 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2964478982 Jun 28 07:50:23 PM PDT 24 Jun 28 07:50:44 PM PDT 24 92390297 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3134531240 Jun 28 07:49:28 PM PDT 24 Jun 28 07:49:31 PM PDT 24 40638094 ps
T952 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.716390816 Jun 28 07:50:25 PM PDT 24 Jun 28 07:50:46 PM PDT 24 31566274 ps
T953 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3171503091 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:38 PM PDT 24 47349415 ps
T954 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3087727756 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:45 PM PDT 24 82734169 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.348756610 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:42 PM PDT 24 71838412 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3604634786 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 39065578 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1843473528 Jun 28 07:49:29 PM PDT 24 Jun 28 07:49:37 PM PDT 24 123012234 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1973026575 Jun 28 07:48:55 PM PDT 24 Jun 28 07:49:03 PM PDT 24 298790256 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.194899133 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:41 PM PDT 24 407703618 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1598142619 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:44 PM PDT 24 56407020 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.75561746 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:35 PM PDT 24 138436942 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1398949535 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:38 PM PDT 24 177708224 ps
T963 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4262181000 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:52 PM PDT 24 161103145 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.932715127 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:55 PM PDT 24 63721668 ps
T965 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2004576654 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:42 PM PDT 24 1598777324 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4288406218 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 328867383 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2934856003 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 147897411 ps
T968 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3559186381 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:39 PM PDT 24 86765988 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3779613989 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:44 PM PDT 24 288146992 ps
T136 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4018369157 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 72802350 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.896688624 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:54 PM PDT 24 45735282 ps
T971 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.270535176 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:56 PM PDT 24 224271802 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.448933219 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:41 PM PDT 24 224363433 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.875651074 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 70728496 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2563455922 Jun 28 07:49:31 PM PDT 24 Jun 28 07:49:37 PM PDT 24 109369376 ps
T975 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1630628261 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:42 PM PDT 24 29145010 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.111986402 Jun 28 07:49:36 PM PDT 24 Jun 28 07:49:48 PM PDT 24 228693335 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1782171931 Jun 28 07:49:30 PM PDT 24 Jun 28 07:49:35 PM PDT 24 68500603 ps
T978 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.895043168 Jun 28 07:50:17 PM PDT 24 Jun 28 07:50:20 PM PDT 24 86398150 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3750128175 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:59 PM PDT 24 371989567 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.120475789 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:40 PM PDT 24 20244303 ps
T981 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3276615205 Jun 28 07:50:24 PM PDT 24 Jun 28 07:50:44 PM PDT 24 100438171 ps
T982 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2095498528 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:38 PM PDT 24 65261090 ps
T983 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3411602493 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:42 PM PDT 24 13644182 ps
T146 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4211440733 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:43 PM PDT 24 85370364 ps
T196 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1467826499 Jun 28 07:48:44 PM PDT 24 Jun 28 07:48:54 PM PDT 24 741347072 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3213374507 Jun 28 07:49:34 PM PDT 24 Jun 28 07:49:43 PM PDT 24 66943734 ps
T985 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.214889793 Jun 28 07:50:22 PM PDT 24 Jun 28 07:50:41 PM PDT 24 83800782 ps
T144 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2669332853 Jun 28 07:49:35 PM PDT 24 Jun 28 07:49:43 PM PDT 24 56244752 ps
T139 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2634842247 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 107586077 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.964847828 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:37 PM PDT 24 47550139 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3667550718 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:38 PM PDT 24 21851798 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.370329326 Jun 28 07:49:36 PM PDT 24 Jun 28 07:50:09 PM PDT 24 5237430847 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2281392074 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:43 PM PDT 24 215926724 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1793134313 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:39 PM PDT 24 49099376 ps
T991 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3554679096 Jun 28 07:50:23 PM PDT 24 Jun 28 07:50:44 PM PDT 24 44961249 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.306802805 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:55 PM PDT 24 170399306 ps
T993 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1733725244 Jun 28 07:50:21 PM PDT 24 Jun 28 07:50:50 PM PDT 24 5531401240 ps
T994 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3217847746 Jun 28 07:48:46 PM PDT 24 Jun 28 07:48:58 PM PDT 24 301374100 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4243980497 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 38292191 ps
T996 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.565376456 Jun 28 07:48:43 PM PDT 24 Jun 28 07:48:48 PM PDT 24 179293486 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.629746337 Jun 28 07:48:45 PM PDT 24 Jun 28 07:48:56 PM PDT 24 83939154 ps
T193 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1222851655 Jun 28 07:49:35 PM PDT 24 Jun 28 07:49:42 PM PDT 24 45102592 ps
T998 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3928344137 Jun 28 07:49:35 PM PDT 24 Jun 28 07:49:44 PM PDT 24 1170574225 ps
T999 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.979421774 Jun 28 07:50:15 PM PDT 24 Jun 28 07:50:16 PM PDT 24 79435144 ps
T195 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2700303527 Jun 28 07:49:32 PM PDT 24 Jun 28 07:49:39 PM PDT 24 22624432 ps
T142 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2197337678 Jun 28 07:49:33 PM PDT 24 Jun 28 07:49:42 PM PDT 24 129764380 ps
T1000 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1924390763 Jun 28 07:50:20 PM PDT 24 Jun 28 07:50:36 PM PDT 24 31306016 ps

Test location /workspace/coverage/default/35.lc_ctrl_errors.771981906
Short name T13
Test name
Test status
Simulation time 2062542650 ps
CPU time 15.2 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 226584 kb
Host smart-aa5d74d2-dc3f-4831-bfea-50c35c8bb02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771981906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.771981906
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1456277507
Short name T10
Test name
Test status
Simulation time 29866807514 ps
CPU time 263.01 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:48:00 PM PDT 24
Peak memory 284044 kb
Host smart-b6c62bcf-8902-4fe6-a219-cec6d9766503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456277507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1456277507
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3235925904
Short name T49
Test name
Test status
Simulation time 226464786 ps
CPU time 9.17 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:42:24 PM PDT 24
Peak memory 225780 kb
Host smart-955411b6-dd4d-400f-90d8-a02d05150493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235925904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3235925904
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3141719233
Short name T223
Test name
Test status
Simulation time 972462442 ps
CPU time 12.7 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:47 PM PDT 24
Peak memory 226428 kb
Host smart-d424ffae-b640-43bb-9fa0-562ffe04c767
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141719233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3141719233
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.4132336630
Short name T154
Test name
Test status
Simulation time 46483776772 ps
CPU time 702.49 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:52:45 PM PDT 24
Peak memory 430868 kb
Host smart-8b8fffcf-b53a-4861-8dfc-4f663eb22d6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4132336630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.4132336630
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3420697276
Short name T2
Test name
Test status
Simulation time 10369919 ps
CPU time 0.79 seconds
Started Jun 28 07:40:40 PM PDT 24
Finished Jun 28 07:41:05 PM PDT 24
Peak memory 209424 kb
Host smart-d8fcd7c7-df4e-448d-8f07-4c011c5d17cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420697276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3420697276
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1324455873
Short name T31
Test name
Test status
Simulation time 217331831 ps
CPU time 8.41 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:00 PM PDT 24
Peak memory 226400 kb
Host smart-c96981d1-6d75-49b5-bf34-6541c2aad6e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324455873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
324455873
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.408404902
Short name T51
Test name
Test status
Simulation time 1057751479 ps
CPU time 42.24 seconds
Started Jun 28 07:39:41 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 270244 kb
Host smart-fe604cc0-8621-4dc7-bae2-573d9d2ed2cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408404902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.408404902
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1912133669
Short name T84
Test name
Test status
Simulation time 47413266911 ps
CPU time 409.19 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:49:26 PM PDT 24
Peak memory 422536 kb
Host smart-792bd78f-00e2-42bc-a463-6252cc1d6c3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1912133669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1912133669
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2878269910
Short name T125
Test name
Test status
Simulation time 273250728 ps
CPU time 3.86 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217424 kb
Host smart-c91c32be-14b6-40e5-ba99-4c77e4b1d538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878269910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2878269910
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1270636423
Short name T170
Test name
Test status
Simulation time 14186875851 ps
CPU time 238.24 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:44:23 PM PDT 24
Peak memory 272132 kb
Host smart-df08c1b0-56d3-4483-9cd4-05d148620b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270636423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1270636423
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3255846024
Short name T148
Test name
Test status
Simulation time 101862620 ps
CPU time 2.22 seconds
Started Jun 28 07:48:54 PM PDT 24
Finished Jun 28 07:49:02 PM PDT 24
Peak memory 217372 kb
Host smart-ba6d49b0-8d39-485e-8ba3-8c72809a29a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325584
6024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3255846024
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.675357755
Short name T1
Test name
Test status
Simulation time 1295168130 ps
CPU time 12.33 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:54 PM PDT 24
Peak memory 217580 kb
Host smart-d8cc0542-380b-48c9-b08c-4f5581468863
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675357755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.675357755
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.85457473
Short name T14
Test name
Test status
Simulation time 13546239 ps
CPU time 0.84 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 209172 kb
Host smart-5b72fb2a-538b-4af1-8a8d-3dbc17c7ced2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85457473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.85457473
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2937595416
Short name T167
Test name
Test status
Simulation time 26611285 ps
CPU time 1.04 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:32 PM PDT 24
Peak memory 209164 kb
Host smart-687b68d8-f092-441d-a7b4-1cea432382aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937595416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2937595416
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3922966228
Short name T140
Test name
Test status
Simulation time 272070552 ps
CPU time 4.8 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:41 PM PDT 24
Peak memory 217272 kb
Host smart-f7929688-2fc9-497f-aff3-3edc4238bb4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922966228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3922966228
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4131899270
Short name T11
Test name
Test status
Simulation time 1523131774 ps
CPU time 15.9 seconds
Started Jun 28 07:40:14 PM PDT 24
Finished Jun 28 07:40:55 PM PDT 24
Peak memory 247132 kb
Host smart-7e87f9f2-3236-49e1-8493-c65aafc5f20e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131899270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4131899270
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.865281245
Short name T75
Test name
Test status
Simulation time 279171601 ps
CPU time 6.27 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:42:00 PM PDT 24
Peak memory 247644 kb
Host smart-ec905109-80a7-40e1-b437-8f8e32bfe4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865281245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.865281245
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2277845919
Short name T126
Test name
Test status
Simulation time 156423214 ps
CPU time 3.6 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 217312 kb
Host smart-5f4cabc5-ee85-4e76-8e6f-664390825c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277845919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2277845919
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2130944269
Short name T54
Test name
Test status
Simulation time 1358268011 ps
CPU time 8.77 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 218704 kb
Host smart-881ef2f6-1652-4b7b-bbd6-dbac4a9e64d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130944269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2130944269
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3352644404
Short name T93
Test name
Test status
Simulation time 192743329930 ps
CPU time 656.1 seconds
Started Jun 28 07:43:32 PM PDT 24
Finished Jun 28 07:54:36 PM PDT 24
Peak memory 448200 kb
Host smart-716fb60b-8e99-4dc6-be58-1752517c8237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3352644404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3352644404
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.400931195
Short name T137
Test name
Test status
Simulation time 121007567 ps
CPU time 4.4 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:30 PM PDT 24
Peak memory 217324 kb
Host smart-47076161-b1b3-4ded-bfc7-0ad89d6d8197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400931195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.400931195
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3775286502
Short name T118
Test name
Test status
Simulation time 2258688216 ps
CPU time 67.96 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:44:36 PM PDT 24
Peak memory 273728 kb
Host smart-67c20c50-6728-4ac8-a618-3d784643ec2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775286502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3775286502
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3737107069
Short name T187
Test name
Test status
Simulation time 38340393 ps
CPU time 0.95 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:53 PM PDT 24
Peak memory 209256 kb
Host smart-12b6f317-3092-4af0-9045-c4d61dd7fc32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737107069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3737107069
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2539236857
Short name T104
Test name
Test status
Simulation time 103455056719 ps
CPU time 826.18 seconds
Started Jun 28 07:41:16 PM PDT 24
Finished Jun 28 07:55:42 PM PDT 24
Peak memory 340556 kb
Host smart-dd423f52-3682-4b0f-853f-1efdf5323058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2539236857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2539236857
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1479296623
Short name T35
Test name
Test status
Simulation time 405605843 ps
CPU time 24.74 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:40:13 PM PDT 24
Peak memory 269700 kb
Host smart-b30e206e-9999-4175-8c08-2386e6816cc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479296623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1479296623
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3057579940
Short name T145
Test name
Test status
Simulation time 101110620 ps
CPU time 4.12 seconds
Started Jun 28 07:50:18 PM PDT 24
Finished Jun 28 07:50:24 PM PDT 24
Peak memory 217324 kb
Host smart-8375a559-a345-4a4f-b42a-bdc1433da8bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057579940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3057579940
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1153846272
Short name T141
Test name
Test status
Simulation time 267094315 ps
CPU time 1.91 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 221664 kb
Host smart-6f0ac490-60a0-4339-9951-6e580c8eb280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153846272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1153846272
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4018369157
Short name T136
Test name
Test status
Simulation time 72802350 ps
CPU time 2.2 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 221672 kb
Host smart-b5f7efa6-9e41-42ae-b1bf-d96658a34f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018369157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4018369157
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2634842247
Short name T139
Test name
Test status
Simulation time 107586077 ps
CPU time 2.72 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 222084 kb
Host smart-09deb1d9-6e53-48f6-ad31-7bde08b2d122
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634842247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2634842247
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1695873968
Short name T206
Test name
Test status
Simulation time 16067896 ps
CPU time 0.77 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:39:49 PM PDT 24
Peak memory 209320 kb
Host smart-16a84782-1c52-4d65-95c5-a93a7610eae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695873968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1695873968
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1811714386
Short name T203
Test name
Test status
Simulation time 21833190 ps
CPU time 0.91 seconds
Started Jun 28 07:39:33 PM PDT 24
Finished Jun 28 07:39:41 PM PDT 24
Peak memory 209120 kb
Host smart-bfd7ad3b-1649-4268-a976-c8d0a4142eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811714386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1811714386
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4214621738
Short name T204
Test name
Test status
Simulation time 148546777 ps
CPU time 0.83 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:46 PM PDT 24
Peak memory 209180 kb
Host smart-7c83995c-9a2d-460a-882d-99bdc14cae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214621738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4214621738
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.107895403
Short name T133
Test name
Test status
Simulation time 106392786 ps
CPU time 2.73 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:58 PM PDT 24
Peak memory 221908 kb
Host smart-0706624f-4199-49ec-af51-47a02ea05e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107895403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.107895403
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3831419159
Short name T130
Test name
Test status
Simulation time 206982796 ps
CPU time 2.89 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:40 PM PDT 24
Peak memory 222320 kb
Host smart-64b7e869-2971-42ba-ae24-4270e4fd2f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831419159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3831419159
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2609468635
Short name T47
Test name
Test status
Simulation time 390679817 ps
CPU time 11.66 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 218644 kb
Host smart-f424e44a-a6af-41a5-83a5-7eaa18cc8ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609468635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2609468635
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2289084583
Short name T7
Test name
Test status
Simulation time 7706144472 ps
CPU time 50.51 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:41:13 PM PDT 24
Peak memory 284080 kb
Host smart-39981fcf-09ab-4701-8896-bbeafdaeeeeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289084583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2289084583
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.946802206
Short name T5
Test name
Test status
Simulation time 303082436 ps
CPU time 10.15 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:44 PM PDT 24
Peak memory 218672 kb
Host smart-ab8eb008-f76a-46f9-9c14-55460e5458fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946802206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.946802206
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3544531965
Short name T904
Test name
Test status
Simulation time 94138802 ps
CPU time 1.13 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:57 PM PDT 24
Peak memory 209100 kb
Host smart-25ff795c-100c-47aa-a4f2-e55bed2fce8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544531965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3544531965
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1467826499
Short name T196
Test name
Test status
Simulation time 741347072 ps
CPU time 2.72 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:54 PM PDT 24
Peak memory 217252 kb
Host smart-3ab97d93-39de-403e-b687-416db35ca00c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467826499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1467826499
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1501281410
Short name T945
Test name
Test status
Simulation time 36607651 ps
CPU time 1 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:56 PM PDT 24
Peak memory 209592 kb
Host smart-630f4f97-6c0c-4f86-b024-cd5c4a6bd5ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501281410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1501281410
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1964843065
Short name T918
Test name
Test status
Simulation time 28537782 ps
CPU time 1.25 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:50 PM PDT 24
Peak memory 218440 kb
Host smart-6c089d60-5cfe-43e3-8231-93739858ad43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964843065 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1964843065
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.797052776
Short name T152
Test name
Test status
Simulation time 82098551 ps
CPU time 1.45 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:54 PM PDT 24
Peak memory 208956 kb
Host smart-55e115e1-c6d8-402d-a291-b54766292241
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797052776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.797052776
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.815845781
Short name T943
Test name
Test status
Simulation time 508847004 ps
CPU time 5.48 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:54 PM PDT 24
Peak memory 216720 kb
Host smart-8f439888-2444-4df0-8ec6-9ee6e29a8cb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815845781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.815845781
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1588476530
Short name T920
Test name
Test status
Simulation time 2615838919 ps
CPU time 6.49 seconds
Started Jun 28 07:48:42 PM PDT 24
Finished Jun 28 07:48:52 PM PDT 24
Peak memory 217088 kb
Host smart-2c2cc5be-eed1-49c7-9cbb-6f36f5a770c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588476530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1588476530
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.306802805
Short name T992
Test name
Test status
Simulation time 170399306 ps
CPU time 1.7 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:55 PM PDT 24
Peak memory 217264 kb
Host smart-c9a99349-4789-415e-bcdc-430ecc35f3b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306802805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.306802805
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.932715127
Short name T964
Test name
Test status
Simulation time 63721668 ps
CPU time 1.6 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:55 PM PDT 24
Peak memory 218952 kb
Host smart-7212cf5e-a345-4f16-94c9-809dcf8a053b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932715
127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.932715127
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3164688977
Short name T874
Test name
Test status
Simulation time 132338098 ps
CPU time 1.51 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:50 PM PDT 24
Peak memory 217068 kb
Host smart-a3f27732-3460-4f88-b962-6c444a0aa096
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164688977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3164688977
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2486672478
Short name T921
Test name
Test status
Simulation time 26014114 ps
CPU time 1.18 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:55 PM PDT 24
Peak memory 217272 kb
Host smart-67ead1ba-833a-4acb-841c-508e14cf56f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486672478 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2486672478
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.817327404
Short name T927
Test name
Test status
Simulation time 205334720 ps
CPU time 1.22 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:57 PM PDT 24
Peak memory 209224 kb
Host smart-0de0ceb9-6000-4e9e-8adc-198a89c96174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817327404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.817327404
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.565376456
Short name T996
Test name
Test status
Simulation time 179293486 ps
CPU time 2.72 seconds
Started Jun 28 07:48:43 PM PDT 24
Finished Jun 28 07:48:48 PM PDT 24
Peak memory 218360 kb
Host smart-26d867db-278f-461a-b656-1e98e8484e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565376456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.565376456
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.270535176
Short name T971
Test name
Test status
Simulation time 224271802 ps
CPU time 4.19 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:56 PM PDT 24
Peak memory 217448 kb
Host smart-3f5799c6-9121-4962-af44-78725a640a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270535176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.270535176
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4150473073
Short name T917
Test name
Test status
Simulation time 22861415 ps
CPU time 1.37 seconds
Started Jun 28 07:48:47 PM PDT 24
Finished Jun 28 07:48:57 PM PDT 24
Peak memory 217312 kb
Host smart-97448186-e006-4ecb-b154-54a5d0ce539a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150473073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4150473073
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1378732054
Short name T882
Test name
Test status
Simulation time 257662148 ps
CPU time 2.14 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:55 PM PDT 24
Peak memory 209068 kb
Host smart-d5eb09f1-2800-431c-a396-725f84089c6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378732054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1378732054
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1516874722
Short name T894
Test name
Test status
Simulation time 103515799 ps
CPU time 1 seconds
Started Jun 28 07:48:48 PM PDT 24
Finished Jun 28 07:48:58 PM PDT 24
Peak memory 210140 kb
Host smart-55c3b5dc-59a0-4059-a287-1efbd79cba7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516874722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1516874722
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1199334142
Short name T875
Test name
Test status
Simulation time 31634068 ps
CPU time 1.15 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:57 PM PDT 24
Peak memory 221440 kb
Host smart-eb65c41a-ae9b-468b-a377-ba6f45f615de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199334142 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1199334142
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.978693900
Short name T131
Test name
Test status
Simulation time 16764689 ps
CPU time 1.12 seconds
Started Jun 28 07:48:54 PM PDT 24
Finished Jun 28 07:49:01 PM PDT 24
Peak memory 209100 kb
Host smart-c4a15ec1-229e-4d1d-be68-2201b118cc8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978693900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.978693900
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4198391698
Short name T931
Test name
Test status
Simulation time 44571894 ps
CPU time 1.1 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:55 PM PDT 24
Peak memory 208956 kb
Host smart-0de782d6-b8b3-4bcd-990b-64985a8a32d6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198391698 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4198391698
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3715415118
Short name T151
Test name
Test status
Simulation time 1248464863 ps
CPU time 13.47 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:49:02 PM PDT 24
Peak memory 216844 kb
Host smart-2a8f6607-29e3-429a-8626-536bb9b9e835
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715415118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3715415118
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2847378132
Short name T923
Test name
Test status
Simulation time 969949993 ps
CPU time 10.69 seconds
Started Jun 28 07:48:51 PM PDT 24
Finished Jun 28 07:49:10 PM PDT 24
Peak memory 208784 kb
Host smart-875692df-4404-4538-b0af-2d6dfe468c38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847378132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2847378132
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4262181000
Short name T963
Test name
Test status
Simulation time 161103145 ps
CPU time 1.24 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:52 PM PDT 24
Peak memory 210456 kb
Host smart-95a02c95-5c13-49f9-92da-d8e5fce1de71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262181000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.4262181000
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1784239315
Short name T935
Test name
Test status
Simulation time 573015321 ps
CPU time 3.76 seconds
Started Jun 28 07:48:51 PM PDT 24
Finished Jun 28 07:49:03 PM PDT 24
Peak memory 219532 kb
Host smart-25c7ee14-8c11-4c41-9286-f8861fe10f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178423
9315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1784239315
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3217847746
Short name T994
Test name
Test status
Simulation time 301374100 ps
CPU time 2.16 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:58 PM PDT 24
Peak memory 209048 kb
Host smart-1a0ca25e-892f-4b57-a5fc-7bf6b027f0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217847746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3217847746
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.896688624
Short name T970
Test name
Test status
Simulation time 45735282 ps
CPU time 0.96 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:54 PM PDT 24
Peak memory 209252 kb
Host smart-ebf2dbe7-a406-4bfc-966d-c3b21b146ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896688624 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.896688624
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.629746337
Short name T997
Test name
Test status
Simulation time 83939154 ps
CPU time 1.92 seconds
Started Jun 28 07:48:45 PM PDT 24
Finished Jun 28 07:48:56 PM PDT 24
Peak memory 209196 kb
Host smart-0044a703-2315-4fe0-9a62-53952fd129b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629746337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.629746337
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2145838589
Short name T129
Test name
Test status
Simulation time 557016745 ps
CPU time 3.75 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:54 PM PDT 24
Peak memory 217356 kb
Host smart-b5f7248a-cc93-4e6d-a44d-ba50f443b9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145838589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2145838589
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1167927883
Short name T893
Test name
Test status
Simulation time 18627587 ps
CPU time 1.26 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:34 PM PDT 24
Peak memory 217496 kb
Host smart-50a2a8ae-e4a9-4583-80ed-067db3dea1a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167927883 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1167927883
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2964478982
Short name T951
Test name
Test status
Simulation time 92390297 ps
CPU time 1.03 seconds
Started Jun 28 07:50:23 PM PDT 24
Finished Jun 28 07:50:44 PM PDT 24
Peak memory 209092 kb
Host smart-3fd62b5c-007d-491e-b4fc-bd4773dd0823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964478982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2964478982
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3552611418
Short name T934
Test name
Test status
Simulation time 39565472 ps
CPU time 1.26 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217348 kb
Host smart-7ebdf5a1-e65f-4d48-85e7-15e5811bb250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552611418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3552611418
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3806440077
Short name T925
Test name
Test status
Simulation time 115966477 ps
CPU time 4.45 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 217272 kb
Host smart-5138f846-7f36-4ac9-a6d4-a7af5e3a0c76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806440077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3806440077
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3266521709
Short name T891
Test name
Test status
Simulation time 50202591 ps
CPU time 1.09 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 218384 kb
Host smart-46d55a26-4f53-4a09-bf6d-999db403fde5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266521709 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3266521709
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1261796295
Short name T190
Test name
Test status
Simulation time 84737487 ps
CPU time 1.06 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 209120 kb
Host smart-40f6c6cc-bb8e-4ebf-8d59-102d40c6aac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261796295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1261796295
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1795956351
Short name T168
Test name
Test status
Simulation time 105620915 ps
CPU time 2.02 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:36 PM PDT 24
Peak memory 217396 kb
Host smart-786056da-a879-49d4-9954-49b32decc949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795956351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1795956351
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1107474671
Short name T122
Test name
Test status
Simulation time 219813444 ps
CPU time 3.29 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:46 PM PDT 24
Peak memory 217364 kb
Host smart-09e36b17-a7eb-4200-9c2c-40e6ae8b46c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107474671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1107474671
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1324143829
Short name T121
Test name
Test status
Simulation time 179717435 ps
CPU time 2 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 221884 kb
Host smart-a4fc613d-2368-45fb-9e21-2fe4c7b1b35b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324143829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1324143829
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.732182103
Short name T878
Test name
Test status
Simulation time 55115004 ps
CPU time 1.29 seconds
Started Jun 28 07:50:25 PM PDT 24
Finished Jun 28 07:50:46 PM PDT 24
Peak memory 217520 kb
Host smart-2bab6bee-8414-43ec-afcb-518489c63db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732182103 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.732182103
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2898007538
Short name T936
Test name
Test status
Simulation time 19308183 ps
CPU time 0.98 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 208828 kb
Host smart-5b94466a-5e52-40b4-9df9-1646f8bdceee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898007538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2898007538
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3554679096
Short name T991
Test name
Test status
Simulation time 44961249 ps
CPU time 1.31 seconds
Started Jun 28 07:50:23 PM PDT 24
Finished Jun 28 07:50:44 PM PDT 24
Peak memory 209128 kb
Host smart-627b43b7-7d63-4681-9131-bc80dd637c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554679096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3554679096
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1838204788
Short name T888
Test name
Test status
Simulation time 40891171 ps
CPU time 1.99 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 217272 kb
Host smart-e8665deb-82a1-46bd-ad6e-809547704434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838204788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1838204788
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1348615358
Short name T135
Test name
Test status
Simulation time 65416124 ps
CPU time 1.95 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 221972 kb
Host smart-5f55ca88-0788-4c88-a134-ea0f7e1ac932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348615358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1348615358
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4272666303
Short name T173
Test name
Test status
Simulation time 103397222 ps
CPU time 1.48 seconds
Started Jun 28 07:50:18 PM PDT 24
Finished Jun 28 07:50:23 PM PDT 24
Peak memory 221600 kb
Host smart-f1ae1a59-749e-4c79-ab69-80fdc52fbbb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272666303 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4272666303
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3994086191
Short name T885
Test name
Test status
Simulation time 46350968 ps
CPU time 0.85 seconds
Started Jun 28 07:50:17 PM PDT 24
Finished Jun 28 07:50:20 PM PDT 24
Peak memory 209096 kb
Host smart-967ba02d-3f8e-4d64-9d00-5822d957455f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994086191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3994086191
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1342743696
Short name T197
Test name
Test status
Simulation time 67769971 ps
CPU time 1.68 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 211308 kb
Host smart-a674c640-9bbd-4e1b-a840-0a1185735be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342743696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1342743696
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2446189554
Short name T914
Test name
Test status
Simulation time 224965525 ps
CPU time 4.65 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 217272 kb
Host smart-2cd47582-a012-4150-9788-773e08424f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446189554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2446189554
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2922890703
Short name T147
Test name
Test status
Simulation time 53511134 ps
CPU time 2.52 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:45 PM PDT 24
Peak memory 217324 kb
Host smart-fc9cd1d8-a70f-428c-bb7a-8f76cdee4f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922890703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2922890703
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.243399794
Short name T123
Test name
Test status
Simulation time 101637293 ps
CPU time 1.15 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:44 PM PDT 24
Peak memory 217568 kb
Host smart-20b30318-b866-4fde-8b00-cfc3d3ac8f04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243399794 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.243399794
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3276615205
Short name T981
Test name
Test status
Simulation time 100438171 ps
CPU time 0.97 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:44 PM PDT 24
Peak memory 208472 kb
Host smart-89762d87-3a8a-4cae-8f74-7c2e309180cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276615205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3276615205
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.895043168
Short name T978
Test name
Test status
Simulation time 86398150 ps
CPU time 1.28 seconds
Started Jun 28 07:50:17 PM PDT 24
Finished Jun 28 07:50:20 PM PDT 24
Peak memory 209096 kb
Host smart-f6ddec61-01f7-44ff-b530-6da256596ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895043168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.895043168
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3557630556
Short name T916
Test name
Test status
Simulation time 308981997 ps
CPU time 5.29 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217264 kb
Host smart-752cf61b-8d6c-4ce9-8dbd-0db6266c8dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557630556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3557630556
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2046610603
Short name T924
Test name
Test status
Simulation time 200303789 ps
CPU time 0.95 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217452 kb
Host smart-3b80586c-4c3a-4b09-8d32-787fc13cc8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046610603 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2046610603
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1712737735
Short name T922
Test name
Test status
Simulation time 86024290 ps
CPU time 1.12 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 209112 kb
Host smart-6c686528-e171-4774-892d-37088fa0359d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712737735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1712737735
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2236986982
Short name T887
Test name
Test status
Simulation time 434257266 ps
CPU time 4.19 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:37 PM PDT 24
Peak memory 217356 kb
Host smart-8453fdaf-a946-4d5f-82ce-1f8c82505d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236986982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2236986982
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.665060391
Short name T207
Test name
Test status
Simulation time 96491853 ps
CPU time 1.76 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:36 PM PDT 24
Peak memory 221428 kb
Host smart-63e96724-d289-4238-abfc-b017520ce8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665060391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.665060391
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3171503091
Short name T953
Test name
Test status
Simulation time 47349415 ps
CPU time 1.6 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 222676 kb
Host smart-fc0a0623-ec4a-413e-911c-0564a3738a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171503091 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3171503091
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4256108491
Short name T189
Test name
Test status
Simulation time 41503017 ps
CPU time 0.87 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 209000 kb
Host smart-b81e32c4-faac-4a7b-9423-24008deaab5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256108491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4256108491
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.592251005
Short name T929
Test name
Test status
Simulation time 53334867 ps
CPU time 1.06 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 209124 kb
Host smart-c24f67e8-074a-4466-8d5f-44d2db3ad098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592251005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.592251005
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.431528031
Short name T124
Test name
Test status
Simulation time 551207862 ps
CPU time 3.44 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:48 PM PDT 24
Peak memory 217296 kb
Host smart-f4b13beb-13b7-4640-a764-cafe6b1ca21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431528031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.431528031
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.180487095
Short name T143
Test name
Test status
Simulation time 77436477 ps
CPU time 3.43 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:40 PM PDT 24
Peak memory 217356 kb
Host smart-c35d98ff-e9b2-47d5-a4b7-fcc2a2018ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180487095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.180487095
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2857767515
Short name T902
Test name
Test status
Simulation time 112057269 ps
CPU time 1.29 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 218544 kb
Host smart-ba1a13b6-f93e-4c2b-99b7-0c83fad4de89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857767515 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2857767515
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2450782635
Short name T192
Test name
Test status
Simulation time 38509303 ps
CPU time 0.86 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:33 PM PDT 24
Peak memory 209128 kb
Host smart-f6eba3a1-feee-432d-b25f-5b0113de726b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450782635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2450782635
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3036448048
Short name T169
Test name
Test status
Simulation time 170434660 ps
CPU time 1.97 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:46 PM PDT 24
Peak memory 217328 kb
Host smart-c39fef6d-4d6d-4d32-9465-9dfdf2d37cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036448048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3036448048
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3559186381
Short name T968
Test name
Test status
Simulation time 86765988 ps
CPU time 1.32 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 217468 kb
Host smart-352587a9-bd72-4aa2-aea6-ad1d7b4ae20f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559186381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3559186381
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.716390816
Short name T952
Test name
Test status
Simulation time 31566274 ps
CPU time 1.4 seconds
Started Jun 28 07:50:25 PM PDT 24
Finished Jun 28 07:50:46 PM PDT 24
Peak memory 217624 kb
Host smart-6578d726-e2f7-4dd8-a931-ad83cc8ebb69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716390816 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.716390816
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.964847828
Short name T986
Test name
Test status
Simulation time 47550139 ps
CPU time 0.96 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:37 PM PDT 24
Peak memory 209124 kb
Host smart-7a4f2a48-5b6e-4103-9182-e6e8a41d74f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964847828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.964847828
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3321938070
Short name T946
Test name
Test status
Simulation time 143060898 ps
CPU time 0.99 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 209204 kb
Host smart-6002302b-d150-4df4-a50a-718ed3d5f95d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321938070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3321938070
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3456866002
Short name T890
Test name
Test status
Simulation time 217908567 ps
CPU time 1.8 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217372 kb
Host smart-46c26de4-5eed-404f-bfe2-26f4c577e725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456866002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3456866002
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2095498528
Short name T982
Test name
Test status
Simulation time 65261090 ps
CPU time 1.33 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 217532 kb
Host smart-fdacea80-4577-4ee7-a05d-3c8c1cf0e9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095498528 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2095498528
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3177550
Short name T896
Test name
Test status
Simulation time 14209838 ps
CPU time 0.89 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 209108 kb
Host smart-2afa8416-5d80-448d-a2c3-edfe2cba5d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3177550
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3611767693
Short name T941
Test name
Test status
Simulation time 39703848 ps
CPU time 1.39 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 211256 kb
Host smart-e755cc50-7a90-4bdf-9767-2e0553c59df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611767693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3611767693
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1442168468
Short name T949
Test name
Test status
Simulation time 24710923 ps
CPU time 1.63 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 217276 kb
Host smart-332c1b6a-b3cb-426f-ae02-83c8f4351a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442168468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1442168468
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3248810096
Short name T186
Test name
Test status
Simulation time 33250080 ps
CPU time 1.28 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:34 PM PDT 24
Peak memory 209192 kb
Host smart-691e515c-2849-4a9f-840d-72ba7529464f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248810096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3248810096
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1630628261
Short name T975
Test name
Test status
Simulation time 29145010 ps
CPU time 1.93 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 209080 kb
Host smart-229f9919-ac7c-4fb7-9e59-b1f5080b32d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630628261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1630628261
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3667550718
Short name T987
Test name
Test status
Simulation time 21851798 ps
CPU time 0.87 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:38 PM PDT 24
Peak memory 209440 kb
Host smart-554bf699-7d3a-4a2f-8b41-5dcb9fcc7ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667550718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3667550718
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1181394002
Short name T947
Test name
Test status
Simulation time 40256881 ps
CPU time 0.95 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 217268 kb
Host smart-90671d4d-f8a5-40e9-898b-d320ac776a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181394002 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1181394002
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3094225120
Short name T188
Test name
Test status
Simulation time 42972761 ps
CPU time 0.84 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 208960 kb
Host smart-2af7ebc5-fcb7-4edd-8879-0a8499d21a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094225120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3094225120
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.743498042
Short name T870
Test name
Test status
Simulation time 150996806 ps
CPU time 1.01 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 208956 kb
Host smart-4510db34-be5b-45f3-b4a0-89a839eb83a2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743498042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.743498042
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3750128175
Short name T979
Test name
Test status
Simulation time 371989567 ps
CPU time 9.29 seconds
Started Jun 28 07:48:44 PM PDT 24
Finished Jun 28 07:48:59 PM PDT 24
Peak memory 208804 kb
Host smart-95705ea9-54be-4016-b6e5-b9850e97eaa4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750128175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3750128175
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1969301061
Short name T871
Test name
Test status
Simulation time 6319603050 ps
CPU time 20.22 seconds
Started Jun 28 07:48:48 PM PDT 24
Finished Jun 28 07:49:17 PM PDT 24
Peak memory 209076 kb
Host smart-cafcba22-6b79-4724-ae21-52711ebe469b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969301061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1969301061
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4009341173
Short name T884
Test name
Test status
Simulation time 387820923 ps
CPU time 1.21 seconds
Started Jun 28 07:48:55 PM PDT 24
Finished Jun 28 07:49:02 PM PDT 24
Peak memory 210388 kb
Host smart-01a5e23e-4556-4745-a161-8b5e16c81754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009341173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4009341173
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1973026575
Short name T958
Test name
Test status
Simulation time 298790256 ps
CPU time 2.31 seconds
Started Jun 28 07:48:55 PM PDT 24
Finished Jun 28 07:49:03 PM PDT 24
Peak memory 208968 kb
Host smart-a3c5373e-f0f7-411d-855f-848565c23a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973026575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1973026575
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2433361055
Short name T199
Test name
Test status
Simulation time 282076744 ps
CPU time 1.84 seconds
Started Jun 28 07:48:46 PM PDT 24
Finished Jun 28 07:48:56 PM PDT 24
Peak memory 211136 kb
Host smart-b9a9a599-529c-47a9-9edb-16129f000ad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433361055 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2433361055
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.75561746
Short name T961
Test name
Test status
Simulation time 138436942 ps
CPU time 1.71 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:35 PM PDT 24
Peak memory 211188 kb
Host smart-670c74dd-5838-4d53-80b6-0ac37233c015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75561746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_s
ame_csr_outstanding.75561746
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3824605660
Short name T120
Test name
Test status
Simulation time 213984186 ps
CPU time 3.07 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 217740 kb
Host smart-52af1848-1935-4bd3-8c93-ce9f5aff76df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824605660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3824605660
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2669332853
Short name T144
Test name
Test status
Simulation time 56244752 ps
CPU time 1.97 seconds
Started Jun 28 07:49:35 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 221968 kb
Host smart-16688edc-7c2f-40e5-af3a-e2df7cbe0594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669332853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2669332853
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3134531240
Short name T194
Test name
Test status
Simulation time 40638094 ps
CPU time 1.32 seconds
Started Jun 28 07:49:28 PM PDT 24
Finished Jun 28 07:49:31 PM PDT 24
Peak memory 209260 kb
Host smart-03a9f84b-dc84-48d6-bba4-fc0ecf1d8f97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134531240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3134531240
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3345425532
Short name T919
Test name
Test status
Simulation time 227628541 ps
CPU time 1.66 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:40 PM PDT 24
Peak memory 209060 kb
Host smart-f949ccca-bc3c-4574-81c6-0d579da39994
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345425532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3345425532
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3859016873
Short name T905
Test name
Test status
Simulation time 189113859 ps
CPU time 1.23 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:38 PM PDT 24
Peak memory 218040 kb
Host smart-45d60e5e-e6a1-43a4-8533-48f992878a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859016873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3859016873
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2934856003
Short name T967
Test name
Test status
Simulation time 147897411 ps
CPU time 1.49 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 217564 kb
Host smart-9bcda636-a959-4f90-928b-1ca33acc3857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934856003 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2934856003
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.761943138
Short name T185
Test name
Test status
Simulation time 165270113 ps
CPU time 0.87 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:34 PM PDT 24
Peak memory 209088 kb
Host smart-4f76d874-67c5-4773-89ff-93f2d69a6852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761943138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.761943138
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2382058211
Short name T900
Test name
Test status
Simulation time 35895468 ps
CPU time 1.46 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:32 PM PDT 24
Peak memory 208536 kb
Host smart-9a357244-ef43-4555-b9f2-e587e8fd47ac
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382058211 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2382058211
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.704712346
Short name T895
Test name
Test status
Simulation time 1295007927 ps
CPU time 13.79 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:54 PM PDT 24
Peak memory 216944 kb
Host smart-5c79418e-53dc-4c23-9e41-e5945aa88560
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704712346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.704712346
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2214707703
Short name T877
Test name
Test status
Simulation time 1386469986 ps
CPU time 13.86 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:53 PM PDT 24
Peak memory 208776 kb
Host smart-331fb2a7-4759-49b5-a8e6-143be05c04ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214707703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2214707703
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3828100638
Short name T127
Test name
Test status
Simulation time 188446373 ps
CPU time 1.26 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:38 PM PDT 24
Peak memory 210572 kb
Host smart-dfc8ad30-b941-4df3-aa17-a2c05c451374
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828100638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3828100638
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.448933219
Short name T972
Test name
Test status
Simulation time 224363433 ps
CPU time 2.1 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 217332 kb
Host smart-c678a88a-c87a-41ee-b8e1-7b8337b8ba19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448933
219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.448933219
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2967430403
Short name T901
Test name
Test status
Simulation time 129909004 ps
CPU time 1.78 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 217080 kb
Host smart-d129435f-c36f-41cd-a89e-3fe2a5610e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967430403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2967430403
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2084981912
Short name T939
Test name
Test status
Simulation time 37445633 ps
CPU time 1.49 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 211084 kb
Host smart-66e54332-6111-4c8b-9d82-f10333db40ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084981912 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2084981912
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1612707330
Short name T200
Test name
Test status
Simulation time 64058205 ps
CPU time 1.06 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:35 PM PDT 24
Peak memory 209096 kb
Host smart-0fe3577b-cabc-4885-96cf-41aeb474c9cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612707330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1612707330
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1633911845
Short name T909
Test name
Test status
Simulation time 93029989 ps
CPU time 3.73 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 217272 kb
Host smart-9d036ccc-97cb-45b7-a6ab-e49ff1ea0ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633911845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1633911845
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.634167936
Short name T138
Test name
Test status
Simulation time 160505868 ps
CPU time 2.73 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:40 PM PDT 24
Peak memory 222188 kb
Host smart-fdac6181-354f-4d7a-8ed0-7ee10926582b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634167936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.634167936
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.551259693
Short name T950
Test name
Test status
Simulation time 55923299 ps
CPU time 0.96 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 209208 kb
Host smart-c1ef303e-ecea-4dc8-9e08-7901c19d6edc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551259693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.551259693
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2563455922
Short name T974
Test name
Test status
Simulation time 109369376 ps
CPU time 1.5 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 209088 kb
Host smart-7f9e5fe7-1de2-47cb-b7be-b089509ee747
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563455922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2563455922
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2134171479
Short name T128
Test name
Test status
Simulation time 24985796 ps
CPU time 1 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:34 PM PDT 24
Peak memory 210244 kb
Host smart-d766cb00-7839-470e-b905-2295ac479490
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134171479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2134171479
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3447649850
Short name T932
Test name
Test status
Simulation time 32905954 ps
CPU time 1.46 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:32 PM PDT 24
Peak memory 218388 kb
Host smart-e88254d6-db9a-4318-9db0-1accb42b0fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447649850 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3447649850
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2647021705
Short name T907
Test name
Test status
Simulation time 46150570 ps
CPU time 0.87 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 208992 kb
Host smart-a851f65b-588f-490a-89a5-212b3c55eb07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647021705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2647021705
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.875651074
Short name T973
Test name
Test status
Simulation time 70728496 ps
CPU time 2.09 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 208960 kb
Host smart-f8ce0111-13d3-4456-8b7e-287b0251daef
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875651074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.875651074
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3158911814
Short name T897
Test name
Test status
Simulation time 2245505692 ps
CPU time 12.95 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:50 PM PDT 24
Peak memory 208852 kb
Host smart-673ef83a-0366-45e8-abf5-48b0c12f7fb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158911814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3158911814
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2439774414
Short name T938
Test name
Test status
Simulation time 3024121306 ps
CPU time 18.95 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:54 PM PDT 24
Peak memory 209068 kb
Host smart-207d4596-4455-4db9-af07-ee368bd296e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439774414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2439774414
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.403997718
Short name T903
Test name
Test status
Simulation time 240054467 ps
CPU time 1.31 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 210436 kb
Host smart-3847382c-e4ca-4b59-9660-46cbc32cc32c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403997718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.403997718
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4163618815
Short name T892
Test name
Test status
Simulation time 175813113 ps
CPU time 1.69 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 218800 kb
Host smart-118a00d9-2d4f-4811-87f4-09cbe7b9f35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416361
8815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4163618815
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.674774337
Short name T912
Test name
Test status
Simulation time 130711287 ps
CPU time 2.05 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 217116 kb
Host smart-6e33ae68-869d-4fc6-9478-d7cae37e01d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674774337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.674774337
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2776122570
Short name T899
Test name
Test status
Simulation time 14680544 ps
CPU time 1.16 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 217284 kb
Host smart-072719a5-8671-4605-b4cf-334bc82abea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776122570 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2776122570
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1782171931
Short name T977
Test name
Test status
Simulation time 68500603 ps
CPU time 1.38 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:35 PM PDT 24
Peak memory 211220 kb
Host smart-6f7e0114-7b64-44ed-abb1-c960ed8ec952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782171931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1782171931
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2711728093
Short name T913
Test name
Test status
Simulation time 154787179 ps
CPU time 5.59 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 217260 kb
Host smart-d61c9d4a-f8aa-48dd-9434-123a7df9ddf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711728093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2711728093
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.937396640
Short name T879
Test name
Test status
Simulation time 86527027 ps
CPU time 1.49 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 219676 kb
Host smart-e953c612-811c-4e2c-841a-2c0370dfc537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937396640 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.937396640
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2700303527
Short name T195
Test name
Test status
Simulation time 22624432 ps
CPU time 1.11 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 209060 kb
Host smart-d1c0a38b-5da8-4b3a-8829-640a705a8b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700303527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2700303527
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2321128192
Short name T880
Test name
Test status
Simulation time 121886679 ps
CPU time 1.31 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 208936 kb
Host smart-c1382a7b-9723-4e05-a955-99c9113e133c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321128192 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2321128192
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2406839023
Short name T149
Test name
Test status
Simulation time 813892793 ps
CPU time 10.07 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:45 PM PDT 24
Peak memory 208792 kb
Host smart-82740521-5a20-4148-917d-783c7ad5b972
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406839023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2406839023
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4183552433
Short name T942
Test name
Test status
Simulation time 1100267472 ps
CPU time 26.7 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:59 PM PDT 24
Peak memory 209012 kb
Host smart-7ba80e75-acfd-40e3-b800-954f23b4da44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183552433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4183552433
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4288406218
Short name T966
Test name
Test status
Simulation time 328867383 ps
CPU time 1.7 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 210468 kb
Host smart-047d70f6-b011-4433-9da1-ba18bb92c743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288406218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4288406218
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1619680640
Short name T926
Test name
Test status
Simulation time 49976686 ps
CPU time 2.43 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:36 PM PDT 24
Peak memory 218404 kb
Host smart-18152e33-7480-44ef-afee-1f6b5b9556e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161968
0640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1619680640
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1398949535
Short name T962
Test name
Test status
Simulation time 177708224 ps
CPU time 2.77 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:38 PM PDT 24
Peak memory 209064 kb
Host smart-f06e3f7a-e116-44be-945c-733bd65e4eff
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398949535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1398949535
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3256076581
Short name T928
Test name
Test status
Simulation time 42320222 ps
CPU time 1.44 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:49:35 PM PDT 24
Peak memory 217284 kb
Host smart-8829fde6-807b-41fe-a94b-997f9220164d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256076581 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3256076581
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1298371111
Short name T930
Test name
Test status
Simulation time 74660070 ps
CPU time 1.19 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 211024 kb
Host smart-47804e71-040d-40f1-a56a-9fa3ab02c8b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298371111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1298371111
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1843473528
Short name T957
Test name
Test status
Simulation time 123012234 ps
CPU time 4.86 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 217276 kb
Host smart-5086085f-e42c-4eb7-ab87-71c9b94f5c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843473528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1843473528
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2197337678
Short name T142
Test name
Test status
Simulation time 129764380 ps
CPU time 2.62 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 217300 kb
Host smart-ca270d96-992e-44ac-abe3-09c0560239fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197337678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2197337678
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.120475789
Short name T980
Test name
Test status
Simulation time 20244303 ps
CPU time 1.7 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:40 PM PDT 24
Peak memory 222828 kb
Host smart-3b1844c7-62b5-4524-8776-3c674a08766f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120475789 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.120475789
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3411602493
Short name T983
Test name
Test status
Simulation time 13644182 ps
CPU time 0.94 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 209120 kb
Host smart-78f9cf41-5937-4815-a1e9-3953bfcc97e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411602493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3411602493
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.348756610
Short name T955
Test name
Test status
Simulation time 71838412 ps
CPU time 1.53 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 208976 kb
Host smart-79b3369b-5291-418b-8720-73382f0df074
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348756610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.348756610
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.111986402
Short name T976
Test name
Test status
Simulation time 228693335 ps
CPU time 5.84 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:48 PM PDT 24
Peak memory 208684 kb
Host smart-f44bba41-d55d-48b8-abf0-dd0adb76743a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111986402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.111986402
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1301164948
Short name T911
Test name
Test status
Simulation time 25885904515 ps
CPU time 29.52 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:50:09 PM PDT 24
Peak memory 209128 kb
Host smart-b74e4f32-e3e3-4959-881d-33a29a3fbb7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301164948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1301164948
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1530265879
Short name T872
Test name
Test status
Simulation time 124606072 ps
CPU time 1.27 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:40 PM PDT 24
Peak memory 210452 kb
Host smart-972c2fe6-6c4f-4e19-a204-473656d61805
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530265879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1530265879
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2004576654
Short name T965
Test name
Test status
Simulation time 1598777324 ps
CPU time 4.9 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 217936 kb
Host smart-f762e62f-e3fc-4aa4-ae68-a8e8101ae4e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200457
6654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2004576654
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3779613989
Short name T969
Test name
Test status
Simulation time 288146992 ps
CPU time 1.56 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 216956 kb
Host smart-e2b2ccb1-912a-47d9-8358-9f070505d656
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779613989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3779613989
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3702630433
Short name T908
Test name
Test status
Simulation time 20934081 ps
CPU time 1.38 seconds
Started Jun 28 07:49:29 PM PDT 24
Finished Jun 28 07:49:34 PM PDT 24
Peak memory 217460 kb
Host smart-cdf1cf98-cde3-4764-85c8-a6cae41fb504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702630433 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3702630433
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4243980497
Short name T995
Test name
Test status
Simulation time 38292191 ps
CPU time 1.21 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:39 PM PDT 24
Peak memory 211168 kb
Host smart-dd55c6bf-9a3f-4799-bae9-ff782334c859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243980497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4243980497
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3604634786
Short name T956
Test name
Test status
Simulation time 39065578 ps
CPU time 1.78 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 217328 kb
Host smart-026e608d-a47a-4cec-ae93-e52ff573e9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604634786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3604634786
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1790462832
Short name T873
Test name
Test status
Simulation time 32665658 ps
CPU time 1.41 seconds
Started Jun 28 07:49:35 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 218568 kb
Host smart-02944dca-ff6c-4578-88f0-7f1004c34523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790462832 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1790462832
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1222851655
Short name T193
Test name
Test status
Simulation time 45102592 ps
CPU time 0.8 seconds
Started Jun 28 07:49:35 PM PDT 24
Finished Jun 28 07:49:42 PM PDT 24
Peak memory 209020 kb
Host smart-79c5bf1c-8599-4e4a-b53f-9d99efc0a69c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222851655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1222851655
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1775409231
Short name T883
Test name
Test status
Simulation time 57440126 ps
CPU time 1.16 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 208944 kb
Host smart-6bf8c5b9-1736-4b5f-adee-9494ca122f27
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775409231 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1775409231
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.194899133
Short name T959
Test name
Test status
Simulation time 407703618 ps
CPU time 4.3 seconds
Started Jun 28 07:49:32 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 209060 kb
Host smart-afc3a677-95c7-42e7-9081-2c4e539411ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194899133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.194899133
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.370329326
Short name T988
Test name
Test status
Simulation time 5237430847 ps
CPU time 26.93 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:50:09 PM PDT 24
Peak memory 209080 kb
Host smart-75b4af66-7dbe-4909-bd66-dc01feaee39d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370329326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.370329326
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2281392074
Short name T989
Test name
Test status
Simulation time 215926724 ps
CPU time 2.77 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 210576 kb
Host smart-c314acc6-1c63-4916-b766-322361fd5c25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281392074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2281392074
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2263810724
Short name T937
Test name
Test status
Simulation time 122460136 ps
CPU time 2.31 seconds
Started Jun 28 07:49:31 PM PDT 24
Finished Jun 28 07:49:37 PM PDT 24
Peak memory 218712 kb
Host smart-16cafa74-b57a-4df2-a7c1-d78a39e302cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226381
0724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2263810724
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3928344137
Short name T998
Test name
Test status
Simulation time 1170574225 ps
CPU time 1.73 seconds
Started Jun 28 07:49:35 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 208892 kb
Host smart-b4c23954-7091-4d61-a255-750f77ec285e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928344137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3928344137
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.243054422
Short name T198
Test name
Test status
Simulation time 69152332 ps
CPU time 1.21 seconds
Started Jun 28 07:49:33 PM PDT 24
Finished Jun 28 07:49:41 PM PDT 24
Peak memory 217280 kb
Host smart-6e863d28-3582-4aee-8fc1-b49f5c83212c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243054422 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.243054422
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1598142619
Short name T960
Test name
Test status
Simulation time 56407020 ps
CPU time 1.42 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:44 PM PDT 24
Peak memory 208992 kb
Host smart-7105a87e-b895-4193-ac37-c0142e889b3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598142619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1598142619
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3213374507
Short name T984
Test name
Test status
Simulation time 66943734 ps
CPU time 2.1 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 217300 kb
Host smart-ba81d050-b873-4772-a826-8e284203e2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213374507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3213374507
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4211440733
Short name T146
Test name
Test status
Simulation time 85370364 ps
CPU time 2.68 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:49:43 PM PDT 24
Peak memory 222088 kb
Host smart-900a8ff7-770f-43ab-8987-7bf3978ebf07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211440733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4211440733
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1077630616
Short name T906
Test name
Test status
Simulation time 54813262 ps
CPU time 1.63 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 218396 kb
Host smart-89fefbc2-7426-4b74-997f-2dfdfa891c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077630616 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1077630616
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2054569109
Short name T191
Test name
Test status
Simulation time 15784843 ps
CPU time 1.09 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:38 PM PDT 24
Peak memory 209124 kb
Host smart-40a3a765-106a-4fd1-b378-3643e69a635a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054569109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2054569109
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.237769060
Short name T898
Test name
Test status
Simulation time 31599279 ps
CPU time 0.98 seconds
Started Jun 28 07:50:18 PM PDT 24
Finished Jun 28 07:50:22 PM PDT 24
Peak memory 208936 kb
Host smart-7c439c64-2471-43d7-916c-5331bab48cf2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237769060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.237769060
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1361393913
Short name T933
Test name
Test status
Simulation time 1746643485 ps
CPU time 19.14 seconds
Started Jun 28 07:49:34 PM PDT 24
Finished Jun 28 07:50:00 PM PDT 24
Peak memory 216800 kb
Host smart-6ad6be65-0193-42ee-ba46-e186ecab1247
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361393913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1361393913
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4158577886
Short name T910
Test name
Test status
Simulation time 3856949300 ps
CPU time 44.36 seconds
Started Jun 28 07:49:30 PM PDT 24
Finished Jun 28 07:50:18 PM PDT 24
Peak memory 209072 kb
Host smart-7749b8fe-1257-4d80-8346-7d3f62ef7578
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158577886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4158577886
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3087727756
Short name T954
Test name
Test status
Simulation time 82734169 ps
CPU time 2.72 seconds
Started Jun 28 07:49:36 PM PDT 24
Finished Jun 28 07:49:45 PM PDT 24
Peak memory 210792 kb
Host smart-cf453ead-cd71-4a31-9774-ffdbb3d4c7de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087727756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3087727756
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1434800470
Short name T150
Test name
Test status
Simulation time 552122879 ps
CPU time 3.75 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:41 PM PDT 24
Peak memory 218408 kb
Host smart-21d1dde7-89fc-4be4-894f-cecb14544c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143480
0470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1434800470
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.455087647
Short name T948
Test name
Test status
Simulation time 58839581 ps
CPU time 2.12 seconds
Started Jun 28 07:49:35 PM PDT 24
Finished Jun 28 07:49:45 PM PDT 24
Peak memory 217212 kb
Host smart-a95c4549-2932-49fe-9f76-6bcb3b215e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455087647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.455087647
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.979421774
Short name T999
Test name
Test status
Simulation time 79435144 ps
CPU time 1 seconds
Started Jun 28 07:50:15 PM PDT 24
Finished Jun 28 07:50:16 PM PDT 24
Peak memory 209132 kb
Host smart-59f1f3b5-c035-4326-b02b-b83a84d4b1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979421774 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.979421774
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.214889793
Short name T985
Test name
Test status
Simulation time 83800782 ps
CPU time 1.44 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:41 PM PDT 24
Peak memory 211096 kb
Host smart-cf5d5021-b956-41c4-a238-6bf10c9a2f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214889793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.214889793
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2309592294
Short name T881
Test name
Test status
Simulation time 32048927 ps
CPU time 1.01 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 218524 kb
Host smart-1cfe20d0-b744-45d3-a1f8-ac4acd6a4861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309592294 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2309592294
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3535728690
Short name T132
Test name
Test status
Simulation time 11711366 ps
CPU time 0.99 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:45 PM PDT 24
Peak memory 209124 kb
Host smart-73dbf48a-0ab1-4bb7-b52c-31b85977918e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535728690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3535728690
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1283509058
Short name T889
Test name
Test status
Simulation time 91870309 ps
CPU time 1.1 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:27 PM PDT 24
Peak memory 208460 kb
Host smart-8393d564-ee55-48d9-9bf6-8e93a1c9ff5d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283509058 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1283509058
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.839737085
Short name T886
Test name
Test status
Simulation time 2055219560 ps
CPU time 11.43 seconds
Started Jun 28 07:50:24 PM PDT 24
Finished Jun 28 07:50:55 PM PDT 24
Peak memory 209060 kb
Host smart-05ab28a6-35d0-4057-9914-6983f2739eed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839737085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.839737085
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1733725244
Short name T993
Test name
Test status
Simulation time 5531401240 ps
CPU time 12.8 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:50 PM PDT 24
Peak memory 217104 kb
Host smart-1241da78-4a54-4d42-822e-f01e420b84fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733725244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1733725244
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1793134313
Short name T990
Test name
Test status
Simulation time 49099376 ps
CPU time 1.86 seconds
Started Jun 28 07:50:21 PM PDT 24
Finished Jun 28 07:50:39 PM PDT 24
Peak memory 210576 kb
Host smart-e049fa00-a9f1-4613-974f-391283d6585f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793134313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1793134313
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3398023741
Short name T944
Test name
Test status
Simulation time 160778251 ps
CPU time 1.73 seconds
Started Jun 28 07:50:18 PM PDT 24
Finished Jun 28 07:50:26 PM PDT 24
Peak memory 218572 kb
Host smart-bc44ff29-88e3-4d98-b89e-90d054b06104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339802
3741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3398023741
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1392307817
Short name T876
Test name
Test status
Simulation time 112913699 ps
CPU time 1.56 seconds
Started Jun 28 07:50:19 PM PDT 24
Finished Jun 28 07:50:31 PM PDT 24
Peak memory 209064 kb
Host smart-73c76290-d981-4f93-b7f8-4eff97a06347
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392307817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1392307817
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4021059529
Short name T940
Test name
Test status
Simulation time 51385003 ps
CPU time 1.1 seconds
Started Jun 28 07:50:18 PM PDT 24
Finished Jun 28 07:50:23 PM PDT 24
Peak memory 209132 kb
Host smart-99628de9-7ede-4d81-9a96-118b5a14d8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021059529 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4021059529
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3615223176
Short name T915
Test name
Test status
Simulation time 134004036 ps
CPU time 1.76 seconds
Started Jun 28 07:50:22 PM PDT 24
Finished Jun 28 07:50:40 PM PDT 24
Peak memory 217352 kb
Host smart-c496f9a6-3bb9-4ad0-a90f-37c39fa7c96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615223176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3615223176
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1924390763
Short name T1000
Test name
Test status
Simulation time 31306016 ps
CPU time 1.84 seconds
Started Jun 28 07:50:20 PM PDT 24
Finished Jun 28 07:50:36 PM PDT 24
Peak memory 217272 kb
Host smart-9bb6869f-c575-438e-907c-08db4cd5399e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924390763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1924390763
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1995644511
Short name T134
Test name
Test status
Simulation time 72579345 ps
CPU time 2.6 seconds
Started Jun 28 07:50:16 PM PDT 24
Finished Jun 28 07:50:20 PM PDT 24
Peak memory 222016 kb
Host smart-e569a186-3f31-43f0-afb3-8d7ac3e2efaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995644511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1995644511
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2183531466
Short name T499
Test name
Test status
Simulation time 20719893 ps
CPU time 1.16 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:39:52 PM PDT 24
Peak memory 209568 kb
Host smart-c256ace3-3430-4c63-9ce7-f10d32168376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183531466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2183531466
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2957617695
Short name T864
Test name
Test status
Simulation time 379717714 ps
CPU time 15.07 seconds
Started Jun 28 07:39:33 PM PDT 24
Finished Jun 28 07:39:55 PM PDT 24
Peak memory 226460 kb
Host smart-6cc118ed-1e4e-4120-8472-8e1e466f00fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957617695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2957617695
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2921481967
Short name T768
Test name
Test status
Simulation time 131176035 ps
CPU time 4.28 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:49 PM PDT 24
Peak memory 217600 kb
Host smart-f1515c35-3f43-4791-96b9-fcefc513823c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921481967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2921481967
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1867637250
Short name T19
Test name
Test status
Simulation time 1903299938 ps
CPU time 31.89 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:40:14 PM PDT 24
Peak memory 219224 kb
Host smart-d4fb037d-6464-483c-b2ba-1fcdee68309d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867637250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1867637250
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1013423539
Short name T839
Test name
Test status
Simulation time 6266955944 ps
CPU time 28.2 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:40:12 PM PDT 24
Peak memory 218156 kb
Host smart-24dedbcf-900e-4bec-8491-ee06308e885a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013423539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
013423539
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2094614263
Short name T304
Test name
Test status
Simulation time 999407010 ps
CPU time 6.24 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:54 PM PDT 24
Peak memory 218652 kb
Host smart-f3b9f85a-e3e0-4c14-a3ac-a3ceea369393
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094614263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2094614263
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.978160129
Short name T440
Test name
Test status
Simulation time 956710808 ps
CPU time 14.52 seconds
Started Jun 28 07:39:38 PM PDT 24
Finished Jun 28 07:40:04 PM PDT 24
Peak memory 217992 kb
Host smart-23abafeb-ada3-4108-9dce-39fd98618ad9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978160129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.978160129
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.21869478
Short name T78
Test name
Test status
Simulation time 236932306 ps
CPU time 3.17 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:48 PM PDT 24
Peak memory 217992 kb
Host smart-94c447c8-f4bd-4610-9dde-4141728fe977
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21869478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.21869478
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3320454108
Short name T694
Test name
Test status
Simulation time 1677832788 ps
CPU time 62.39 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 269696 kb
Host smart-add6e103-2aa2-4c07-aab8-5d82d8fc3517
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320454108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3320454108
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2754425407
Short name T395
Test name
Test status
Simulation time 2050598193 ps
CPU time 20.77 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 250764 kb
Host smart-3c05096f-379f-4373-a7d2-db3b774a4c4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754425407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2754425407
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2444291446
Short name T615
Test name
Test status
Simulation time 98292427 ps
CPU time 2.98 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:48 PM PDT 24
Peak memory 222628 kb
Host smart-2406e2ee-21ba-43d3-b2fe-68644f4ef616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444291446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2444291446
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1394674773
Short name T692
Test name
Test status
Simulation time 243978106 ps
CPU time 16.42 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:59 PM PDT 24
Peak memory 214984 kb
Host smart-36463cf4-801a-49a1-b5c5-0ccdbfe37dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394674773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1394674773
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4215023254
Short name T115
Test name
Test status
Simulation time 110026134 ps
CPU time 22.78 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:40:16 PM PDT 24
Peak memory 269032 kb
Host smart-b34674d9-b9b3-49a6-8906-299057061312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215023254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4215023254
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3165403574
Short name T589
Test name
Test status
Simulation time 1014659249 ps
CPU time 10.73 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 219280 kb
Host smart-38436eec-99ba-4f93-b556-0ca3e2db0e47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165403574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3165403574
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2280078843
Short name T293
Test name
Test status
Simulation time 4019132962 ps
CPU time 12 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 219296 kb
Host smart-108ec25d-2477-4339-809c-6d6c73443781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280078843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2280078843
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2194027710
Short name T408
Test name
Test status
Simulation time 2287124543 ps
CPU time 7.17 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:54 PM PDT 24
Peak memory 225544 kb
Host smart-e9860637-d0da-4be4-b567-0fb9825add43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194027710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
194027710
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3153927018
Short name T404
Test name
Test status
Simulation time 1717699758 ps
CPU time 10.86 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:53 PM PDT 24
Peak memory 226416 kb
Host smart-bf3ffb74-dc65-4665-9d2a-887015b0f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153927018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3153927018
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2201461254
Short name T662
Test name
Test status
Simulation time 176565191 ps
CPU time 2.61 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:39:51 PM PDT 24
Peak memory 214936 kb
Host smart-2bbc4149-5f6f-48b3-bf6b-eac09d8ebc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201461254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2201461254
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2005366992
Short name T429
Test name
Test status
Simulation time 1942967890 ps
CPU time 28.85 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:40:10 PM PDT 24
Peak memory 246568 kb
Host smart-e70cd177-87dc-4e7c-9f2a-50c2d6cfa749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005366992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2005366992
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.736944243
Short name T272
Test name
Test status
Simulation time 447805616 ps
CPU time 7.6 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:53 PM PDT 24
Peak memory 251224 kb
Host smart-9686fad1-6539-4202-8845-9287b8e63114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736944243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.736944243
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4292330570
Short name T540
Test name
Test status
Simulation time 25618940243 ps
CPU time 83.52 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:41:16 PM PDT 24
Peak memory 251392 kb
Host smart-a0e18d9d-8669-4b15-b840-1a54b6b8049b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292330570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4292330570
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4039165753
Short name T531
Test name
Test status
Simulation time 13364100 ps
CPU time 1.1 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:39:50 PM PDT 24
Peak memory 212208 kb
Host smart-5f066471-7eb8-4dc7-bf2f-2d3ec5a9b6a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039165753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4039165753
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1294420752
Short name T851
Test name
Test status
Simulation time 51531772 ps
CPU time 0.92 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:39:52 PM PDT 24
Peak memory 209388 kb
Host smart-c2ae58c8-dd95-42cf-9c8f-f3af163a6750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294420752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1294420752
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3617052563
Short name T505
Test name
Test status
Simulation time 4607731718 ps
CPU time 16.84 seconds
Started Jun 28 07:39:41 PM PDT 24
Finished Jun 28 07:40:10 PM PDT 24
Peak memory 226520 kb
Host smart-bdbf9e80-2c94-4972-b8bb-fc55e041364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617052563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3617052563
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2012726851
Short name T616
Test name
Test status
Simulation time 13277060480 ps
CPU time 18.98 seconds
Started Jun 28 07:39:44 PM PDT 24
Finished Jun 28 07:40:14 PM PDT 24
Peak memory 218128 kb
Host smart-c09c85bd-0f34-4c1b-83d4-83566ec63217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012726851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2012726851
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1672400345
Short name T803
Test name
Test status
Simulation time 11586258748 ps
CPU time 28.62 seconds
Started Jun 28 07:39:44 PM PDT 24
Finished Jun 28 07:40:24 PM PDT 24
Peak memory 218504 kb
Host smart-e60acbce-4d6d-47e3-b982-147de68d5222
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672400345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1672400345
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4061054526
Short name T6
Test name
Test status
Simulation time 478187151 ps
CPU time 10.44 seconds
Started Jun 28 07:39:44 PM PDT 24
Finished Jun 28 07:40:05 PM PDT 24
Peak memory 218088 kb
Host smart-3da08f52-35eb-4867-8757-a7b76fe9345e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061054526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
061054526
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.124062215
Short name T263
Test name
Test status
Simulation time 718637981 ps
CPU time 3.5 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 218584 kb
Host smart-4681bfec-f5ca-4114-b188-7c1a7696cfa3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124062215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.124062215
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.896265491
Short name T807
Test name
Test status
Simulation time 1909582677 ps
CPU time 11.55 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:56 PM PDT 24
Peak memory 217980 kb
Host smart-833ee61f-e520-4b31-ae17-c75e58341077
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896265491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.896265491
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1865556403
Short name T843
Test name
Test status
Simulation time 248057081 ps
CPU time 4.21 seconds
Started Jun 28 07:39:41 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 217912 kb
Host smart-27b2b9e0-7177-49c8-929d-dae6e977fbb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865556403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1865556403
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3300949808
Short name T278
Test name
Test status
Simulation time 6478606038 ps
CPU time 34.95 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:26 PM PDT 24
Peak memory 267672 kb
Host smart-7a11f614-12bb-469d-ab77-a8a0fdbdd889
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300949808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3300949808
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3891286860
Short name T799
Test name
Test status
Simulation time 868731266 ps
CPU time 11.5 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:40:04 PM PDT 24
Peak memory 251252 kb
Host smart-56e7f480-4269-497c-b693-d7fec4ebe771
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891286860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3891286860
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3657770935
Short name T374
Test name
Test status
Simulation time 67309062 ps
CPU time 3.67 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 218624 kb
Host smart-8cb3db3c-acdc-492f-a028-9f6e0404b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657770935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3657770935
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1849278426
Short name T371
Test name
Test status
Simulation time 237779219 ps
CPU time 6.5 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:40:00 PM PDT 24
Peak memory 214848 kb
Host smart-e097e8b3-5808-48bd-852b-a213e96ab459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849278426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1849278426
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3632462266
Short name T88
Test name
Test status
Simulation time 670338497 ps
CPU time 28.11 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:40:14 PM PDT 24
Peak memory 282336 kb
Host smart-1c6a191b-e39e-425e-b976-2679e9bf2d67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632462266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3632462266
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.243129006
Short name T280
Test name
Test status
Simulation time 1063280047 ps
CPU time 8.87 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:40:01 PM PDT 24
Peak memory 219248 kb
Host smart-87b17af5-419f-433d-8643-ddef339dc8d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243129006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.243129006
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2700232239
Short name T604
Test name
Test status
Simulation time 1753393052 ps
CPU time 12.58 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:04 PM PDT 24
Peak memory 218620 kb
Host smart-93223e8d-7086-4a96-9e02-76e982cec28e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700232239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2700232239
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3657231296
Short name T310
Test name
Test status
Simulation time 1487202766 ps
CPU time 9.66 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:01 PM PDT 24
Peak memory 226452 kb
Host smart-1b3b890c-afec-4c15-882c-8e29de820f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657231296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3657231296
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.192942343
Short name T257
Test name
Test status
Simulation time 488458740 ps
CPU time 2.88 seconds
Started Jun 28 07:39:38 PM PDT 24
Finished Jun 28 07:39:54 PM PDT 24
Peak memory 218068 kb
Host smart-4613c8a9-faf7-4924-ab56-d499d501d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192942343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.192942343
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.249944673
Short name T92
Test name
Test status
Simulation time 202099629 ps
CPU time 23.64 seconds
Started Jun 28 07:39:33 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 251296 kb
Host smart-22f5ef00-6fd8-4814-a33b-1839ca33d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249944673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.249944673
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3524564401
Short name T739
Test name
Test status
Simulation time 91361619 ps
CPU time 4.32 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:51 PM PDT 24
Peak memory 226756 kb
Host smart-deb78798-57e0-4bce-9cd7-bbbab71a58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524564401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3524564401
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1440404908
Short name T176
Test name
Test status
Simulation time 1197861943 ps
CPU time 38.95 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:40:31 PM PDT 24
Peak memory 251272 kb
Host smart-4ba1eb12-c4b8-4569-9a0c-f1ac6d249964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440404908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1440404908
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2634905581
Short name T182
Test name
Test status
Simulation time 201829899299 ps
CPU time 795.26 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:53:02 PM PDT 24
Peak memory 526232 kb
Host smart-3b81b35c-21b3-4547-96d6-24fd947a7c7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2634905581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2634905581
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2743377978
Short name T393
Test name
Test status
Simulation time 66170306 ps
CPU time 1.33 seconds
Started Jun 28 07:39:43 PM PDT 24
Finished Jun 28 07:39:56 PM PDT 24
Peak memory 218052 kb
Host smart-1551ce93-34a1-4ec2-8758-4bec4624b840
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743377978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2743377978
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.566187269
Short name T562
Test name
Test status
Simulation time 64272114 ps
CPU time 1.09 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:05 PM PDT 24
Peak memory 209484 kb
Host smart-fd7b5810-1903-460b-a5c2-db5deea207e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566187269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.566187269
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2273355189
Short name T750
Test name
Test status
Simulation time 539338685 ps
CPU time 10.59 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:15 PM PDT 24
Peak memory 218656 kb
Host smart-687e7434-9078-42dd-9cbb-5f43f2ecf1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273355189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2273355189
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.872922873
Short name T26
Test name
Test status
Simulation time 606658184 ps
CPU time 14.11 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:17 PM PDT 24
Peak memory 217496 kb
Host smart-9eb93ad5-3e2c-45c7-b255-c9936987b625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872922873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.872922873
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2517154602
Short name T245
Test name
Test status
Simulation time 2099344386 ps
CPU time 40.31 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:43 PM PDT 24
Peak memory 218588 kb
Host smart-6069245d-ca28-4146-be64-886628ee5628
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517154602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2517154602
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.653586907
Short name T373
Test name
Test status
Simulation time 358975866 ps
CPU time 6.13 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:10 PM PDT 24
Peak memory 218568 kb
Host smart-66cf1223-48e1-47f3-9609-5dff53fe7835
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653586907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.653586907
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1757918845
Short name T302
Test name
Test status
Simulation time 221681167 ps
CPU time 5.89 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:09 PM PDT 24
Peak memory 217984 kb
Host smart-47729ad0-90b5-4116-86b7-872f47a44025
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757918845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1757918845
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2741750860
Short name T470
Test name
Test status
Simulation time 5681795816 ps
CPU time 70.59 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:42:17 PM PDT 24
Peak memory 279316 kb
Host smart-28e71b4e-da64-45f3-8317-afe211ea8494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741750860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2741750860
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2054255882
Short name T162
Test name
Test status
Simulation time 1393407314 ps
CPU time 9.97 seconds
Started Jun 28 07:40:35 PM PDT 24
Finished Jun 28 07:41:09 PM PDT 24
Peak memory 246128 kb
Host smart-74b82670-6dff-4937-8384-ea5ebe68eab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054255882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2054255882
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2796263606
Short name T674
Test name
Test status
Simulation time 60695594 ps
CPU time 2.14 seconds
Started Jun 28 07:40:42 PM PDT 24
Finished Jun 28 07:41:08 PM PDT 24
Peak memory 218632 kb
Host smart-f03f6ca7-e585-4eda-81b3-90f90b75bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796263606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2796263606
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2234924633
Short name T556
Test name
Test status
Simulation time 1037477153 ps
CPU time 15.98 seconds
Started Jun 28 07:40:42 PM PDT 24
Finished Jun 28 07:41:22 PM PDT 24
Peak memory 220336 kb
Host smart-f97cef2c-671d-44c7-89e4-6c183f49fc3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234924633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2234924633
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1736776455
Short name T822
Test name
Test status
Simulation time 571264578 ps
CPU time 10.34 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:14 PM PDT 24
Peak memory 218600 kb
Host smart-6f33718e-8607-4172-8514-2954bd030ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736776455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1736776455
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3089622478
Short name T795
Test name
Test status
Simulation time 1002122020 ps
CPU time 9.59 seconds
Started Jun 28 07:40:40 PM PDT 24
Finished Jun 28 07:41:14 PM PDT 24
Peak memory 226388 kb
Host smart-46eddb5c-46a9-4ea7-a204-08ab66ac0237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089622478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3089622478
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.222084221
Short name T793
Test name
Test status
Simulation time 703695628 ps
CPU time 7.61 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:10 PM PDT 24
Peak memory 225460 kb
Host smart-d2b0b41a-03c3-4819-b618-b833e4d6c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222084221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.222084221
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3706324182
Short name T534
Test name
Test status
Simulation time 73468632 ps
CPU time 3.15 seconds
Started Jun 28 07:40:20 PM PDT 24
Finished Jun 28 07:40:50 PM PDT 24
Peak memory 215080 kb
Host smart-e66b29d1-e5f3-4ac4-bcfc-158bf51570ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706324182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3706324182
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.988390455
Short name T468
Test name
Test status
Simulation time 569321858 ps
CPU time 18.4 seconds
Started Jun 28 07:40:44 PM PDT 24
Finished Jun 28 07:41:28 PM PDT 24
Peak memory 250896 kb
Host smart-3953f193-7a35-40e2-9288-637ebb8085dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988390455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.988390455
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4071496476
Short name T111
Test name
Test status
Simulation time 328631587 ps
CPU time 9.31 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:15 PM PDT 24
Peak memory 251332 kb
Host smart-b8b7cb2f-5242-406d-9589-4405a55e612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071496476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4071496476
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1138247657
Short name T326
Test name
Test status
Simulation time 4762683198 ps
CPU time 145.56 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:43:30 PM PDT 24
Peak memory 284044 kb
Host smart-efc1c781-8709-4340-9dfe-6eeed2a070bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138247657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1138247657
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2326441265
Short name T44
Test name
Test status
Simulation time 35034065851 ps
CPU time 802.34 seconds
Started Jun 28 07:40:42 PM PDT 24
Finished Jun 28 07:54:29 PM PDT 24
Peak memory 414356 kb
Host smart-89b1b357-19ab-413c-8a30-4c168c03c710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2326441265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2326441265
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3277088429
Short name T471
Test name
Test status
Simulation time 28021780 ps
CPU time 0.77 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:40:44 PM PDT 24
Peak memory 209040 kb
Host smart-f9a43bab-d2ec-4bb3-a762-c5fd6fb95286
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277088429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3277088429
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2498317379
Short name T867
Test name
Test status
Simulation time 63319417 ps
CPU time 1.25 seconds
Started Jun 28 07:40:43 PM PDT 24
Finished Jun 28 07:41:10 PM PDT 24
Peak memory 209444 kb
Host smart-5f636d8b-7f3b-43ce-ac44-50d1a3202fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498317379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2498317379
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1569195834
Short name T542
Test name
Test status
Simulation time 306016896 ps
CPU time 10.47 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:15 PM PDT 24
Peak memory 226404 kb
Host smart-75d463c3-a1cf-4ac2-9c3b-456fc8f4e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569195834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1569195834
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1323061396
Short name T549
Test name
Test status
Simulation time 1858049026 ps
CPU time 10.99 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:14 PM PDT 24
Peak memory 217748 kb
Host smart-1b751ab5-6e0a-4613-bf7c-557520d862eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323061396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1323061396
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.846104015
Short name T837
Test name
Test status
Simulation time 27121811416 ps
CPU time 67.16 seconds
Started Jun 28 07:40:40 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 226436 kb
Host smart-e483eba9-d5d9-4053-a47b-22c092bacd2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846104015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.846104015
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2248588818
Short name T584
Test name
Test status
Simulation time 74529023 ps
CPU time 2.99 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:07 PM PDT 24
Peak memory 218568 kb
Host smart-29411350-3326-4b75-bf88-84689de57407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248588818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2248588818
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2645339955
Short name T736
Test name
Test status
Simulation time 4304305823 ps
CPU time 5.58 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:08 PM PDT 24
Peak memory 218048 kb
Host smart-3ec353f1-4bc8-43d3-bc54-ea5f2eaa6723
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645339955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2645339955
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1035856367
Short name T242
Test name
Test status
Simulation time 2218075369 ps
CPU time 52.37 seconds
Started Jun 28 07:40:37 PM PDT 24
Finished Jun 28 07:41:53 PM PDT 24
Peak memory 279664 kb
Host smart-890713eb-f2f4-466c-9790-fc5822b8c130
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035856367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1035856367
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1510417901
Short name T748
Test name
Test status
Simulation time 371844828 ps
CPU time 10.91 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:14 PM PDT 24
Peak memory 243072 kb
Host smart-e6860967-77c0-43f5-b664-924caba9d68a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510417901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1510417901
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4013710089
Short name T387
Test name
Test status
Simulation time 19163582 ps
CPU time 1.46 seconds
Started Jun 28 07:40:42 PM PDT 24
Finished Jun 28 07:41:07 PM PDT 24
Peak memory 218636 kb
Host smart-ae9bc0a9-f2ef-4d5a-a709-8b0c7f841044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013710089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4013710089
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3661875741
Short name T42
Test name
Test status
Simulation time 1308117257 ps
CPU time 12.34 seconds
Started Jun 28 07:40:42 PM PDT 24
Finished Jun 28 07:41:18 PM PDT 24
Peak memory 219288 kb
Host smart-61d6e3ab-b63b-4e45-9b24-4e431a9b4ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661875741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3661875741
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.696830587
Short name T230
Test name
Test status
Simulation time 342182850 ps
CPU time 8.82 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 218608 kb
Host smart-8b3c5bb9-dfb0-4ba1-b5f5-8347b6d45676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696830587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.696830587
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.165457989
Short name T231
Test name
Test status
Simulation time 1478354249 ps
CPU time 7.87 seconds
Started Jun 28 07:40:40 PM PDT 24
Finished Jun 28 07:41:12 PM PDT 24
Peak memory 218592 kb
Host smart-7acc193d-32d5-400e-9a7f-ffac50eb9477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165457989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.165457989
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.818670264
Short name T648
Test name
Test status
Simulation time 719231129 ps
CPU time 7.14 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 218552 kb
Host smart-492a73d3-638a-49bc-b81e-49fdb5cc7f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818670264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.818670264
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4147709136
Short name T577
Test name
Test status
Simulation time 87123853 ps
CPU time 2.93 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:41:06 PM PDT 24
Peak memory 218152 kb
Host smart-bd75ae20-c1d8-44fc-bb4b-a624c85c6243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147709136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4147709136
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.315486996
Short name T512
Test name
Test status
Simulation time 198062872 ps
CPU time 22.24 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:25 PM PDT 24
Peak memory 251328 kb
Host smart-5697899b-0b24-404c-9e68-bf7f52fa4c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315486996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.315486996
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3266890288
Short name T294
Test name
Test status
Simulation time 235916781 ps
CPU time 2.72 seconds
Started Jun 28 07:40:37 PM PDT 24
Finished Jun 28 07:41:03 PM PDT 24
Peak memory 226752 kb
Host smart-ef015b31-f534-466b-98f7-50b9c20aa1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266890288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3266890288
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4255419191
Short name T260
Test name
Test status
Simulation time 13876899164 ps
CPU time 91.41 seconds
Started Jun 28 07:40:37 PM PDT 24
Finished Jun 28 07:42:33 PM PDT 24
Peak memory 280080 kb
Host smart-ab8152aa-7276-499c-9af9-01df84d59cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255419191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4255419191
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3095413556
Short name T446
Test name
Test status
Simulation time 106589309 ps
CPU time 0.93 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:34 PM PDT 24
Peak memory 209308 kb
Host smart-254999cb-9dfc-47f5-a9db-640fdc0ca9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095413556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3095413556
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1103658533
Short name T357
Test name
Test status
Simulation time 1159304600 ps
CPU time 14.28 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:19 PM PDT 24
Peak memory 218524 kb
Host smart-13edd214-8bc6-49e4-8c4e-f96927c96087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103658533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1103658533
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2085580088
Short name T786
Test name
Test status
Simulation time 298605117 ps
CPU time 8.26 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:13 PM PDT 24
Peak memory 217584 kb
Host smart-4401cac0-ff93-4042-9a73-d4e1bb15ea4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085580088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2085580088
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3932388167
Short name T741
Test name
Test status
Simulation time 4170544414 ps
CPU time 26.83 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:31 PM PDT 24
Peak memory 219240 kb
Host smart-2753489a-0c15-4595-8bc0-c83395b062de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932388167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3932388167
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3568340471
Short name T493
Test name
Test status
Simulation time 390426620 ps
CPU time 11.93 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:16 PM PDT 24
Peak memory 223676 kb
Host smart-310c5b1c-60fb-4451-99e2-9674feac3a4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568340471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3568340471
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.4275008090
Short name T503
Test name
Test status
Simulation time 950022130 ps
CPU time 7.14 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:13 PM PDT 24
Peak memory 217992 kb
Host smart-3cfa5206-bd3b-4ad2-81d6-0be5e0b7a801
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275008090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.4275008090
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3479818016
Short name T673
Test name
Test status
Simulation time 6118706762 ps
CPU time 60.02 seconds
Started Jun 28 07:40:36 PM PDT 24
Finished Jun 28 07:42:00 PM PDT 24
Peak memory 276100 kb
Host smart-0cef95ca-0a8d-4c77-a16f-78ced07be932
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479818016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3479818016
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2147431472
Short name T445
Test name
Test status
Simulation time 3706769963 ps
CPU time 41.87 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:46 PM PDT 24
Peak memory 249376 kb
Host smart-d376b068-b838-4600-a92c-f33b21291101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147431472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2147431472
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1125130326
Short name T606
Test name
Test status
Simulation time 138867423 ps
CPU time 2.05 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:06 PM PDT 24
Peak memory 218620 kb
Host smart-79308c9e-e1a1-4bde-bb85-2f1f3408f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125130326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1125130326
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.404335057
Short name T229
Test name
Test status
Simulation time 333323444 ps
CPU time 12.58 seconds
Started Jun 28 07:40:41 PM PDT 24
Finished Jun 28 07:41:17 PM PDT 24
Peak memory 219236 kb
Host smart-431a307a-e898-4ce2-a264-0ac9c9a3fd74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404335057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.404335057
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.537220116
Short name T778
Test name
Test status
Simulation time 243585412 ps
CPU time 10.59 seconds
Started Jun 28 07:40:36 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 218544 kb
Host smart-d101e443-d588-48eb-bbf4-fba24b8c7383
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537220116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.537220116
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.366961834
Short name T315
Test name
Test status
Simulation time 266175127 ps
CPU time 7.12 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 218492 kb
Host smart-07ac6c26-0360-4a07-badd-23bb60a945f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366961834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.366961834
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3826997835
Short name T533
Test name
Test status
Simulation time 319448055 ps
CPU time 12.46 seconds
Started Jun 28 07:40:44 PM PDT 24
Finished Jun 28 07:41:22 PM PDT 24
Peak memory 218368 kb
Host smart-14b623c6-6f66-43a7-8563-6f9dc98617dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826997835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3826997835
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1030331494
Short name T751
Test name
Test status
Simulation time 268407188 ps
CPU time 2.47 seconds
Started Jun 28 07:40:44 PM PDT 24
Finished Jun 28 07:41:12 PM PDT 24
Peak memory 214892 kb
Host smart-9d5cd601-8d5f-4c31-80b1-4b2f7abf7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030331494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1030331494
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2464311394
Short name T285
Test name
Test status
Simulation time 1546412686 ps
CPU time 40.79 seconds
Started Jun 28 07:40:39 PM PDT 24
Finished Jun 28 07:41:45 PM PDT 24
Peak memory 251340 kb
Host smart-61db4c65-f694-4dda-9bbb-3bcdf8d2e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464311394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2464311394
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.4039352859
Short name T345
Test name
Test status
Simulation time 87270340 ps
CPU time 6.49 seconds
Started Jun 28 07:40:40 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 251232 kb
Host smart-3ec0c111-0d8f-4c97-b75f-bfb0e1fd483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039352859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.4039352859
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4226330738
Short name T60
Test name
Test status
Simulation time 15604515492 ps
CPU time 70.9 seconds
Started Jun 28 07:40:38 PM PDT 24
Finished Jun 28 07:42:14 PM PDT 24
Peak memory 277264 kb
Host smart-45486847-04c2-442b-a53f-6d1405e07c81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226330738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4226330738
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2705072440
Short name T91
Test name
Test status
Simulation time 26558157097 ps
CPU time 237.63 seconds
Started Jun 28 07:40:57 PM PDT 24
Finished Jun 28 07:45:22 PM PDT 24
Peak memory 488092 kb
Host smart-9cea7838-62ef-493e-80e5-877e00219d87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2705072440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2705072440
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2125164800
Short name T497
Test name
Test status
Simulation time 15348582 ps
CPU time 1 seconds
Started Jun 28 07:40:35 PM PDT 24
Finished Jun 28 07:41:02 PM PDT 24
Peak memory 209220 kb
Host smart-f9dbc37e-0af3-44db-83aa-e5177b961775
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125164800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2125164800
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1441935149
Short name T72
Test name
Test status
Simulation time 25427808 ps
CPU time 1.35 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:35 PM PDT 24
Peak memory 209392 kb
Host smart-c1b573be-46b6-4295-86c5-14b17fa354e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441935149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1441935149
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.4291258597
Short name T288
Test name
Test status
Simulation time 1364728925 ps
CPU time 15.11 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:56 PM PDT 24
Peak memory 218640 kb
Host smart-a1ad2ded-a6ec-47ca-a0b7-2808e4950ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291258597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.4291258597
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3402323867
Short name T596
Test name
Test status
Simulation time 462540146 ps
CPU time 11.64 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 217888 kb
Host smart-6c838847-a76c-4be7-8b4c-eca52b4e1058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402323867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3402323867
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2257905451
Short name T796
Test name
Test status
Simulation time 4391007551 ps
CPU time 57.22 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:42:28 PM PDT 24
Peak memory 219232 kb
Host smart-2fe08ab3-cb71-4140-a315-b806150febaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257905451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2257905451
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.82698316
Short name T292
Test name
Test status
Simulation time 3429660032 ps
CPU time 16.63 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:59 PM PDT 24
Peak memory 218544 kb
Host smart-11721ed0-c6a0-41aa-bfac-7217806369ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82698316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_
prog_failure.82698316
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2637694012
Short name T253
Test name
Test status
Simulation time 544371256 ps
CPU time 8.28 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:47 PM PDT 24
Peak memory 217988 kb
Host smart-dd364b86-aac9-406e-abc8-0119441d230e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637694012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2637694012
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2634165912
Short name T18
Test name
Test status
Simulation time 965477440 ps
CPU time 32.69 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:42:06 PM PDT 24
Peak memory 246484 kb
Host smart-46942ac9-c35b-475e-981d-a98332d11439
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634165912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2634165912
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1308188945
Short name T569
Test name
Test status
Simulation time 229409408 ps
CPU time 11.52 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 243084 kb
Host smart-cc3d5dd6-6e1a-41fa-838b-85e695bc7b43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308188945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1308188945
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1812988027
Short name T590
Test name
Test status
Simulation time 37840812 ps
CPU time 2.03 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:40 PM PDT 24
Peak memory 218624 kb
Host smart-fdc9f0e9-4471-47c4-9f80-78d36e26496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812988027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1812988027
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3376843963
Short name T650
Test name
Test status
Simulation time 1509117394 ps
CPU time 13.67 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:41 PM PDT 24
Peak memory 218604 kb
Host smart-cced2a29-3a61-4a3d-9c81-d65bf9f36087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376843963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3376843963
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1634316053
Short name T329
Test name
Test status
Simulation time 1881013204 ps
CPU time 6.32 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:34 PM PDT 24
Peak memory 218592 kb
Host smart-f614bc55-4b2c-49c7-a9a4-5496871c7b9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634316053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1634316053
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.190403173
Short name T364
Test name
Test status
Simulation time 106083497 ps
CPU time 3.99 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:38 PM PDT 24
Peak memory 218040 kb
Host smart-71d2d04c-a055-4801-adf7-2c5c7a298a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190403173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.190403173
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3222115902
Short name T718
Test name
Test status
Simulation time 951694771 ps
CPU time 31.73 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:42:03 PM PDT 24
Peak memory 251312 kb
Host smart-f76efff6-6796-4784-a67e-762b454422db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222115902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3222115902
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3310787725
Short name T261
Test name
Test status
Simulation time 58003936 ps
CPU time 7.54 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:40 PM PDT 24
Peak memory 251340 kb
Host smart-c0b80b3b-3282-4bae-bcb0-97f63c8fae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310787725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3310787725
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1810768749
Short name T819
Test name
Test status
Simulation time 27139864631 ps
CPU time 111.61 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:43:22 PM PDT 24
Peak memory 273748 kb
Host smart-d1fed410-cede-4be1-ada6-fc184d5c0185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810768749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1810768749
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.133131507
Short name T392
Test name
Test status
Simulation time 59844843 ps
CPU time 0.8 seconds
Started Jun 28 07:40:57 PM PDT 24
Finished Jun 28 07:41:25 PM PDT 24
Peak memory 209324 kb
Host smart-2d67804a-bfcd-466b-960e-ac7a63ab9121
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133131507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.133131507
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3653125851
Short name T399
Test name
Test status
Simulation time 65760628 ps
CPU time 0.9 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:28 PM PDT 24
Peak memory 209452 kb
Host smart-685e838b-b46e-4741-8323-ab5f0c538e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653125851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3653125851
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3598310865
Short name T405
Test name
Test status
Simulation time 269526295 ps
CPU time 8.42 seconds
Started Jun 28 07:40:57 PM PDT 24
Finished Jun 28 07:41:32 PM PDT 24
Peak memory 218660 kb
Host smart-3846f923-294f-41de-a9ae-9be47b3deb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598310865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3598310865
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4165600672
Short name T826
Test name
Test status
Simulation time 264008866 ps
CPU time 4.38 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 217544 kb
Host smart-407a4739-da82-4733-9bba-b1d403892af1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165600672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4165600672
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3939195358
Short name T685
Test name
Test status
Simulation time 27411482740 ps
CPU time 40.48 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:42:22 PM PDT 24
Peak memory 219796 kb
Host smart-f6ad6070-13c3-4138-944c-1d466988c067
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939195358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3939195358
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1233445234
Short name T775
Test name
Test status
Simulation time 616739125 ps
CPU time 8.97 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 218576 kb
Host smart-066a3407-15ba-41d4-8990-67a2ce8444fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233445234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1233445234
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.4009118522
Short name T396
Test name
Test status
Simulation time 431910987 ps
CPU time 3.38 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:45 PM PDT 24
Peak memory 217576 kb
Host smart-2f1125f2-092d-488a-8bef-a0c41f7682b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009118522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.4009118522
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2200264400
Short name T798
Test name
Test status
Simulation time 4456864925 ps
CPU time 83.55 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 270064 kb
Host smart-e7881ddf-ba45-4d08-a1fa-f41ab7f8edd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200264400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2200264400
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2828634569
Short name T546
Test name
Test status
Simulation time 2380128505 ps
CPU time 7 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:46 PM PDT 24
Peak memory 223316 kb
Host smart-14ae0791-148e-4bd3-af84-bdbbdb6c7fdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828634569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2828634569
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3905839686
Short name T379
Test name
Test status
Simulation time 388193628 ps
CPU time 4.45 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:41:33 PM PDT 24
Peak memory 223160 kb
Host smart-ea4caff6-fe18-4a14-883a-cf8f0b1ecd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905839686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3905839686
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1791542117
Short name T658
Test name
Test status
Simulation time 2366052983 ps
CPU time 11.94 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:46 PM PDT 24
Peak memory 220100 kb
Host smart-2c9e3a83-ae3a-406a-89ca-d6761d5677e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791542117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1791542117
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3075728036
Short name T684
Test name
Test status
Simulation time 640877502 ps
CPU time 12.11 seconds
Started Jun 28 07:40:57 PM PDT 24
Finished Jun 28 07:41:36 PM PDT 24
Peak memory 226368 kb
Host smart-f421195f-b5b0-444a-9c28-75b4b849face
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075728036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3075728036
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3814456392
Short name T475
Test name
Test status
Simulation time 1248041885 ps
CPU time 10.79 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:42 PM PDT 24
Peak memory 226372 kb
Host smart-b7498949-eac2-4a82-82a2-9b2fa2a0fef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814456392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3814456392
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1960552047
Short name T812
Test name
Test status
Simulation time 3864757140 ps
CPU time 10.1 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:38 PM PDT 24
Peak memory 226000 kb
Host smart-15500573-6d0e-4d1d-8d26-6e5c2a86e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960552047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1960552047
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3896497532
Short name T444
Test name
Test status
Simulation time 29915386 ps
CPU time 1.25 seconds
Started Jun 28 07:40:55 PM PDT 24
Finished Jun 28 07:41:23 PM PDT 24
Peak memory 214100 kb
Host smart-06d3354e-2616-421a-9abc-79a680f871c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896497532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3896497532
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2994918339
Short name T403
Test name
Test status
Simulation time 470037977 ps
CPU time 25.42 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:59 PM PDT 24
Peak memory 251196 kb
Host smart-208e0e26-fd75-48d9-be6a-1130cd8afdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994918339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2994918339
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.121974529
Short name T220
Test name
Test status
Simulation time 190994451 ps
CPU time 2.61 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:36 PM PDT 24
Peak memory 222680 kb
Host smart-e5775216-7f70-41c8-aac3-b28c7af7c301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121974529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.121974529
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.850902815
Short name T607
Test name
Test status
Simulation time 28115168197 ps
CPU time 228.86 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:45:27 PM PDT 24
Peak memory 272328 kb
Host smart-c6f18809-ced6-46ac-b022-da851fbe3e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850902815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.850902815
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.844678158
Short name T455
Test name
Test status
Simulation time 21090131 ps
CPU time 0.92 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 209300 kb
Host smart-18f9d2a0-d389-4707-8b88-a07acb0a6816
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844678158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.844678158
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4147499322
Short name T174
Test name
Test status
Simulation time 28442659 ps
CPU time 0.98 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 209332 kb
Host smart-0c89aead-ba65-4e87-b804-c825c85c38be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147499322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4147499322
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4020097348
Short name T431
Test name
Test status
Simulation time 526279956 ps
CPU time 11.93 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:54 PM PDT 24
Peak memory 218612 kb
Host smart-1e17f89b-1717-4534-b957-179b89c91529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020097348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4020097348
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1343123487
Short name T821
Test name
Test status
Simulation time 901143558 ps
CPU time 9.19 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:43 PM PDT 24
Peak memory 217840 kb
Host smart-903acfad-3ad0-470f-8526-9e392a9901fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343123487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1343123487
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2338902860
Short name T643
Test name
Test status
Simulation time 7067234107 ps
CPU time 44.39 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:42:15 PM PDT 24
Peak memory 218636 kb
Host smart-082ed64b-19e2-4ecc-be11-5bed10415a14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338902860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2338902860
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4058978754
Short name T735
Test name
Test status
Simulation time 523904128 ps
CPU time 2.88 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:41:33 PM PDT 24
Peak memory 222152 kb
Host smart-355a6918-ec2c-49e2-a8c6-2e235243a45c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058978754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4058978754
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.417100960
Short name T461
Test name
Test status
Simulation time 376274405 ps
CPU time 9.7 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:43 PM PDT 24
Peak memory 217784 kb
Host smart-d016f805-af4b-49fe-af38-a778aefdfa76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417100960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
417100960
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2679429368
Short name T249
Test name
Test status
Simulation time 850792638 ps
CPU time 40.93 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:42:15 PM PDT 24
Peak memory 251236 kb
Host smart-cdbf4a34-dcf7-4283-aded-ba66052ecb8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679429368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2679429368
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2044811986
Short name T687
Test name
Test status
Simulation time 657877266 ps
CPU time 13.53 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:40 PM PDT 24
Peak memory 250668 kb
Host smart-d65f70f0-b7ba-4da5-852c-0a19df0dd9c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044811986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2044811986
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2105270208
Short name T789
Test name
Test status
Simulation time 1233666597 ps
CPU time 3.02 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:41 PM PDT 24
Peak memory 222732 kb
Host smart-9c4888b2-0ac1-4045-a1b6-d664db32e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105270208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2105270208
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.123626478
Short name T732
Test name
Test status
Simulation time 245835873 ps
CPU time 10.54 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 226456 kb
Host smart-9332ecd1-cd60-4152-8759-1028c6f3f4ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123626478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.123626478
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1223487644
Short name T522
Test name
Test status
Simulation time 683859037 ps
CPU time 13.73 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:52 PM PDT 24
Peak memory 218584 kb
Host smart-8409e523-c307-4ed4-be11-0f003f1655d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223487644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1223487644
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1613210800
Short name T761
Test name
Test status
Simulation time 576506680 ps
CPU time 7.58 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 226432 kb
Host smart-72959c8b-47d3-4b84-919c-22c7c8ef7e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613210800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1613210800
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.804395216
Short name T526
Test name
Test status
Simulation time 53507696 ps
CPU time 2.98 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:30 PM PDT 24
Peak memory 223472 kb
Host smart-ffe3deaa-b404-4add-ad9c-c591ee7c8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804395216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.804395216
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.974768742
Short name T347
Test name
Test status
Simulation time 873553360 ps
CPU time 22.62 seconds
Started Jun 28 07:40:58 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 251340 kb
Host smart-79f1ec7c-94dc-42c9-b0d5-535a6fb903b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974768742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.974768742
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1210707810
Short name T782
Test name
Test status
Simulation time 101896241 ps
CPU time 3.25 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:38 PM PDT 24
Peak memory 222920 kb
Host smart-ebcdba54-7761-4008-bce8-b844447976fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210707810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1210707810
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4153621977
Short name T538
Test name
Test status
Simulation time 13018000248 ps
CPU time 88.6 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 269884 kb
Host smart-c833edfe-4be2-41f5-8796-7d0dc8f7537a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153621977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4153621977
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3379804555
Short name T527
Test name
Test status
Simulation time 19287236 ps
CPU time 1.09 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:35 PM PDT 24
Peak memory 218124 kb
Host smart-62913121-9d77-4fae-bc04-0bb734784ce8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379804555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3379804555
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3251668082
Short name T593
Test name
Test status
Simulation time 23233374 ps
CPU time 0.98 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:45 PM PDT 24
Peak memory 209352 kb
Host smart-83461997-e5b6-4693-be8f-4eeed1995524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251668082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3251668082
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1380770974
Short name T394
Test name
Test status
Simulation time 1709474211 ps
CPU time 10.82 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:41:41 PM PDT 24
Peak memory 218644 kb
Host smart-b382e7ac-a6d5-488d-902f-797233e94c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380770974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1380770974
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4139236156
Short name T325
Test name
Test status
Simulation time 242907173 ps
CPU time 6.2 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 217424 kb
Host smart-39d22753-f132-44f0-8123-99cbbcb1ec0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139236156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4139236156
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3261872839
Short name T432
Test name
Test status
Simulation time 10275608280 ps
CPU time 35.32 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:42:13 PM PDT 24
Peak memory 219272 kb
Host smart-aa9303f8-f5ce-428d-93bf-717b1a60dc14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261872839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3261872839
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2305050293
Short name T579
Test name
Test status
Simulation time 1876148804 ps
CPU time 13.47 seconds
Started Jun 28 07:41:07 PM PDT 24
Finished Jun 28 07:41:58 PM PDT 24
Peak memory 224660 kb
Host smart-436d2a37-0bae-4d36-beeb-b0c83305e867
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305050293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2305050293
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4290702383
Short name T555
Test name
Test status
Simulation time 468751201 ps
CPU time 7.14 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:49 PM PDT 24
Peak memory 217996 kb
Host smart-21ab1fb8-9e42-4fb2-b88c-a11975cd0fea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290702383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.4290702383
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2737666976
Short name T411
Test name
Test status
Simulation time 1096400697 ps
CPU time 46.34 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:42:28 PM PDT 24
Peak memory 252356 kb
Host smart-da087048-ed95-4e05-addb-dd0b1f42a93b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737666976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2737666976
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3044024559
Short name T355
Test name
Test status
Simulation time 324297412 ps
CPU time 9.96 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:52 PM PDT 24
Peak memory 247816 kb
Host smart-213fe82d-1565-4d5a-a403-5defc0d44b03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044024559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3044024559
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3349609092
Short name T365
Test name
Test status
Simulation time 105953069 ps
CPU time 3.2 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:37 PM PDT 24
Peak memory 218748 kb
Host smart-f2a346c0-19d8-42c4-9af2-94f2bcd6c549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349609092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3349609092
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3953114279
Short name T369
Test name
Test status
Simulation time 5062966662 ps
CPU time 13.53 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:42:02 PM PDT 24
Peak memory 219356 kb
Host smart-e537167c-0044-4b39-9f9e-463f21eea239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953114279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3953114279
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1693591278
Short name T424
Test name
Test status
Simulation time 1204606621 ps
CPU time 12.72 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 218636 kb
Host smart-30e21d8d-795a-4786-be05-960153913981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693591278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1693591278
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2272803109
Short name T518
Test name
Test status
Simulation time 228834875 ps
CPU time 6.02 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 218516 kb
Host smart-2230e2a7-6bf6-42cf-8894-7a2703db378e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272803109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2272803109
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3935647302
Short name T696
Test name
Test status
Simulation time 414725941 ps
CPU time 10.95 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:45 PM PDT 24
Peak memory 218724 kb
Host smart-d542a154-248c-460d-a614-37a790348f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935647302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3935647302
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1797691591
Short name T283
Test name
Test status
Simulation time 381751126 ps
CPU time 2.65 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 218036 kb
Host smart-a869b60d-2ab9-4be2-9bd9-0fd11578bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797691591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1797691591
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1427568385
Short name T791
Test name
Test status
Simulation time 286990722 ps
CPU time 28.03 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:42:00 PM PDT 24
Peak memory 251312 kb
Host smart-a1d476c0-1ea7-4d19-9e17-f31a38a35d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427568385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1427568385
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.319647952
Short name T210
Test name
Test status
Simulation time 372566902 ps
CPU time 8.54 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:47 PM PDT 24
Peak memory 251348 kb
Host smart-9d1a7af3-36ab-4620-a7ca-84501d09dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319647952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.319647952
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2030097365
Short name T45
Test name
Test status
Simulation time 5296192082 ps
CPU time 177.32 seconds
Started Jun 28 07:41:07 PM PDT 24
Finished Jun 28 07:44:42 PM PDT 24
Peak memory 278248 kb
Host smart-bb492c79-7f54-4e46-98bc-8dadd51093f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030097365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2030097365
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3943481581
Short name T667
Test name
Test status
Simulation time 52155180 ps
CPU time 0.87 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 213212 kb
Host smart-4f388087-9403-4563-9512-ce7dd4bf8633
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943481581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3943481581
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3558644222
Short name T70
Test name
Test status
Simulation time 38698899 ps
CPU time 0.96 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 209372 kb
Host smart-775c2286-6f72-428f-802e-574001b4f7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558644222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3558644222
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4133234626
Short name T483
Test name
Test status
Simulation time 322426474 ps
CPU time 13.12 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 218640 kb
Host smart-048dd2d8-abd0-4db9-ad47-ad9570f18e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133234626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4133234626
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2962082596
Short name T40
Test name
Test status
Simulation time 3762346110 ps
CPU time 92.45 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 220524 kb
Host smart-d916c60c-f96a-4727-9a76-ace5b3a7a960
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962082596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2962082596
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1653348293
Short name T480
Test name
Test status
Simulation time 131833304 ps
CPU time 3.07 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:41:56 PM PDT 24
Peak memory 222144 kb
Host smart-90b84ce0-53fa-4961-bf70-d3b3fef5ebc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653348293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1653348293
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3435024640
Short name T617
Test name
Test status
Simulation time 771877440 ps
CPU time 9.98 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:48 PM PDT 24
Peak memory 217988 kb
Host smart-632d79c5-122a-4267-b705-7340d3855573
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435024640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3435024640
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1219111001
Short name T678
Test name
Test status
Simulation time 1496766794 ps
CPU time 54.69 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 267660 kb
Host smart-54dfdcf1-a38d-4930-99aa-57f2ea733667
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219111001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1219111001
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3148210186
Short name T762
Test name
Test status
Simulation time 268133130 ps
CPU time 6.44 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:42:00 PM PDT 24
Peak memory 223212 kb
Host smart-02262de4-b8b6-437d-a04d-ec56266f3375
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148210186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3148210186
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3113100114
Short name T498
Test name
Test status
Simulation time 108790339 ps
CPU time 3.36 seconds
Started Jun 28 07:41:12 PM PDT 24
Finished Jun 28 07:41:55 PM PDT 24
Peak memory 218632 kb
Host smart-4754eade-1e48-4007-a558-2ce4c8a28e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113100114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3113100114
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1482110337
Short name T757
Test name
Test status
Simulation time 1326937043 ps
CPU time 11.64 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:53 PM PDT 24
Peak memory 218872 kb
Host smart-659b302b-4861-4f8a-821b-668ebc1de62f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482110337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1482110337
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.34288637
Short name T701
Test name
Test status
Simulation time 1782550305 ps
CPU time 12.84 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:42:07 PM PDT 24
Peak memory 218512 kb
Host smart-059e9533-aa34-4752-b830-2ab6803c5a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34288637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_dig
est.34288637
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3590364631
Short name T708
Test name
Test status
Simulation time 1543836330 ps
CPU time 10.7 seconds
Started Jun 28 07:41:12 PM PDT 24
Finished Jun 28 07:42:03 PM PDT 24
Peak memory 226384 kb
Host smart-f888778f-b335-4c73-8a00-eb7fd2420af9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590364631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3590364631
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3602239022
Short name T717
Test name
Test status
Simulation time 473029979 ps
CPU time 9.75 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:48 PM PDT 24
Peak memory 218696 kb
Host smart-17fb5d59-ba0e-4960-9141-5d34d733934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602239022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3602239022
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2794263737
Short name T730
Test name
Test status
Simulation time 537271892 ps
CPU time 2.85 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 214868 kb
Host smart-aa27c28c-48b1-427b-a814-b79106c9a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794263737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2794263737
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2120165418
Short name T853
Test name
Test status
Simulation time 780520843 ps
CPU time 20.62 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 251336 kb
Host smart-d4d1655f-9b60-4940-8d8f-37d0e740bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120165418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2120165418
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.72841377
Short name T660
Test name
Test status
Simulation time 11419343186 ps
CPU time 117.11 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:43:41 PM PDT 24
Peak memory 278296 kb
Host smart-cece21f2-ff2e-4763-b91d-a25c8ba8e6fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72841377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.lc_ctrl_stress_all.72841377
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2901114419
Short name T153
Test name
Test status
Simulation time 4877732580 ps
CPU time 93.45 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 284256 kb
Host smart-0e5ba777-b1f3-47eb-a0fa-ed0590a71708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2901114419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2901114419
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.683702005
Short name T666
Test name
Test status
Simulation time 15776106 ps
CPU time 0.92 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:41:53 PM PDT 24
Peak memory 212216 kb
Host smart-26ed3c2f-5adc-43a6-8fb9-a61dde535f57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683702005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.683702005
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.861836546
Short name T420
Test name
Test status
Simulation time 18523463 ps
CPU time 0.94 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 209380 kb
Host smart-95a18548-ae9f-4a7b-a41b-2d65263729c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861836546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.861836546
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3024537518
Short name T699
Test name
Test status
Simulation time 2199299602 ps
CPU time 14.27 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 07:41:45 PM PDT 24
Peak memory 226500 kb
Host smart-9eb3a05b-f7af-44fd-93d7-b8462b632d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024537518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3024537518
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.655374409
Short name T95
Test name
Test status
Simulation time 107922906 ps
CPU time 3.1 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:41 PM PDT 24
Peak memory 217420 kb
Host smart-01379227-240d-4230-abb8-953b1aed40ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655374409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.655374409
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.21887514
Short name T588
Test name
Test status
Simulation time 1598586879 ps
CPU time 26.38 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:42:04 PM PDT 24
Peak memory 218564 kb
Host smart-547d8e70-e981-40f7-b6b7-727609e6c868
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.21887514
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3058391151
Short name T281
Test name
Test status
Simulation time 3387962534 ps
CPU time 12.56 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:47 PM PDT 24
Peak memory 226424 kb
Host smart-c1d90a90-d3da-4782-8a44-e9e74568485c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058391151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3058391151
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.543174954
Short name T425
Test name
Test status
Simulation time 1164953178 ps
CPU time 3.98 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:43 PM PDT 24
Peak memory 217984 kb
Host smart-fd47dbdd-e90e-4bea-8126-43f8063ca1cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543174954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
543174954
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3664884230
Short name T450
Test name
Test status
Simulation time 3907425065 ps
CPU time 48.02 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:42:26 PM PDT 24
Peak memory 273732 kb
Host smart-b269465a-7712-4a00-be68-991caa14d168
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664884230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3664884230
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2077564055
Short name T528
Test name
Test status
Simulation time 414072394 ps
CPU time 11.5 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:49 PM PDT 24
Peak memory 251144 kb
Host smart-dfb82ca7-7f35-4fe1-ae39-5f061f0be0de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077564055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2077564055
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.779622876
Short name T709
Test name
Test status
Simulation time 274641100 ps
CPU time 5.88 seconds
Started Jun 28 07:41:04 PM PDT 24
Finished Jun 28 07:41:47 PM PDT 24
Peak memory 222864 kb
Host smart-96946996-c474-4fcd-b56b-0ea7c8270082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779622876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.779622876
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3280776763
Short name T594
Test name
Test status
Simulation time 1012810673 ps
CPU time 11.61 seconds
Started Jun 28 07:41:06 PM PDT 24
Finished Jun 28 07:41:54 PM PDT 24
Peak memory 226392 kb
Host smart-40c8428c-244a-4984-956e-2328c45fa0d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280776763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3280776763
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1107176715
Short name T453
Test name
Test status
Simulation time 977084271 ps
CPU time 8.37 seconds
Started Jun 28 07:41:05 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 218608 kb
Host smart-e18680d5-2cfa-4b36-906e-dd94a300471d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107176715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1107176715
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3648072189
Short name T609
Test name
Test status
Simulation time 495706806 ps
CPU time 11.77 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:50 PM PDT 24
Peak memory 218516 kb
Host smart-7a26f02b-45bd-4bdf-84a1-944c65354072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648072189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3648072189
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.613309146
Short name T599
Test name
Test status
Simulation time 417913597 ps
CPU time 7.93 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:46 PM PDT 24
Peak memory 226436 kb
Host smart-2c051478-a842-426a-acb0-0f23b6ef2fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613309146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.613309146
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4278710952
Short name T69
Test name
Test status
Simulation time 292908366 ps
CPU time 3.42 seconds
Started Jun 28 07:41:13 PM PDT 24
Finished Jun 28 07:41:57 PM PDT 24
Peak memory 218068 kb
Host smart-2d9cf1ed-9cbd-4dba-a632-cd9bc95775ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278710952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4278710952
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3653074671
Short name T598
Test name
Test status
Simulation time 471189508 ps
CPU time 27.28 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:42:05 PM PDT 24
Peak memory 251332 kb
Host smart-695c2afc-b96f-4743-8452-e44f218639d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653074671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3653074671
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2637245481
Short name T303
Test name
Test status
Simulation time 244871311 ps
CPU time 6.25 seconds
Started Jun 28 07:41:00 PM PDT 24
Finished Jun 28 07:41:40 PM PDT 24
Peak memory 247196 kb
Host smart-3fdf1fa8-b792-437f-b9f9-748a1c9289b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637245481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2637245481
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2275511102
Short name T100
Test name
Test status
Simulation time 2185810566 ps
CPU time 44.08 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:42:18 PM PDT 24
Peak memory 220388 kb
Host smart-573d615d-e448-4cec-bd91-913038a169b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275511102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2275511102
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1867884460
Short name T866
Test name
Test status
Simulation time 98990765507 ps
CPU time 1872.41 seconds
Started Jun 28 07:40:59 PM PDT 24
Finished Jun 28 08:12:44 PM PDT 24
Peak memory 497288 kb
Host smart-c9abb723-6763-4f74-8db8-d9ee408838a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1867884460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1867884460
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1270578363
Short name T759
Test name
Test status
Simulation time 39142861 ps
CPU time 0.86 seconds
Started Jun 28 07:41:03 PM PDT 24
Finished Jun 28 07:41:39 PM PDT 24
Peak memory 212200 kb
Host smart-e69b69c6-b138-4219-b33e-a46ce17242b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270578363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1270578363
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3786715572
Short name T409
Test name
Test status
Simulation time 162577027 ps
CPU time 0.97 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 209028 kb
Host smart-f21d05fb-0ba3-4b39-8e17-f68f9ecb62cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786715572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3786715572
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.952528367
Short name T370
Test name
Test status
Simulation time 569031174 ps
CPU time 13.55 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 226448 kb
Host smart-c33f39e7-4018-4f06-a701-6777b8058723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952528367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.952528367
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1253784343
Short name T340
Test name
Test status
Simulation time 825022594 ps
CPU time 19.35 seconds
Started Jun 28 07:41:25 PM PDT 24
Finished Jun 28 07:42:27 PM PDT 24
Peak memory 217564 kb
Host smart-f3c19219-4e35-4ecc-aca1-05230309bb67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253784343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1253784343
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2170517609
Short name T836
Test name
Test status
Simulation time 2562185309 ps
CPU time 41.07 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:40 PM PDT 24
Peak memory 219528 kb
Host smart-68418c75-cb3a-4518-bed7-7c4bb18e2934
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170517609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2170517609
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3935539629
Short name T702
Test name
Test status
Simulation time 2755088750 ps
CPU time 18.15 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:18 PM PDT 24
Peak memory 226108 kb
Host smart-98a3bb2c-7285-4f6c-abb8-c30ebeb8d339
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935539629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3935539629
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1525374267
Short name T656
Test name
Test status
Simulation time 1521840715 ps
CPU time 8.77 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:09 PM PDT 24
Peak memory 217928 kb
Host smart-4d6ab5ea-f11e-4526-90cd-f0183537ec88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525374267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1525374267
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3848465542
Short name T390
Test name
Test status
Simulation time 6678794099 ps
CPU time 62.3 seconds
Started Jun 28 07:41:20 PM PDT 24
Finished Jun 28 07:43:05 PM PDT 24
Peak memory 251268 kb
Host smart-75e8dad9-94a7-4c03-b19b-c6504e57250d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848465542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3848465542
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2001915553
Short name T415
Test name
Test status
Simulation time 1518299789 ps
CPU time 12.83 seconds
Started Jun 28 07:41:19 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 251208 kb
Host smart-75ad62d1-b0ce-42b7-9c09-cd220d67a0a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001915553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2001915553
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3883727888
Short name T863
Test name
Test status
Simulation time 47870351 ps
CPU time 1.66 seconds
Started Jun 28 07:41:01 PM PDT 24
Finished Jun 28 07:41:36 PM PDT 24
Peak memory 218564 kb
Host smart-f5f6252f-8bce-43b7-b899-286d674f0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883727888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3883727888
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2705180093
Short name T740
Test name
Test status
Simulation time 252813537 ps
CPU time 10.25 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 219308 kb
Host smart-213be4a5-5d7e-4719-8d52-725c352285e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705180093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2705180093
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2331024431
Short name T700
Test name
Test status
Simulation time 489815974 ps
CPU time 8.25 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:08 PM PDT 24
Peak memory 218612 kb
Host smart-74b62647-cbcd-41c9-bc36-c57f412f3754
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331024431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2331024431
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2962811183
Short name T305
Test name
Test status
Simulation time 498430910 ps
CPU time 11.43 seconds
Started Jun 28 07:41:15 PM PDT 24
Finished Jun 28 07:42:07 PM PDT 24
Peak memory 218584 kb
Host smart-a36fe237-09e5-446f-8e39-e0b55415d621
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962811183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2962811183
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.730403557
Short name T208
Test name
Test status
Simulation time 420213836 ps
CPU time 9.58 seconds
Started Jun 28 07:41:20 PM PDT 24
Finished Jun 28 07:42:12 PM PDT 24
Peak memory 218776 kb
Host smart-6e28bd3e-34d8-429f-8445-7da4262b2e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730403557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.730403557
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1517459815
Short name T67
Test name
Test status
Simulation time 85426125 ps
CPU time 3.01 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:37 PM PDT 24
Peak memory 215264 kb
Host smart-3ce53aca-9556-4c26-8da0-b174ceadd3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517459815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1517459815
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1674594213
Short name T823
Test name
Test status
Simulation time 267009683 ps
CPU time 22.82 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 251332 kb
Host smart-d7d849b8-a3aa-492c-9009-72b2f7523dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674594213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1674594213
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1070385777
Short name T218
Test name
Test status
Simulation time 267873285 ps
CPU time 6.26 seconds
Started Jun 28 07:41:02 PM PDT 24
Finished Jun 28 07:41:44 PM PDT 24
Peak memory 247796 kb
Host smart-e142b11b-a006-421e-ba59-49e37b4598ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070385777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1070385777
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2985462728
Short name T716
Test name
Test status
Simulation time 12094135465 ps
CPU time 371.85 seconds
Started Jun 28 07:41:20 PM PDT 24
Finished Jun 28 07:48:15 PM PDT 24
Peak memory 252396 kb
Host smart-1e501559-a68b-46a8-8ad3-ecae99727684
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985462728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2985462728
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2768443129
Short name T523
Test name
Test status
Simulation time 15569918 ps
CPU time 1.11 seconds
Started Jun 28 07:41:11 PM PDT 24
Finished Jun 28 07:41:49 PM PDT 24
Peak memory 212304 kb
Host smart-eff9f04e-aa83-4a3d-a53b-1fb231fcb0fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768443129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2768443129
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2438671477
Short name T90
Test name
Test status
Simulation time 61569019 ps
CPU time 1.09 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:48 PM PDT 24
Peak memory 209344 kb
Host smart-3cb463e5-63a5-4b5d-bc94-68de255f0fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438671477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2438671477
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2046420741
Short name T642
Test name
Test status
Simulation time 2144425358 ps
CPU time 8.42 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:40:00 PM PDT 24
Peak memory 218728 kb
Host smart-2a53acf3-e49c-496a-beec-0b0e15aa4bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046420741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2046420741
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.504193474
Short name T846
Test name
Test status
Simulation time 5463505017 ps
CPU time 10.85 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:54 PM PDT 24
Peak memory 218140 kb
Host smart-16548657-8b29-4ed0-b7e6-5d78c5090ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504193474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.504193474
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4161193250
Short name T484
Test name
Test status
Simulation time 943417478 ps
CPU time 30.85 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:40:20 PM PDT 24
Peak memory 218544 kb
Host smart-1f7b44b5-c215-4079-b5e6-3c9c74df96d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161193250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4161193250
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2153816229
Short name T448
Test name
Test status
Simulation time 67131977 ps
CPU time 1.58 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:45 PM PDT 24
Peak memory 217764 kb
Host smart-7a3ff90e-9781-4cdd-a6fb-b82c5b281162
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153816229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
153816229
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3329643103
Short name T441
Test name
Test status
Simulation time 561705517 ps
CPU time 10.99 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:55 PM PDT 24
Peak memory 224560 kb
Host smart-c70fd867-2147-47b8-83c9-0967a69d58d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329643103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3329643103
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1963500287
Short name T451
Test name
Test status
Simulation time 6842321258 ps
CPU time 31.5 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:40:19 PM PDT 24
Peak memory 218036 kb
Host smart-5dd64d38-5b4f-4784-9769-8982ca921864
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963500287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1963500287
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3156753368
Short name T17
Test name
Test status
Simulation time 1771961911 ps
CPU time 4.3 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:51 PM PDT 24
Peak memory 217992 kb
Host smart-0e3c83ba-9fc5-409b-be7d-863678f4824a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156753368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3156753368
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.291592023
Short name T447
Test name
Test status
Simulation time 4408348475 ps
CPU time 53.26 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:40:41 PM PDT 24
Peak memory 268404 kb
Host smart-372f2ec4-cc79-41be-a182-96c35adf7d6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291592023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.291592023
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2293940230
Short name T665
Test name
Test status
Simulation time 3771983455 ps
CPU time 16.89 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:40:04 PM PDT 24
Peak memory 251300 kb
Host smart-b22d2746-6744-4512-8e24-73315f9bd49c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293940230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2293940230
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3909153169
Short name T859
Test name
Test status
Simulation time 294933943 ps
CPU time 3.55 seconds
Started Jun 28 07:39:43 PM PDT 24
Finished Jun 28 07:39:58 PM PDT 24
Peak memory 218612 kb
Host smart-fff9bdd3-903a-4253-98e2-95220dcf117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909153169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3909153169
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3093571678
Short name T378
Test name
Test status
Simulation time 302137765 ps
CPU time 11.3 seconds
Started Jun 28 07:39:40 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 218016 kb
Host smart-477394b5-f889-488a-8a3a-fd8211347411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093571678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3093571678
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.19782247
Short name T827
Test name
Test status
Simulation time 349671547 ps
CPU time 16.21 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:40:04 PM PDT 24
Peak memory 218712 kb
Host smart-798d548b-9417-4c1b-ab53-4259fe139cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19782247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.19782247
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2986716901
Short name T865
Test name
Test status
Simulation time 211297271 ps
CPU time 9.32 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:56 PM PDT 24
Peak memory 218608 kb
Host smart-188cc032-6181-4561-8496-10780f72813a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986716901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2986716901
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1257439648
Short name T600
Test name
Test status
Simulation time 594469523 ps
CPU time 10.63 seconds
Started Jun 28 07:39:36 PM PDT 24
Finished Jun 28 07:39:59 PM PDT 24
Peak memory 218584 kb
Host smart-b326b3d3-d1e9-473d-ad70-12f22ca63145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257439648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
257439648
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3058601491
Short name T507
Test name
Test status
Simulation time 1155579815 ps
CPU time 10.86 seconds
Started Jun 28 07:39:43 PM PDT 24
Finished Jun 28 07:40:06 PM PDT 24
Peak memory 226060 kb
Host smart-fcd6014b-5a6c-4d09-a4f8-d91b5fee25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058601491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3058601491
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3739404707
Short name T77
Test name
Test status
Simulation time 44150891 ps
CPU time 2.62 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 218056 kb
Host smart-c7a0dbe6-1a1d-4171-bea8-302c695da877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739404707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3739404707
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2377165789
Short name T653
Test name
Test status
Simulation time 863597021 ps
CPU time 24.07 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:40:18 PM PDT 24
Peak memory 251324 kb
Host smart-7fd3669a-f104-4b75-ace8-116d587b3e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377165789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2377165789
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4028518803
Short name T32
Test name
Test status
Simulation time 131023735 ps
CPU time 8.91 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 251320 kb
Host smart-07e07863-a026-4810-8941-d18aa93972cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028518803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4028518803
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4042916206
Short name T73
Test name
Test status
Simulation time 11771794598 ps
CPU time 193.27 seconds
Started Jun 28 07:39:38 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 282804 kb
Host smart-c79db5ae-255d-40c8-b695-fa6aa839b868
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042916206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4042916206
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2249622555
Short name T29
Test name
Test status
Simulation time 14504694 ps
CPU time 0.96 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:43 PM PDT 24
Peak memory 209336 kb
Host smart-8cb95bb1-8a26-4df9-866e-2b4dac3e3dd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249622555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2249622555
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.491080196
Short name T494
Test name
Test status
Simulation time 3302310639 ps
CPU time 10.21 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:10 PM PDT 24
Peak memory 218676 kb
Host smart-881d3b68-1ada-41ba-a944-6393267982ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491080196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.491080196
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1049689777
Short name T102
Test name
Test status
Simulation time 185447906 ps
CPU time 5.34 seconds
Started Jun 28 07:41:16 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 217604 kb
Host smart-82a703b5-ad95-4092-8196-02ecc8835bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049689777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1049689777
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2300784926
Short name T849
Test name
Test status
Simulation time 100192805 ps
CPU time 1.66 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:02 PM PDT 24
Peak memory 218628 kb
Host smart-234b4ff3-6554-4ae1-821d-3c3689793652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300784926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2300784926
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2331963999
Short name T15
Test name
Test status
Simulation time 3828535243 ps
CPU time 14.17 seconds
Started Jun 28 07:41:20 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 226516 kb
Host smart-a5511647-f6f1-4d6b-8398-7b9aa8ee5388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331963999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2331963999
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3616104851
Short name T572
Test name
Test status
Simulation time 356293461 ps
CPU time 11.16 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 218616 kb
Host smart-a0139124-a227-4f29-b39f-f5e1b7ad6ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616104851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3616104851
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.510128887
Short name T238
Test name
Test status
Simulation time 637922574 ps
CPU time 20.94 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:21 PM PDT 24
Peak memory 226316 kb
Host smart-1be8951a-78a7-4ff1-85ac-d78905343d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510128887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.510128887
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1033915894
Short name T516
Test name
Test status
Simulation time 3089946221 ps
CPU time 13.73 seconds
Started Jun 28 07:41:15 PM PDT 24
Finished Jun 28 07:42:09 PM PDT 24
Peak memory 226504 kb
Host smart-08090b53-0e4b-403c-b291-b6f245943478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033915894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1033915894
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.669879424
Short name T74
Test name
Test status
Simulation time 45682296 ps
CPU time 2.02 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:02 PM PDT 24
Peak memory 214536 kb
Host smart-e1b3c2e5-d562-4ad5-bd62-963ae20bec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669879424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.669879424
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1549761998
Short name T745
Test name
Test status
Simulation time 506335440 ps
CPU time 17.61 seconds
Started Jun 28 07:41:19 PM PDT 24
Finished Jun 28 07:42:20 PM PDT 24
Peak memory 251284 kb
Host smart-c585897a-2202-4da5-979e-a151536c7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549761998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1549761998
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1357476044
Short name T211
Test name
Test status
Simulation time 167998893 ps
CPU time 6.15 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:06 PM PDT 24
Peak memory 247328 kb
Host smart-0ad2a909-61b5-4eaa-9b1a-3310d1a06098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357476044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1357476044
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3565840384
Short name T81
Test name
Test status
Simulation time 16210442622 ps
CPU time 88.47 seconds
Started Jun 28 07:41:15 PM PDT 24
Finished Jun 28 07:43:23 PM PDT 24
Peak memory 268104 kb
Host smart-211e4136-a4f8-465e-9c7e-023e406159fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565840384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3565840384
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3877358651
Short name T752
Test name
Test status
Simulation time 166343476 ps
CPU time 0.85 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 209284 kb
Host smart-32d91f68-3448-4379-a0b8-e84bfe9d3a1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877358651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3877358651
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.166619924
Short name T820
Test name
Test status
Simulation time 57414955 ps
CPU time 1.1 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 208980 kb
Host smart-37681ad6-bebb-4e9f-b7db-09d4bccdce4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166619924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.166619924
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1698450012
Short name T314
Test name
Test status
Simulation time 1202681664 ps
CPU time 13.31 seconds
Started Jun 28 07:41:21 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 218632 kb
Host smart-d63df76e-d979-4720-a6b3-81e87e2d7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698450012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1698450012
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2505094807
Short name T720
Test name
Test status
Simulation time 268392766 ps
CPU time 3.33 seconds
Started Jun 28 07:41:25 PM PDT 24
Finished Jun 28 07:42:10 PM PDT 24
Peak memory 217504 kb
Host smart-2988cfc2-a3a2-4ea0-b766-d9ed2040e888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505094807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2505094807
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2842876920
Short name T274
Test name
Test status
Simulation time 70628045 ps
CPU time 2.81 seconds
Started Jun 28 07:41:20 PM PDT 24
Finished Jun 28 07:42:05 PM PDT 24
Peak memory 218636 kb
Host smart-659f2bd3-5a43-43dc-94d1-dbb79193d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842876920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2842876920
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3992676785
Short name T157
Test name
Test status
Simulation time 390253958 ps
CPU time 17.82 seconds
Started Jun 28 07:41:15 PM PDT 24
Finished Jun 28 07:42:14 PM PDT 24
Peak memory 218592 kb
Host smart-7af57a0e-29cb-4a91-8cf0-e71b9780caef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992676785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3992676785
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1573231071
Short name T407
Test name
Test status
Simulation time 2038831623 ps
CPU time 8.7 seconds
Started Jun 28 07:41:16 PM PDT 24
Finished Jun 28 07:42:05 PM PDT 24
Peak memory 218604 kb
Host smart-891f1c09-e3fc-4658-8ffa-c009c432ce0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573231071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1573231071
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.948489561
Short name T3
Test name
Test status
Simulation time 858233645 ps
CPU time 8.92 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:42:08 PM PDT 24
Peak memory 218564 kb
Host smart-156af421-277e-42c6-bef1-7c4d77d98201
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948489561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.948489561
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3312261050
Short name T209
Test name
Test status
Simulation time 270350563 ps
CPU time 11.21 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:14 PM PDT 24
Peak memory 218688 kb
Host smart-75d89f04-8c67-4d57-9a9f-43cb081ee78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312261050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3312261050
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1193379930
Short name T354
Test name
Test status
Simulation time 63513737 ps
CPU time 1.47 seconds
Started Jun 28 07:41:16 PM PDT 24
Finished Jun 28 07:42:00 PM PDT 24
Peak memory 214292 kb
Host smart-59458007-c1ff-444a-beb8-0d8685699f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193379930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1193379930
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.4101841837
Short name T214
Test name
Test status
Simulation time 347728367 ps
CPU time 31.22 seconds
Started Jun 28 07:41:16 PM PDT 24
Finished Jun 28 07:42:27 PM PDT 24
Peak memory 251340 kb
Host smart-cb407b79-1727-4986-953e-d2809bdd5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101841837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.4101841837
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3073109695
Short name T496
Test name
Test status
Simulation time 312524259 ps
CPU time 8.26 seconds
Started Jun 28 07:41:14 PM PDT 24
Finished Jun 28 07:42:04 PM PDT 24
Peak memory 251260 kb
Host smart-5970b95f-7af6-4132-92ae-7d5a46c7a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073109695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3073109695
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3037131506
Short name T289
Test name
Test status
Simulation time 4849331953 ps
CPU time 159.32 seconds
Started Jun 28 07:41:17 PM PDT 24
Finished Jun 28 07:44:40 PM PDT 24
Peak memory 270960 kb
Host smart-17e5ca85-c7be-4465-b23b-5335a9aa39c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037131506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3037131506
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3790927294
Short name T98
Test name
Test status
Simulation time 12519965 ps
CPU time 0.85 seconds
Started Jun 28 07:41:25 PM PDT 24
Finished Jun 28 07:42:09 PM PDT 24
Peak memory 209200 kb
Host smart-fa58702b-92d0-457a-9cec-b7c6054ead0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790927294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3790927294
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2370656039
Short name T693
Test name
Test status
Simulation time 156644872 ps
CPU time 0.94 seconds
Started Jun 28 07:41:33 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 209352 kb
Host smart-850fa656-a908-44f6-a8a2-bd34a03e320d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370656039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2370656039
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1911811319
Short name T663
Test name
Test status
Simulation time 588514662 ps
CPU time 22.08 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:40 PM PDT 24
Peak memory 218040 kb
Host smart-f6c48899-726c-4a44-8698-51f40ca6ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911811319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1911811319
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.76837129
Short name T23
Test name
Test status
Simulation time 2093392939 ps
CPU time 6.3 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:21 PM PDT 24
Peak memory 217816 kb
Host smart-f0e1f0cb-3079-4ac7-9486-6ca2c589696c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76837129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.76837129
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.221771130
Short name T375
Test name
Test status
Simulation time 25138631 ps
CPU time 1.92 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:21 PM PDT 24
Peak memory 218628 kb
Host smart-45f3ead3-ef29-4a88-b50e-aba7474ccc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221771130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.221771130
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2791473990
Short name T787
Test name
Test status
Simulation time 1620092290 ps
CPU time 12.26 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:30 PM PDT 24
Peak memory 219304 kb
Host smart-c3e268ed-48ac-41b0-8e53-3e3a607c6e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791473990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2791473990
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3162927839
Short name T380
Test name
Test status
Simulation time 171442602 ps
CPU time 8.19 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:27 PM PDT 24
Peak memory 218608 kb
Host smart-37845802-2d7f-47b7-be78-0f8f12d4d671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162927839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3162927839
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.106367712
Short name T585
Test name
Test status
Simulation time 2836174151 ps
CPU time 7.02 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:42:26 PM PDT 24
Peak memory 218596 kb
Host smart-6ba779f8-7c5f-4558-9872-ed1385cc0844
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106367712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.106367712
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2350866844
Short name T419
Test name
Test status
Simulation time 94965679 ps
CPU time 1.88 seconds
Started Jun 28 07:41:21 PM PDT 24
Finished Jun 28 07:42:05 PM PDT 24
Peak memory 214736 kb
Host smart-6d9430a2-dda9-4b6b-9446-c56672c6627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350866844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2350866844
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.941175379
Short name T479
Test name
Test status
Simulation time 1223743703 ps
CPU time 33.35 seconds
Started Jun 28 07:41:22 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 251324 kb
Host smart-f2bcf7f7-8b9b-4ec5-9227-a9a7087bb3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941175379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.941175379
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.626116809
Short name T672
Test name
Test status
Simulation time 77630772 ps
CPU time 7.31 seconds
Started Jun 28 07:41:21 PM PDT 24
Finished Jun 28 07:42:10 PM PDT 24
Peak memory 251328 kb
Host smart-e640a8c5-3058-4c76-86eb-a94ff5099034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626116809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.626116809
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.520206254
Short name T464
Test name
Test status
Simulation time 6484057417 ps
CPU time 135.76 seconds
Started Jun 28 07:41:45 PM PDT 24
Finished Jun 28 07:44:40 PM PDT 24
Peak memory 228052 kb
Host smart-466f3ac1-674c-4e97-8a2d-dc4e9ba2dfb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520206254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.520206254
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.17417989
Short name T39
Test name
Test status
Simulation time 23199140 ps
CPU time 0.84 seconds
Started Jun 28 07:41:18 PM PDT 24
Finished Jun 28 07:42:01 PM PDT 24
Peak memory 209224 kb
Host smart-2ce2b93c-6b65-4030-b6b4-77f392f379d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctr
l_volatile_unlock_smoke.17417989
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1337586795
Short name T565
Test name
Test status
Simulation time 150664521 ps
CPU time 0.93 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:15 PM PDT 24
Peak memory 209380 kb
Host smart-13e28279-6e85-49a0-bf1b-d7f74985f834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337586795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1337586795
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1934766926
Short name T442
Test name
Test status
Simulation time 1540554576 ps
CPU time 15.75 seconds
Started Jun 28 07:41:33 PM PDT 24
Finished Jun 28 07:42:30 PM PDT 24
Peak memory 226440 kb
Host smart-23963b0e-f184-4f12-924f-2e2f4a3c38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934766926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1934766926
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1173388597
Short name T622
Test name
Test status
Simulation time 355233156 ps
CPU time 1.98 seconds
Started Jun 28 07:41:42 PM PDT 24
Finished Jun 28 07:42:25 PM PDT 24
Peak memory 218060 kb
Host smart-dd1b7bec-4dac-46e7-8002-e4a091534fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173388597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1173388597
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3219539678
Short name T250
Test name
Test status
Simulation time 399136742 ps
CPU time 3.19 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:22 PM PDT 24
Peak memory 218636 kb
Host smart-feea0c82-42c0-476d-96b8-0156bc9f9883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219539678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3219539678
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4002385193
Short name T389
Test name
Test status
Simulation time 1474293337 ps
CPU time 15.37 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:42:31 PM PDT 24
Peak memory 226452 kb
Host smart-4d3ed2de-8e09-4ad4-b055-077c45da059c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002385193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4002385193
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3103084035
Short name T85
Test name
Test status
Simulation time 3759958142 ps
CPU time 17.97 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:33 PM PDT 24
Peak memory 218736 kb
Host smart-f9f70d56-9d1d-4edb-9a98-5571bc16a2c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103084035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3103084035
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4090202436
Short name T324
Test name
Test status
Simulation time 746269750 ps
CPU time 9.99 seconds
Started Jun 28 07:41:39 PM PDT 24
Finished Jun 28 07:42:29 PM PDT 24
Peak memory 226360 kb
Host smart-c45be79c-4180-4088-ac6e-ba3bcc24cb28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090202436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4090202436
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4062003372
Short name T413
Test name
Test status
Simulation time 1154320938 ps
CPU time 10.49 seconds
Started Jun 28 07:41:42 PM PDT 24
Finished Jun 28 07:42:32 PM PDT 24
Peak memory 225152 kb
Host smart-b3d90519-32d5-434e-8c9d-8d7d456b2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062003372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4062003372
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2409841779
Short name T227
Test name
Test status
Simulation time 165265719 ps
CPU time 2.49 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:21 PM PDT 24
Peak memory 214636 kb
Host smart-da24864b-6678-4033-a9c3-c98dbc32d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409841779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2409841779
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1737949149
Short name T460
Test name
Test status
Simulation time 319388010 ps
CPU time 32.33 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 251332 kb
Host smart-4d0a4a62-ce1e-4d61-a5e4-a60009a3a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737949149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1737949149
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2646543645
Short name T811
Test name
Test status
Simulation time 413364463 ps
CPU time 3.54 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:18 PM PDT 24
Peak memory 226684 kb
Host smart-76fe30ec-ab65-49e2-a552-82579f9eceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646543645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2646543645
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2161668667
Short name T486
Test name
Test status
Simulation time 9620532987 ps
CPU time 72.63 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:43:31 PM PDT 24
Peak memory 226808 kb
Host smart-5da93567-df26-4455-b45c-a7835af7cb53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161668667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2161668667
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4023729428
Short name T103
Test name
Test status
Simulation time 78470483666 ps
CPU time 628.23 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:52:47 PM PDT 24
Peak memory 448032 kb
Host smart-4e60c2e4-3e80-424d-afd6-b6ed1c4c1d10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4023729428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4023729428
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1949425579
Short name T770
Test name
Test status
Simulation time 28797493 ps
CPU time 0.84 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 209320 kb
Host smart-995d35a0-435c-4649-9b37-287e1d720dd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949425579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1949425579
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.91484712
Short name T295
Test name
Test status
Simulation time 28593115 ps
CPU time 1.01 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:15 PM PDT 24
Peak memory 209388 kb
Host smart-7e7a996d-ccbd-4a47-ae5a-410539598b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91484712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.91484712
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1335940682
Short name T234
Test name
Test status
Simulation time 839731802 ps
CPU time 9.43 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:23 PM PDT 24
Peak memory 218604 kb
Host smart-0c17630a-4070-489f-adaa-310362dde4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335940682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1335940682
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3505429792
Short name T9
Test name
Test status
Simulation time 11013683463 ps
CPU time 30.89 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 217492 kb
Host smart-66de8d95-f1eb-4a8d-ac27-d1a798a6fb40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505429792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3505429792
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2886882641
Short name T382
Test name
Test status
Simulation time 360274838 ps
CPU time 4.15 seconds
Started Jun 28 07:41:39 PM PDT 24
Finished Jun 28 07:42:23 PM PDT 24
Peak memory 218652 kb
Host smart-17ea41f7-a8c5-4f25-bba5-e346a8a884f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886882641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2886882641
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3689753870
Short name T286
Test name
Test status
Simulation time 1206942007 ps
CPU time 8.2 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:26 PM PDT 24
Peak memory 219292 kb
Host smart-ad8f7482-23ab-493e-b2ed-6778d7378024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689753870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3689753870
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4115322003
Short name T439
Test name
Test status
Simulation time 1521954464 ps
CPU time 12.75 seconds
Started Jun 28 07:41:40 PM PDT 24
Finished Jun 28 07:42:32 PM PDT 24
Peak memory 218600 kb
Host smart-66a124e5-04c1-403d-8b11-5c62bd24716e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115322003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4115322003
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.193438248
Short name T255
Test name
Test status
Simulation time 558912811 ps
CPU time 10.74 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:42:30 PM PDT 24
Peak memory 218588 kb
Host smart-8b757305-1387-41b8-acb6-691e07694580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193438248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.193438248
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1308565101
Short name T423
Test name
Test status
Simulation time 248589800 ps
CPU time 7.51 seconds
Started Jun 28 07:41:44 PM PDT 24
Finished Jun 28 07:42:31 PM PDT 24
Peak memory 218788 kb
Host smart-990dc735-244e-47c0-8508-443f7427c79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308565101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1308565101
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3556368265
Short name T628
Test name
Test status
Simulation time 124916567 ps
CPU time 1.87 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 218072 kb
Host smart-1b34cc1b-2a51-4795-b9c9-77fbb88f2329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556368265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3556368265
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2627680760
Short name T376
Test name
Test status
Simulation time 2656732953 ps
CPU time 27.35 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 251384 kb
Host smart-0283e6cb-0f54-4976-9398-233892dbb73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627680760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2627680760
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1906577174
Short name T539
Test name
Test status
Simulation time 318108427 ps
CPU time 8.32 seconds
Started Jun 28 07:41:40 PM PDT 24
Finished Jun 28 07:42:27 PM PDT 24
Peak memory 251316 kb
Host smart-f9b3ea74-4c99-4d93-82d2-326e6b50a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906577174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1906577174
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.625062119
Short name T290
Test name
Test status
Simulation time 19100641572 ps
CPU time 143.99 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:44:38 PM PDT 24
Peak memory 267784 kb
Host smart-9fc9c67d-6edf-4679-8c08-3ab077ca0048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625062119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.625062119
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3417072234
Short name T838
Test name
Test status
Simulation time 32771319 ps
CPU time 1.15 seconds
Started Jun 28 07:41:44 PM PDT 24
Finished Jun 28 07:42:25 PM PDT 24
Peak memory 218072 kb
Host smart-b2db1695-95eb-41bd-bcb3-d8751027f3bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417072234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3417072234
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3737997650
Short name T490
Test name
Test status
Simulation time 101404585 ps
CPU time 1 seconds
Started Jun 28 07:41:43 PM PDT 24
Finished Jun 28 07:42:23 PM PDT 24
Peak memory 209348 kb
Host smart-28ee94de-7464-41da-802e-18710764234f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737997650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3737997650
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1609026602
Short name T800
Test name
Test status
Simulation time 2064181683 ps
CPU time 9.35 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:28 PM PDT 24
Peak memory 218572 kb
Host smart-864d29eb-e99a-4dc4-9c3b-e4cc53c76081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609026602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1609026602
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1929106152
Short name T330
Test name
Test status
Simulation time 55086230 ps
CPU time 1.34 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:20 PM PDT 24
Peak memory 217404 kb
Host smart-e3e492c5-17b0-4818-a5f3-28b2d665f834
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929106152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1929106152
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1740591622
Short name T766
Test name
Test status
Simulation time 272584128 ps
CPU time 2.82 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:22 PM PDT 24
Peak memory 218636 kb
Host smart-289f54b1-2dfe-4807-9330-8e02c51d8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740591622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1740591622
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.758150747
Short name T268
Test name
Test status
Simulation time 295127467 ps
CPU time 13.27 seconds
Started Jun 28 07:41:39 PM PDT 24
Finished Jun 28 07:42:32 PM PDT 24
Peak memory 226472 kb
Host smart-a7480c11-6946-4a25-8273-b7b86cc10d27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758150747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.758150747
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3629279437
Short name T434
Test name
Test status
Simulation time 1329544829 ps
CPU time 11.85 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:42:26 PM PDT 24
Peak memory 218608 kb
Host smart-0ae28145-95ac-4abc-b81c-33f5d2aac5f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629279437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3629279437
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3883478013
Short name T251
Test name
Test status
Simulation time 2233364856 ps
CPU time 12.94 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:28 PM PDT 24
Peak memory 218620 kb
Host smart-a7af0828-6e3f-41d6-a1d2-56d8def5beed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883478013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3883478013
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.594749944
Short name T4
Test name
Test status
Simulation time 946253048 ps
CPU time 10.77 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:42:30 PM PDT 24
Peak memory 218692 kb
Host smart-d5702fa1-af3e-429b-b82a-b78c3946135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594749944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.594749944
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3885575867
Short name T640
Test name
Test status
Simulation time 40723380 ps
CPU time 1.25 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:16 PM PDT 24
Peak memory 222528 kb
Host smart-a74da2e2-9567-4325-8a18-354db762904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885575867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3885575867
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.493025052
Short name T259
Test name
Test status
Simulation time 270955059 ps
CPU time 22.16 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:37 PM PDT 24
Peak memory 251340 kb
Host smart-e756b8fa-d455-40cb-8525-b8a59b2f4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493025052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.493025052
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3655715378
Short name T384
Test name
Test status
Simulation time 85539968 ps
CPU time 7.39 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:26 PM PDT 24
Peak memory 251124 kb
Host smart-7238d525-5701-4a12-9092-0d7940876cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655715378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3655715378
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4243673407
Short name T358
Test name
Test status
Simulation time 6978025423 ps
CPU time 109.12 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:44:04 PM PDT 24
Peak memory 251264 kb
Host smart-a2586503-cde3-4724-9a99-99423a608869
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243673407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4243673407
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3576370487
Short name T309
Test name
Test status
Simulation time 15389556 ps
CPU time 1 seconds
Started Jun 28 07:41:38 PM PDT 24
Finished Jun 28 07:42:19 PM PDT 24
Peak memory 212220 kb
Host smart-29874009-5479-45de-b859-489db287fc34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576370487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3576370487
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.995060446
Short name T273
Test name
Test status
Simulation time 124928960 ps
CPU time 1.34 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:36 PM PDT 24
Peak memory 209376 kb
Host smart-0eb61217-c19d-4dd0-af42-8773236ddb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995060446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.995060446
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3453387090
Short name T402
Test name
Test status
Simulation time 241695565 ps
CPU time 8.71 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 218644 kb
Host smart-066b567a-3a21-47db-86f8-49602a209e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453387090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3453387090
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1270887542
Short name T844
Test name
Test status
Simulation time 597603276 ps
CPU time 2.05 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 217508 kb
Host smart-868cbdb9-d756-4b2c-91df-89eef4570ba2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270887542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1270887542
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.470727791
Short name T737
Test name
Test status
Simulation time 1629606115 ps
CPU time 3.12 seconds
Started Jun 28 07:41:35 PM PDT 24
Finished Jun 28 07:42:18 PM PDT 24
Peak memory 222748 kb
Host smart-1a92b4a7-a90b-418a-b6fd-03e9e4533ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470727791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.470727791
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2250829428
Short name T64
Test name
Test status
Simulation time 209659814 ps
CPU time 9.62 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 218652 kb
Host smart-c32935d7-a885-4769-85fd-18fa828c1546
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250829428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2250829428
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.352917207
Short name T828
Test name
Test status
Simulation time 638379054 ps
CPU time 11.18 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 218772 kb
Host smart-a832fd4d-6a7d-4a2d-a760-5913942d9667
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352917207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.352917207
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1594862365
Short name T815
Test name
Test status
Simulation time 621557827 ps
CPU time 13.49 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:51 PM PDT 24
Peak memory 218496 kb
Host smart-bd2390ea-7fe7-4c52-83ec-fab6a5f98400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594862365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1594862365
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2646933525
Short name T804
Test name
Test status
Simulation time 4458070615 ps
CPU time 7.23 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:42 PM PDT 24
Peak memory 218788 kb
Host smart-4830dd31-e003-40ff-9f4b-4b2dd166a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646933525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2646933525
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.931976385
Short name T790
Test name
Test status
Simulation time 78549837 ps
CPU time 1.75 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:42:20 PM PDT 24
Peak memory 214604 kb
Host smart-74b28a63-78aa-4a43-8114-2b7dc3b00eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931976385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.931976385
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.26326097
Short name T307
Test name
Test status
Simulation time 345082474 ps
CPU time 32.35 seconds
Started Jun 28 07:41:37 PM PDT 24
Finished Jun 28 07:42:51 PM PDT 24
Peak memory 251344 kb
Host smart-78411ca7-58e3-4749-be2d-fec9790ff26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26326097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.26326097
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1976467678
Short name T638
Test name
Test status
Simulation time 77978987 ps
CPU time 7.76 seconds
Started Jun 28 07:41:36 PM PDT 24
Finished Jun 28 07:42:27 PM PDT 24
Peak memory 251324 kb
Host smart-5a7bf99d-f1f5-45ed-9d5b-981283de5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976467678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1976467678
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.22255463
Short name T695
Test name
Test status
Simulation time 2086184640 ps
CPU time 63.55 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:43:41 PM PDT 24
Peak memory 269012 kb
Host smart-47eb1b2a-de02-4ef5-bb26-f2f6bf1b89af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_stress_all.22255463
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4252811325
Short name T418
Test name
Test status
Simulation time 106508184 ps
CPU time 0.76 seconds
Started Jun 28 07:41:34 PM PDT 24
Finished Jun 28 07:42:15 PM PDT 24
Peak memory 208944 kb
Host smart-817dd5fb-d3c6-40d5-a909-e2687067001c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252811325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4252811325
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.464798042
Short name T401
Test name
Test status
Simulation time 20472977 ps
CPU time 0.92 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:42:37 PM PDT 24
Peak memory 209376 kb
Host smart-73e78b1f-db05-4034-812e-1b506da0c936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464798042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.464798042
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3404860359
Short name T567
Test name
Test status
Simulation time 306559953 ps
CPU time 15.72 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:55 PM PDT 24
Peak memory 218636 kb
Host smart-35741545-2257-44f0-ac89-49b89913debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404860359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3404860359
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.849126238
Short name T422
Test name
Test status
Simulation time 18338101812 ps
CPU time 22.18 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 218128 kb
Host smart-2ae42292-253e-412e-94ec-8827729d1308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849126238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.849126238
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3500138376
Short name T473
Test name
Test status
Simulation time 115265141 ps
CPU time 3.05 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:40 PM PDT 24
Peak memory 222704 kb
Host smart-eb96ef84-4486-48dd-94bb-23696a14df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500138376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3500138376
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3962085913
Short name T262
Test name
Test status
Simulation time 1077634492 ps
CPU time 11.6 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 226428 kb
Host smart-011e3672-8fb5-45d1-942b-c4e97340781e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962085913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3962085913
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1426198328
Short name T279
Test name
Test status
Simulation time 2218900112 ps
CPU time 10.79 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 218656 kb
Host smart-d8ca11f9-4380-4702-9565-13c1644438d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426198328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1426198328
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2781232295
Short name T541
Test name
Test status
Simulation time 257490465 ps
CPU time 8.31 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 218588 kb
Host smart-855d45bd-f1a2-461c-a7b9-552d7611cc40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781232295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2781232295
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3457396554
Short name T109
Test name
Test status
Simulation time 485729883 ps
CPU time 9.27 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 218760 kb
Host smart-df2adb50-c3b4-478d-8c83-e005fa0aa1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457396554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3457396554
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3874976167
Short name T443
Test name
Test status
Simulation time 46540903 ps
CPU time 2.64 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:42 PM PDT 24
Peak memory 218088 kb
Host smart-1346acdb-acc8-4799-b151-c9b530622676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874976167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3874976167
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1030679403
Short name T625
Test name
Test status
Simulation time 921720342 ps
CPU time 25.27 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 251420 kb
Host smart-6210ff88-7e81-44ab-832d-50ef8aa4574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030679403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1030679403
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2187177546
Short name T366
Test name
Test status
Simulation time 87723530 ps
CPU time 4.41 seconds
Started Jun 28 07:42:06 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 226748 kb
Host smart-55486d2e-9a9d-44e7-b5ba-fee306ea1de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187177546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2187177546
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3044250440
Short name T725
Test name
Test status
Simulation time 6125047501 ps
CPU time 99.76 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:44:17 PM PDT 24
Peak memory 250980 kb
Host smart-c66fe86f-fdb1-43d8-b014-175198d96b3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044250440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3044250440
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2906935232
Short name T298
Test name
Test status
Simulation time 28941732 ps
CPU time 1.1 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 213300 kb
Host smart-4bfde2b1-51b6-4eae-bc52-1707ff502f63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906935232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2906935232
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2881155341
Short name T566
Test name
Test status
Simulation time 68981067 ps
CPU time 0.93 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:37 PM PDT 24
Peak memory 209376 kb
Host smart-eb809973-049e-4fc9-9786-373ab5812d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881155341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2881155341
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3712164874
Short name T813
Test name
Test status
Simulation time 1165005259 ps
CPU time 14.9 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 226464 kb
Host smart-817c9e0f-53a4-4440-b60a-a3e561f26cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712164874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3712164874
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4287788498
Short name T734
Test name
Test status
Simulation time 813308176 ps
CPU time 11.47 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 217788 kb
Host smart-99db3d24-9ead-4600-aa99-44b8f8a23e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287788498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4287788498
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3979823497
Short name T575
Test name
Test status
Simulation time 68376611 ps
CPU time 1.97 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 222436 kb
Host smart-82f5c110-9467-47aa-b687-e94e5a0682d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979823497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3979823497
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.333250998
Short name T457
Test name
Test status
Simulation time 921100920 ps
CPU time 15.3 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 219384 kb
Host smart-c2d6d085-2db9-4ce7-8ddc-d50bb0dfbc17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333250998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.333250998
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.212068931
Short name T275
Test name
Test status
Simulation time 620962537 ps
CPU time 14.85 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 218532 kb
Host smart-d4a14e41-a602-4500-8da6-345aab2ac270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212068931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.212068931
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1467990276
Short name T552
Test name
Test status
Simulation time 3433480813 ps
CPU time 10.73 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 219064 kb
Host smart-8e3053b9-0e7f-44bd-9707-fdee6abb696b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467990276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1467990276
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4241783953
Short name T753
Test name
Test status
Simulation time 656775436 ps
CPU time 8.48 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 226436 kb
Host smart-02ac8e8b-ab16-4fd2-b309-f0496b746b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241783953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4241783953
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1828481657
Short name T513
Test name
Test status
Simulation time 32196854 ps
CPU time 2.33 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 214548 kb
Host smart-c8e0b763-267e-467b-8f11-bd4e08679fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828481657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1828481657
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.139310220
Short name T287
Test name
Test status
Simulation time 371591309 ps
CPU time 36.57 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 251276 kb
Host smart-312d7032-3ae0-41ad-ada2-ea9df5273229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139310220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.139310220
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4015989168
Short name T847
Test name
Test status
Simulation time 415575383 ps
CPU time 7.08 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 250892 kb
Host smart-1f407eb5-78f1-47c0-9ff2-a523e0301564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015989168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4015989168
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3877425807
Short name T742
Test name
Test status
Simulation time 2975101215 ps
CPU time 59.8 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:43:36 PM PDT 24
Peak memory 251380 kb
Host smart-aacde907-0294-4448-9b0f-f9f846a72f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877425807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3877425807
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.980941849
Short name T119
Test name
Test status
Simulation time 19943888681 ps
CPU time 210.67 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:46:07 PM PDT 24
Peak memory 251592 kb
Host smart-e2744529-0110-4288-a2f1-cdc60d42a599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=980941849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.980941849
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3868474342
Short name T676
Test name
Test status
Simulation time 46717823 ps
CPU time 0.93 seconds
Started Jun 28 07:42:05 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 217884 kb
Host smart-5cd0de12-4fff-47a5-a301-b6112dee1d4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868474342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3868474342
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2763323891
Short name T515
Test name
Test status
Simulation time 82540113 ps
CPU time 1.05 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 209372 kb
Host smart-2ba0a5d3-6e6b-434f-8764-cec385dcd875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763323891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2763323891
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1567279554
Short name T454
Test name
Test status
Simulation time 1243422246 ps
CPU time 14.11 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:51 PM PDT 24
Peak memory 218656 kb
Host smart-d61d8ef5-b958-4197-98f4-dda7e9a9d871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567279554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1567279554
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3959926339
Short name T713
Test name
Test status
Simulation time 128745300 ps
CPU time 2.35 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:42 PM PDT 24
Peak memory 217468 kb
Host smart-628962b6-14c8-4a65-ada5-4f9c1887aee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959926339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3959926339
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3391559026
Short name T161
Test name
Test status
Simulation time 135883697 ps
CPU time 5.92 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:41 PM PDT 24
Peak memory 218636 kb
Host smart-bc261fa8-ac65-4ed4-9c50-2abfbb855b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391559026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3391559026
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.814111910
Short name T738
Test name
Test status
Simulation time 1822017437 ps
CPU time 20.72 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 219208 kb
Host smart-76412d86-bd4d-42d2-ab3f-49b8bcc1b5cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814111910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.814111910
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3218187789
Short name T459
Test name
Test status
Simulation time 309150426 ps
CPU time 9.43 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 218616 kb
Host smart-949c7c5c-2a90-44c5-96bc-6dcf547af50e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218187789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3218187789
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2689042049
Short name T361
Test name
Test status
Simulation time 395569345 ps
CPU time 13.36 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 218588 kb
Host smart-3359b230-5f09-4d51-87d8-5085d9167211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689042049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2689042049
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2819009830
Short name T714
Test name
Test status
Simulation time 773881896 ps
CPU time 8.95 seconds
Started Jun 28 07:41:59 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 225144 kb
Host smart-c783b22d-deb0-4315-bd28-b3c7eaa78fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819009830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2819009830
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2412288770
Short name T506
Test name
Test status
Simulation time 808146358 ps
CPU time 3.41 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 218088 kb
Host smart-90f1ae05-3479-4d68-a356-ba6573a3d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412288770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2412288770
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2964722408
Short name T333
Test name
Test status
Simulation time 262344817 ps
CPU time 30.24 seconds
Started Jun 28 07:42:03 PM PDT 24
Finished Jun 28 07:43:06 PM PDT 24
Peak memory 251336 kb
Host smart-3434e76d-612e-4556-bd5e-5dd39bacce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964722408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2964722408
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1665951315
Short name T226
Test name
Test status
Simulation time 95157434 ps
CPU time 6.66 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:45 PM PDT 24
Peak memory 250864 kb
Host smart-4e443be3-1f2e-440f-98aa-10ed5c1eacc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665951315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1665951315
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3123485453
Short name T760
Test name
Test status
Simulation time 9923921726 ps
CPU time 280.84 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:47:20 PM PDT 24
Peak memory 226492 kb
Host smart-0fe3558d-7368-4509-81fb-ad8ff7a186d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123485453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3123485453
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1048711900
Short name T105
Test name
Test status
Simulation time 34874303487 ps
CPU time 858.41 seconds
Started Jun 28 07:42:07 PM PDT 24
Finished Jun 28 07:56:58 PM PDT 24
Peak memory 464452 kb
Host smart-0dc2bcd9-6d02-4d31-ada2-8ce57592e749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1048711900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1048711900
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2103372080
Short name T82
Test name
Test status
Simulation time 93944968 ps
CPU time 0.88 seconds
Started Jun 28 07:41:59 PM PDT 24
Finished Jun 28 07:42:36 PM PDT 24
Peak memory 212224 kb
Host smart-923caaa3-3282-4208-95e9-b400ae8350d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103372080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2103372080
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3635386735
Short name T767
Test name
Test status
Simulation time 22551500 ps
CPU time 0.85 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:21 PM PDT 24
Peak memory 209200 kb
Host smart-155434eb-185d-4dee-998d-f17b53a204a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635386735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3635386735
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2190577668
Short name T595
Test name
Test status
Simulation time 13296166 ps
CPU time 0.84 seconds
Started Jun 28 07:39:41 PM PDT 24
Finished Jun 28 07:39:54 PM PDT 24
Peak memory 209132 kb
Host smart-080e7456-c2f9-425a-8c2d-131d19b2d9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190577668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2190577668
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1625574036
Short name T495
Test name
Test status
Simulation time 1428911129 ps
CPU time 11.77 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 218652 kb
Host smart-2377bd57-2f0f-409e-ad32-27511db55455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625574036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1625574036
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2461545359
Short name T96
Test name
Test status
Simulation time 719380472 ps
CPU time 3.16 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 217340 kb
Host smart-27db507c-e057-4bac-9765-66f7ff40853a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461545359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2461545359
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.51018714
Short name T669
Test name
Test status
Simulation time 1892636290 ps
CPU time 51.04 seconds
Started Jun 28 07:39:44 PM PDT 24
Finished Jun 28 07:40:46 PM PDT 24
Peak memory 218400 kb
Host smart-468c9306-7ab9-4fc0-a13b-20cefeea2a54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51018714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.51018714
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1352073946
Short name T377
Test name
Test status
Simulation time 278938152 ps
CPU time 4.12 seconds
Started Jun 28 07:39:43 PM PDT 24
Finished Jun 28 07:39:59 PM PDT 24
Peak memory 217920 kb
Host smart-1f412df9-2879-4284-ba26-03860e3d85d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352073946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
352073946
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2372796068
Short name T175
Test name
Test status
Simulation time 1582437790 ps
CPU time 22.3 seconds
Started Jun 28 07:39:38 PM PDT 24
Finished Jun 28 07:40:12 PM PDT 24
Peak memory 225768 kb
Host smart-9f2dafb7-75d3-4f67-8358-49e342022f47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372796068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2372796068
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2865913596
Short name T646
Test name
Test status
Simulation time 1200107089 ps
CPU time 22.7 seconds
Started Jun 28 07:39:43 PM PDT 24
Finished Jun 28 07:40:17 PM PDT 24
Peak memory 217988 kb
Host smart-7f366256-c807-4908-875b-7f0f5ef674f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865913596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2865913596
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.784210248
Short name T79
Test name
Test status
Simulation time 192611347 ps
CPU time 3.17 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 217892 kb
Host smart-49297d31-56b4-4041-a2e3-0b9781ea5405
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784210248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.784210248
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3073093611
Short name T388
Test name
Test status
Simulation time 2689320610 ps
CPU time 65.97 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:41:00 PM PDT 24
Peak memory 267808 kb
Host smart-2d9e5fd7-fe7f-42ef-ae80-b60e22a7e255
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073093611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3073093611
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4130798880
Short name T675
Test name
Test status
Simulation time 7570729259 ps
CPU time 19.53 seconds
Started Jun 28 07:39:38 PM PDT 24
Finished Jun 28 07:40:10 PM PDT 24
Peak memory 226788 kb
Host smart-114fbe52-4209-4d9d-aea8-b51c9db3af2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130798880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4130798880
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1641786426
Short name T517
Test name
Test status
Simulation time 73933671 ps
CPU time 3.82 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:39:57 PM PDT 24
Peak memory 218584 kb
Host smart-55d6ac62-4c40-485c-8298-86dd52b37c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641786426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1641786426
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3101582935
Short name T83
Test name
Test status
Simulation time 1264655516 ps
CPU time 10.4 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:01 PM PDT 24
Peak memory 215060 kb
Host smart-2f751015-3819-4ef3-a0ab-c56f4a2e7631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101582935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3101582935
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4199703349
Short name T216
Test name
Test status
Simulation time 2196263896 ps
CPU time 15.76 seconds
Started Jun 28 07:39:34 PM PDT 24
Finished Jun 28 07:39:59 PM PDT 24
Peak memory 226608 kb
Host smart-e9f87899-6ed1-47b5-a2fe-926227df140c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199703349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4199703349
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2434235851
Short name T525
Test name
Test status
Simulation time 6530012754 ps
CPU time 9.84 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:01 PM PDT 24
Peak memory 218740 kb
Host smart-5e939bc8-75ba-48ec-a713-3f394724cf0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434235851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2434235851
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1241843696
Short name T352
Test name
Test status
Simulation time 1304092512 ps
CPU time 8.94 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:00 PM PDT 24
Peak memory 218604 kb
Host smart-333549f2-696c-4c85-9f1c-f31313b75c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241843696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
241843696
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2089223132
Short name T458
Test name
Test status
Simulation time 283306663 ps
CPU time 11.07 seconds
Started Jun 28 07:39:35 PM PDT 24
Finished Jun 28 07:39:56 PM PDT 24
Peak memory 226416 kb
Host smart-d5b098cb-05a8-4f37-ad7f-a01db2ffb37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089223132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2089223132
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2766346249
Short name T163
Test name
Test status
Simulation time 771787721 ps
CPU time 4.94 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:39:56 PM PDT 24
Peak memory 218068 kb
Host smart-5228de6e-f917-4ee9-93fa-2e4b4960eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766346249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2766346249
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1264045593
Short name T834
Test name
Test status
Simulation time 1138805016 ps
CPU time 23.07 seconds
Started Jun 28 07:39:39 PM PDT 24
Finished Jun 28 07:40:14 PM PDT 24
Peak memory 251336 kb
Host smart-236a845a-671a-4df2-8bbc-2c6eb30c215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264045593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1264045593
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2686167836
Short name T756
Test name
Test status
Simulation time 61820653 ps
CPU time 8.87 seconds
Started Jun 28 07:39:42 PM PDT 24
Finished Jun 28 07:40:02 PM PDT 24
Peak memory 251344 kb
Host smart-0dc0571e-68aa-4746-b83d-ebe30e52b1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686167836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2686167836
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3218217991
Short name T618
Test name
Test status
Simulation time 3123603397 ps
CPU time 80.03 seconds
Started Jun 28 07:39:45 PM PDT 24
Finished Jun 28 07:41:15 PM PDT 24
Peak memory 279692 kb
Host smart-7ec3b3c4-da74-4415-b990-00d9b696f575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218217991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3218217991
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2824069229
Short name T313
Test name
Test status
Simulation time 44217820 ps
CPU time 0.88 seconds
Started Jun 28 07:39:37 PM PDT 24
Finished Jun 28 07:39:50 PM PDT 24
Peak memory 209492 kb
Host smart-7539f81a-b90d-434d-9f4a-82c6ae4d9320
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824069229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2824069229
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1884425602
Short name T524
Test name
Test status
Simulation time 179925852 ps
CPU time 1.09 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:36 PM PDT 24
Peak memory 209436 kb
Host smart-985f57ef-75c3-4462-bcb4-2daf472a771f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884425602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1884425602
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4083837967
Short name T430
Test name
Test status
Simulation time 250807516 ps
CPU time 2.15 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:39 PM PDT 24
Peak memory 217520 kb
Host smart-c475bd7c-d2b2-4d2f-b0f7-dcb37b6d4bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083837967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4083837967
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2281869910
Short name T239
Test name
Test status
Simulation time 329927575 ps
CPU time 2.95 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 222924 kb
Host smart-c7458a8d-ce1e-41a7-859e-5486feba5c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281869910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2281869910
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4044050986
Short name T611
Test name
Test status
Simulation time 2802414690 ps
CPU time 10.6 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 226512 kb
Host smart-0bb87d4d-0496-4003-bf72-2e0cd8aa1e50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044050986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4044050986
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.770645804
Short name T582
Test name
Test status
Simulation time 472098604 ps
CPU time 11.46 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 218608 kb
Host smart-fcaa55db-3949-437f-ad40-9e0486359443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770645804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.770645804
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.693816272
Short name T12
Test name
Test status
Simulation time 387837278 ps
CPU time 12.55 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 218588 kb
Host smart-2db6b3d6-571e-4e1a-a186-a8a0c760513f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693816272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.693816272
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.613182617
Short name T733
Test name
Test status
Simulation time 1755459095 ps
CPU time 8.9 seconds
Started Jun 28 07:42:00 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 218772 kb
Host smart-96806ea7-7e92-4bb3-bf76-966acfa671b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613182617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.613182617
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.97205736
Short name T633
Test name
Test status
Simulation time 187684107 ps
CPU time 5.54 seconds
Started Jun 28 07:42:05 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 217836 kb
Host smart-1d3dc7dd-4284-4fae-af1c-1a26a0826054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97205736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.97205736
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2784363839
Short name T586
Test name
Test status
Simulation time 1454985425 ps
CPU time 34.2 seconds
Started Jun 28 07:42:06 PM PDT 24
Finished Jun 28 07:43:13 PM PDT 24
Peak memory 251328 kb
Host smart-fc4ed733-50aa-4af6-9fb5-5a1f64ab1929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784363839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2784363839
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2988121275
Short name T682
Test name
Test status
Simulation time 90495643 ps
CPU time 7.26 seconds
Started Jun 28 07:42:01 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 250652 kb
Host smart-c90ce7c8-9efb-4e84-8b60-1ecdad167bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988121275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2988121275
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3297878888
Short name T677
Test name
Test status
Simulation time 51154543869 ps
CPU time 138.34 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:44:56 PM PDT 24
Peak memory 281296 kb
Host smart-5bc831f3-7640-4a7f-89a1-20ede7ad63c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297878888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3297878888
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.105071051
Short name T80
Test name
Test status
Simulation time 48720086 ps
CPU time 1.09 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 212268 kb
Host smart-e22d6a6b-3e00-4ea9-9f88-f511925db6d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105071051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.105071051
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2357636441
Short name T240
Test name
Test status
Simulation time 24224314 ps
CPU time 1.02 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 209404 kb
Host smart-9adf2075-9704-4d6d-8085-b1b47c1a2edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357636441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2357636441
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1454559293
Short name T478
Test name
Test status
Simulation time 327465130 ps
CPU time 11.26 seconds
Started Jun 28 07:42:06 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 226440 kb
Host smart-5b1ffff9-1450-4d34-a508-7485ac9cd180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454559293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1454559293
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.8321113
Short name T772
Test name
Test status
Simulation time 3181931939 ps
CPU time 7.65 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 218280 kb
Host smart-a15a9aed-1bb9-47dc-bc71-ea0aa004c8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8321113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.8321113
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.946860212
Short name T860
Test name
Test status
Simulation time 82378617 ps
CPU time 3.73 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:42 PM PDT 24
Peak memory 218616 kb
Host smart-d626e577-8ba2-4928-b5c7-0416d33b74e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946860212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.946860212
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.853728008
Short name T624
Test name
Test status
Simulation time 837843329 ps
CPU time 15.49 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:57 PM PDT 24
Peak memory 226436 kb
Host smart-a322493d-5e36-452f-a75e-739a6bb4bf35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853728008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.853728008
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1276053582
Short name T634
Test name
Test status
Simulation time 1229347578 ps
CPU time 24.2 seconds
Started Jun 28 07:42:16 PM PDT 24
Finished Jun 28 07:43:06 PM PDT 24
Peak memory 218676 kb
Host smart-a7a409a1-1e74-4d89-8a0e-6f19d41ea0a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276053582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1276053582
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3021676370
Short name T221
Test name
Test status
Simulation time 1768815229 ps
CPU time 12.31 seconds
Started Jun 28 07:42:17 PM PDT 24
Finished Jun 28 07:42:55 PM PDT 24
Peak memory 218592 kb
Host smart-a704db6c-2eab-4aa2-b164-160b2c0b0501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021676370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3021676370
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2820171028
Short name T36
Test name
Test status
Simulation time 1355286790 ps
CPU time 9.89 seconds
Started Jun 28 07:42:06 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 226436 kb
Host smart-d2b305f2-79b0-427d-9315-65ec6818e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820171028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2820171028
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3293399221
Short name T397
Test name
Test status
Simulation time 42892135 ps
CPU time 1.54 seconds
Started Jun 28 07:42:04 PM PDT 24
Finished Jun 28 07:42:40 PM PDT 24
Peak memory 218152 kb
Host smart-1583b7de-8592-47cb-8e7f-b21fc719440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293399221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3293399221
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.489314387
Short name T160
Test name
Test status
Simulation time 403695089 ps
CPU time 30.62 seconds
Started Jun 28 07:42:08 PM PDT 24
Finished Jun 28 07:43:10 PM PDT 24
Peak memory 251336 kb
Host smart-59ab334f-20b8-4973-a400-df21293250a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489314387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.489314387
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3820297884
Short name T514
Test name
Test status
Simulation time 85707759 ps
CPU time 8.96 seconds
Started Jun 28 07:42:05 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 251320 kb
Host smart-b00bf667-fc49-4bee-a892-d0c92a6e516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820297884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3820297884
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.907531786
Short name T299
Test name
Test status
Simulation time 130049287507 ps
CPU time 203.32 seconds
Started Jun 28 07:42:21 PM PDT 24
Finished Jun 28 07:46:08 PM PDT 24
Peak memory 226524 kb
Host smart-53f0523a-b4a0-47c1-aca3-1cd53cf29fa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907531786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.907531786
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1969975601
Short name T164
Test name
Test status
Simulation time 28104028451 ps
CPU time 582.92 seconds
Started Jun 28 07:42:19 PM PDT 24
Finished Jun 28 07:52:26 PM PDT 24
Peak memory 525744 kb
Host smart-3cf4647c-dd37-4ba8-b593-15f5d40b18e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1969975601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1969975601
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3577309255
Short name T644
Test name
Test status
Simulation time 30656775 ps
CPU time 0.84 seconds
Started Jun 28 07:42:02 PM PDT 24
Finished Jun 28 07:42:38 PM PDT 24
Peak memory 208592 kb
Host smart-1d9737f5-b845-4bd2-a9a2-a35dcf59924a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577309255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3577309255
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1079165165
Short name T771
Test name
Test status
Simulation time 74923006 ps
CPU time 1.02 seconds
Started Jun 28 07:42:15 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 209380 kb
Host smart-1438f9ff-4455-4e0d-a164-2ed786545893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079165165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1079165165
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3379162537
Short name T659
Test name
Test status
Simulation time 191667739 ps
CPU time 10.13 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:52 PM PDT 24
Peak memory 218644 kb
Host smart-cd4a323b-f1f2-46c3-bdac-052d20c03581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379162537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3379162537
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2429288970
Short name T21
Test name
Test status
Simulation time 933491687 ps
CPU time 12.15 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 217776 kb
Host smart-ce1f0b1f-b556-4441-b18b-fcb17385d10c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429288970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2429288970
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1796575139
Short name T621
Test name
Test status
Simulation time 107799856 ps
CPU time 3.17 seconds
Started Jun 28 07:42:22 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 222888 kb
Host smart-c763027e-d389-4a41-8c1a-0191e35b987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796575139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1796575139
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1329894951
Short name T570
Test name
Test status
Simulation time 471778645 ps
CPU time 12.87 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:42:57 PM PDT 24
Peak memory 218724 kb
Host smart-b7505d44-153e-4415-b6e1-be794886dee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329894951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1329894951
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3774133059
Short name T101
Test name
Test status
Simulation time 1319161249 ps
CPU time 11.05 seconds
Started Jun 28 07:42:19 PM PDT 24
Finished Jun 28 07:42:55 PM PDT 24
Peak memory 218604 kb
Host smart-235b77e5-7efb-4ae4-bbed-bad4ec26e355
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774133059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3774133059
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1114071709
Short name T829
Test name
Test status
Simulation time 337965129 ps
CPU time 12.41 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:54 PM PDT 24
Peak memory 226316 kb
Host smart-536f5c55-5f7c-4a1e-ad7d-bd6a28792887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114071709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1114071709
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3764494996
Short name T343
Test name
Test status
Simulation time 718312953 ps
CPU time 9.13 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:55 PM PDT 24
Peak memory 218688 kb
Host smart-e0daed0e-97ad-4afa-af99-bcff7665dcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764494996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3764494996
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2257712081
Short name T323
Test name
Test status
Simulation time 113932049 ps
CPU time 2.07 seconds
Started Jun 28 07:42:19 PM PDT 24
Finished Jun 28 07:42:46 PM PDT 24
Peak memory 218068 kb
Host smart-16d28d00-7844-49fd-b041-43e287d5bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257712081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2257712081
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3958663641
Short name T543
Test name
Test status
Simulation time 491483104 ps
CPU time 27.78 seconds
Started Jun 28 07:42:16 PM PDT 24
Finished Jun 28 07:43:10 PM PDT 24
Peak memory 251296 kb
Host smart-ee449619-7c29-43eb-b023-9171ebd142c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958663641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3958663641
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1905853851
Short name T559
Test name
Test status
Simulation time 124414306 ps
CPU time 7.43 seconds
Started Jun 28 07:42:29 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 250800 kb
Host smart-b0a9186e-af60-48bb-a8c6-1ba9fe8288c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905853851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1905853851
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.201258623
Short name T328
Test name
Test status
Simulation time 15832250375 ps
CPU time 172.9 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:45:39 PM PDT 24
Peak memory 271764 kb
Host smart-59a1500d-3b9b-45d9-80ef-1879e1645cb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201258623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.201258623
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1904717274
Short name T28
Test name
Test status
Simulation time 16494601 ps
CPU time 1.16 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:42 PM PDT 24
Peak memory 212248 kb
Host smart-6b28d6d6-0998-43d7-9753-6b261c0bb20a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904717274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1904717274
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3138875043
Short name T806
Test name
Test status
Simulation time 72281518 ps
CPU time 1.2 seconds
Started Jun 28 07:42:15 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 209452 kb
Host smart-19dd9dea-0796-4341-8fab-64a9aa3486c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138875043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3138875043
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.117059813
Short name T504
Test name
Test status
Simulation time 3274941332 ps
CPU time 17 seconds
Started Jun 28 07:42:24 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 226508 kb
Host smart-36048d42-e88c-4219-b67d-f9040e604151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117059813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.117059813
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3954403447
Short name T99
Test name
Test status
Simulation time 404130510 ps
CPU time 4.41 seconds
Started Jun 28 07:42:24 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 217744 kb
Host smart-0028c1c6-8fd3-4a5e-b941-5038a85cb525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954403447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3954403447
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3482596128
Short name T831
Test name
Test status
Simulation time 603620185 ps
CPU time 3.01 seconds
Started Jun 28 07:42:13 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 223048 kb
Host smart-deadd2ec-96c1-4781-ae4d-a446682615e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482596128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3482596128
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2303451896
Short name T467
Test name
Test status
Simulation time 2804972409 ps
CPU time 12.13 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 226432 kb
Host smart-2382b371-6855-4b94-a5be-ed7064c53224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303451896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2303451896
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1582884920
Short name T356
Test name
Test status
Simulation time 314684344 ps
CPU time 11.26 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 218592 kb
Host smart-15eadc98-8324-4a3a-9456-7c0a15db4510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582884920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1582884920
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.300482718
Short name T671
Test name
Test status
Simulation time 578342027 ps
CPU time 11.18 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 218592 kb
Host smart-54700a4d-6915-4050-be1e-d2c0d0d2560f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300482718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.300482718
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.231616369
Short name T858
Test name
Test status
Simulation time 308220485 ps
CPU time 7.07 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 225076 kb
Host smart-f01ea3cd-bc03-4e20-b1d4-b50c11c139ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231616369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.231616369
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.582629827
Short name T726
Test name
Test status
Simulation time 57440399 ps
CPU time 1.94 seconds
Started Jun 28 07:42:13 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 218068 kb
Host smart-d664513f-c604-4a46-8c39-a5447408661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582629827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.582629827
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2345549127
Short name T222
Test name
Test status
Simulation time 255526759 ps
CPU time 25.86 seconds
Started Jun 28 07:42:22 PM PDT 24
Finished Jun 28 07:43:11 PM PDT 24
Peak memory 251352 kb
Host smart-9484b72c-6843-4c3b-b748-ce2006300d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345549127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2345549127
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3388455748
Short name T426
Test name
Test status
Simulation time 53122287 ps
CPU time 2.72 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 222680 kb
Host smart-269a3918-a340-4889-9913-74a1c103b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388455748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3388455748
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1444247992
Short name T339
Test name
Test status
Simulation time 10793746002 ps
CPU time 59.16 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:43:43 PM PDT 24
Peak memory 273472 kb
Host smart-549a261e-87b1-4cc3-bf4f-d54b221b7c9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444247992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1444247992
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3181438403
Short name T697
Test name
Test status
Simulation time 11098654 ps
CPU time 0.74 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:47 PM PDT 24
Peak memory 208324 kb
Host smart-e75c29b2-d987-4156-b853-a04329750d44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181438403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3181438403
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3305374813
Short name T537
Test name
Test status
Simulation time 34953138 ps
CPU time 0.92 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 209304 kb
Host smart-9d847bee-a620-4e5e-bd90-25667b74e677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305374813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3305374813
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2038880700
Short name T571
Test name
Test status
Simulation time 1997279372 ps
CPU time 19.87 seconds
Started Jun 28 07:42:17 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 226456 kb
Host smart-af5f4376-41d9-47cd-a2fd-6e6de11c353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038880700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2038880700
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4051727837
Short name T652
Test name
Test status
Simulation time 888115890 ps
CPU time 20.06 seconds
Started Jun 28 07:42:17 PM PDT 24
Finished Jun 28 07:43:02 PM PDT 24
Peak memory 217504 kb
Host smart-aea0e847-3762-4723-ac32-37b455796d5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051727837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4051727837
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3038456755
Short name T246
Test name
Test status
Simulation time 90266350 ps
CPU time 4.35 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 218624 kb
Host smart-65221c3a-454c-437f-8d0d-961af9f977d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038456755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3038456755
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1090987407
Short name T727
Test name
Test status
Simulation time 970952116 ps
CPU time 11.64 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 226440 kb
Host smart-88c07fb6-8a7c-4772-bfdb-8a15109e10c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090987407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1090987407
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1611485260
Short name T282
Test name
Test status
Simulation time 266503903 ps
CPU time 10.66 seconds
Started Jun 28 07:42:21 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 218616 kb
Host smart-830a9c55-afd1-42a4-bd76-ca29bf8fc304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611485260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1611485260
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3296172030
Short name T217
Test name
Test status
Simulation time 2574922320 ps
CPU time 13.06 seconds
Started Jun 28 07:42:29 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 226432 kb
Host smart-e81b2d77-6156-4b17-9e28-1932cb1f39f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296172030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3296172030
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3740556369
Short name T335
Test name
Test status
Simulation time 1224658140 ps
CPU time 13.45 seconds
Started Jun 28 07:42:16 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 218784 kb
Host smart-d21a7ed9-926f-4583-af0c-41aaf4966aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740556369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3740556369
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1018346083
Short name T639
Test name
Test status
Simulation time 711072967 ps
CPU time 3.67 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 218200 kb
Host smart-be0abb20-dcac-4f62-bc83-e6db10fbf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018346083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1018346083
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3485328417
Short name T414
Test name
Test status
Simulation time 486717135 ps
CPU time 30.56 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 284048 kb
Host smart-73f5e82e-4557-4636-90b9-495fd6524318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485328417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3485328417
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.802567265
Short name T178
Test name
Test status
Simulation time 451832869 ps
CPU time 7.62 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 246780 kb
Host smart-39140092-1d55-436e-be29-c26ab62c3f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802567265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.802567265
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.784493651
Short name T435
Test name
Test status
Simulation time 6872114503 ps
CPU time 80.84 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:44:02 PM PDT 24
Peak memory 251380 kb
Host smart-c40db1d1-ab3f-409b-8d98-0ad040192db1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784493651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.784493651
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.38661812
Short name T156
Test name
Test status
Simulation time 2377563603 ps
CPU time 100.33 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:44:27 PM PDT 24
Peak memory 251436 kb
Host smart-21196deb-3876-440c-ab02-a8e83339198c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=38661812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.38661812
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1236990040
Short name T276
Test name
Test status
Simulation time 44543539 ps
CPU time 0.79 seconds
Started Jun 28 07:42:17 PM PDT 24
Finished Jun 28 07:42:44 PM PDT 24
Peak memory 209208 kb
Host smart-d686a42e-64ec-4de3-b0ea-d0aff4c4869e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236990040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1236990040
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.225538651
Short name T722
Test name
Test status
Simulation time 56802327 ps
CPU time 0.99 seconds
Started Jun 28 07:42:28 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 209364 kb
Host smart-447f1194-22d8-4aa3-984e-7d4a549492d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225538651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.225538651
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1537000103
Short name T97
Test name
Test status
Simulation time 205933351 ps
CPU time 5.66 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 217556 kb
Host smart-86bfdbc8-974f-4caf-b3ae-f83358aa5908
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537000103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1537000103
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2783561402
Short name T63
Test name
Test status
Simulation time 227974084 ps
CPU time 3.97 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 218632 kb
Host smart-d4cd47dd-e68c-46d0-ab83-24386896d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783561402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2783561402
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2230478969
Short name T610
Test name
Test status
Simulation time 236093570 ps
CPU time 12.18 seconds
Started Jun 28 07:42:26 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 226372 kb
Host smart-be9509a1-54d3-4eb1-bd79-1b216efdb169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230478969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2230478969
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3064313643
Short name T602
Test name
Test status
Simulation time 1072916465 ps
CPU time 11.64 seconds
Started Jun 28 07:42:28 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 218592 kb
Host smart-2d120d18-2caf-4587-861c-96035349b50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064313643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3064313643
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3217795597
Short name T244
Test name
Test status
Simulation time 268069952 ps
CPU time 9.77 seconds
Started Jun 28 07:42:19 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 218588 kb
Host smart-52c4bd9c-f65e-46db-a0b9-6bc24409aa4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217795597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3217795597
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.746080827
Short name T560
Test name
Test status
Simulation time 881450456 ps
CPU time 10.42 seconds
Started Jun 28 07:42:28 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 226432 kb
Host smart-65d5bbea-e8b2-4715-acbf-ac7f36906d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746080827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.746080827
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1230592656
Short name T477
Test name
Test status
Simulation time 14037269 ps
CPU time 1.03 seconds
Started Jun 28 07:42:16 PM PDT 24
Finished Jun 28 07:42:43 PM PDT 24
Peak memory 212372 kb
Host smart-6e8349f2-1697-4fe8-b0bd-54179a6979f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230592656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1230592656
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3770910087
Short name T359
Test name
Test status
Simulation time 1349219832 ps
CPU time 30.93 seconds
Started Jun 28 07:42:24 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 251468 kb
Host smart-cc77104d-45b1-43ab-8fc5-fd510c5a6127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770910087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3770910087
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.705885901
Short name T780
Test name
Test status
Simulation time 75101053 ps
CPU time 3.96 seconds
Started Jun 28 07:42:23 PM PDT 24
Finished Jun 28 07:42:50 PM PDT 24
Peak memory 226756 kb
Host smart-a5febb62-2a51-42ae-9036-522a61181214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705885901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.705885901
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4203575901
Short name T159
Test name
Test status
Simulation time 3115013626 ps
CPU time 77.25 seconds
Started Jun 28 07:42:28 PM PDT 24
Finished Jun 28 07:44:05 PM PDT 24
Peak memory 275960 kb
Host smart-448cbd21-e9ea-40d4-9f31-87ed0f344775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203575901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4203575901
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.590399673
Short name T647
Test name
Test status
Simulation time 40915877 ps
CPU time 0.93 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:42:45 PM PDT 24
Peak memory 212292 kb
Host smart-33646539-ce38-4000-a96f-d16058911223
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590399673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.590399673
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2749383722
Short name T724
Test name
Test status
Simulation time 110850810 ps
CPU time 1.15 seconds
Started Jun 28 07:42:45 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 209372 kb
Host smart-977c171a-9b8d-42a8-950e-f55ed7ce152c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749383722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2749383722
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3297567523
Short name T550
Test name
Test status
Simulation time 381851412 ps
CPU time 16.56 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 218640 kb
Host smart-936bfe2d-e3c7-410d-80e8-2d3fa1abcc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297567523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3297567523
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3785924311
Short name T705
Test name
Test status
Simulation time 392345142 ps
CPU time 9.22 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:43:04 PM PDT 24
Peak memory 217720 kb
Host smart-b46b304b-d8a4-4885-8926-e19b2338138c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785924311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3785924311
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2204313113
Short name T631
Test name
Test status
Simulation time 324953101 ps
CPU time 2.15 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:00 PM PDT 24
Peak memory 218620 kb
Host smart-84b92977-eec6-4331-b55f-25e967725f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204313113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2204313113
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4023652560
Short name T554
Test name
Test status
Simulation time 682542380 ps
CPU time 10.22 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:43:07 PM PDT 24
Peak memory 219296 kb
Host smart-45428af6-2a3a-43d5-becd-9a312e136e90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023652560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4023652560
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3483059239
Short name T312
Test name
Test status
Simulation time 354876204 ps
CPU time 8.03 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:06 PM PDT 24
Peak memory 218600 kb
Host smart-659665d0-21fb-4bd4-8ee6-594b9b9adebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483059239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3483059239
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3946977620
Short name T580
Test name
Test status
Simulation time 452072418 ps
CPU time 10.56 seconds
Started Jun 28 07:42:46 PM PDT 24
Finished Jun 28 07:43:06 PM PDT 24
Peak memory 218596 kb
Host smart-c65281bf-b615-4cb3-bc5f-565d5cae80c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946977620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3946977620
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4103451010
Short name T50
Test name
Test status
Simulation time 447178015 ps
CPU time 9.48 seconds
Started Jun 28 07:42:45 PM PDT 24
Finished Jun 28 07:43:05 PM PDT 24
Peak memory 218780 kb
Host smart-69bbb484-e467-4d2b-9616-9b37514af26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103451010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4103451010
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3118777440
Short name T65
Test name
Test status
Simulation time 349344838 ps
CPU time 3.2 seconds
Started Jun 28 07:42:20 PM PDT 24
Finished Jun 28 07:42:48 PM PDT 24
Peak memory 218068 kb
Host smart-a45105f3-c28c-4daa-b827-40295e91e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118777440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3118777440
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3202811494
Short name T861
Test name
Test status
Simulation time 215931264 ps
CPU time 19.57 seconds
Started Jun 28 07:42:14 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 251324 kb
Host smart-eb6a6b06-a622-4d32-9199-59ea02ae8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202811494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3202811494
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2937013178
Short name T743
Test name
Test status
Simulation time 281655110 ps
CPU time 8.33 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 251332 kb
Host smart-3fb0b7e4-e346-4a81-b337-f2f0361f6c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937013178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2937013178
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4009367846
Short name T271
Test name
Test status
Simulation time 3788476460 ps
CPU time 45.42 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:43:42 PM PDT 24
Peak memory 226432 kb
Host smart-bf88ab3b-7017-45a2-abba-162f3c256227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009367846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4009367846
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2873049017
Short name T723
Test name
Test status
Simulation time 14051797 ps
CPU time 0.99 seconds
Started Jun 28 07:42:28 PM PDT 24
Finished Jun 28 07:42:49 PM PDT 24
Peak memory 209336 kb
Host smart-efcddb49-a5db-4529-aa34-053f9cfed50d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873049017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2873049017
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1966644911
Short name T270
Test name
Test status
Simulation time 34287204 ps
CPU time 0.84 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 209136 kb
Host smart-c7010d41-826f-47da-a130-65578b3d2221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966644911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1966644911
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1547640770
Short name T228
Test name
Test status
Simulation time 6990637013 ps
CPU time 16.8 seconds
Started Jun 28 07:42:46 PM PDT 24
Finished Jun 28 07:43:12 PM PDT 24
Peak memory 218908 kb
Host smart-45a038f2-d7a1-44ce-98cc-ffc62578fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547640770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1547640770
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1672119888
Short name T332
Test name
Test status
Simulation time 220260550 ps
CPU time 3.34 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 217436 kb
Host smart-1531a27f-65e1-427a-aed2-3e34df2f34ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672119888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1672119888
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1131132542
Short name T852
Test name
Test status
Simulation time 88427462 ps
CPU time 4.18 seconds
Started Jun 28 07:42:46 PM PDT 24
Finished Jun 28 07:43:00 PM PDT 24
Peak memory 222708 kb
Host smart-02ebea96-bc6a-4b7f-b555-b430be84986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131132542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1131132542
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3409571522
Short name T765
Test name
Test status
Simulation time 1052844634 ps
CPU time 10.33 seconds
Started Jun 28 07:42:49 PM PDT 24
Finished Jun 28 07:43:09 PM PDT 24
Peak memory 226452 kb
Host smart-ab9d2728-7212-4f6c-b579-ffe46384b5b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409571522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3409571522
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.291578600
Short name T561
Test name
Test status
Simulation time 1202239153 ps
CPU time 11.85 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:43:08 PM PDT 24
Peak memory 218608 kb
Host smart-1c4f5c7d-9648-40ae-8ccd-84d07304faa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291578600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.291578600
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3094442681
Short name T301
Test name
Test status
Simulation time 433235020 ps
CPU time 8.99 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:07 PM PDT 24
Peak memory 218584 kb
Host smart-8eb9f544-4bc7-49de-9255-d4586f5d0c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094442681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3094442681
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.515109035
Short name T833
Test name
Test status
Simulation time 2511999785 ps
CPU time 11.83 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:43:07 PM PDT 24
Peak memory 226452 kb
Host smart-e2424b61-624a-4756-ba1f-bd4027187f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515109035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.515109035
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3128574206
Short name T763
Test name
Test status
Simulation time 81433867 ps
CPU time 1.97 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 214612 kb
Host smart-839e60a1-b5c9-4f54-9273-36357ccf09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128574206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3128574206
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1089193699
Short name T367
Test name
Test status
Simulation time 418398586 ps
CPU time 17.33 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:43:12 PM PDT 24
Peak memory 251340 kb
Host smart-de1856df-e7f3-411b-a960-0b72cff1ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089193699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1089193699
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2214210860
Short name T318
Test name
Test status
Simulation time 637019089 ps
CPU time 6.61 seconds
Started Jun 28 07:42:49 PM PDT 24
Finished Jun 28 07:43:06 PM PDT 24
Peak memory 250812 kb
Host smart-2ea7b46d-f071-4bdf-97d0-5744c886cce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214210860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2214210860
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1489941677
Short name T462
Test name
Test status
Simulation time 32903058258 ps
CPU time 510.14 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:51:29 PM PDT 24
Peak memory 267940 kb
Host smart-c78592a8-87a9-4f8e-a740-e3b0ec4b9ad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489941677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1489941677
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1297297039
Short name T548
Test name
Test status
Simulation time 18576545 ps
CPU time 1.15 seconds
Started Jun 28 07:42:49 PM PDT 24
Finished Jun 28 07:43:00 PM PDT 24
Peak memory 217992 kb
Host smart-8e093ecd-8318-4d51-a0eb-0dcf3e329aa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297297039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1297297039
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4244979572
Short name T564
Test name
Test status
Simulation time 17048731 ps
CPU time 1.08 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 209412 kb
Host smart-b9f1e16e-50c0-4f29-9d89-e041a52efe7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244979572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4244979572
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.4191743709
Short name T463
Test name
Test status
Simulation time 410353157 ps
CPU time 17.44 seconds
Started Jun 28 07:42:40 PM PDT 24
Finished Jun 28 07:43:10 PM PDT 24
Peak memory 218568 kb
Host smart-9f143055-f52f-44ea-b66f-80698bfcb25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191743709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.4191743709
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1686137926
Short name T25
Test name
Test status
Simulation time 545471999 ps
CPU time 13.14 seconds
Started Jun 28 07:42:45 PM PDT 24
Finished Jun 28 07:43:08 PM PDT 24
Peak memory 217836 kb
Host smart-031c356d-30aa-4db8-8b29-14ab6054fcad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686137926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1686137926
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3125675472
Short name T545
Test name
Test status
Simulation time 89070707 ps
CPU time 3.11 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:01 PM PDT 24
Peak memory 222736 kb
Host smart-54c70216-211c-458e-a6eb-793aef91b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125675472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3125675472
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3715503378
Short name T225
Test name
Test status
Simulation time 6254211736 ps
CPU time 14.67 seconds
Started Jun 28 07:42:46 PM PDT 24
Finished Jun 28 07:43:11 PM PDT 24
Peak memory 226528 kb
Host smart-29f96294-c480-49a0-9660-a2d31c74662d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715503378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3715503378
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1942026122
Short name T284
Test name
Test status
Simulation time 412869944 ps
CPU time 6.92 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:43:04 PM PDT 24
Peak memory 218672 kb
Host smart-ab23f43c-b33a-4255-8c52-1846b3821335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942026122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1942026122
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3812238100
Short name T350
Test name
Test status
Simulation time 418350006 ps
CPU time 10.1 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:08 PM PDT 24
Peak memory 218596 kb
Host smart-d8eb9a99-c7fb-4f02-b7af-6b19eed03a47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812238100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3812238100
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1034712671
Short name T568
Test name
Test status
Simulation time 505511083 ps
CPU time 12.99 seconds
Started Jun 28 07:42:45 PM PDT 24
Finished Jun 28 07:43:08 PM PDT 24
Peak memory 226436 kb
Host smart-9df5e97f-c152-429b-b650-a4241e7e9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034712671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1034712671
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3507180081
Short name T349
Test name
Test status
Simulation time 67257121 ps
CPU time 2.69 seconds
Started Jun 28 07:42:49 PM PDT 24
Finished Jun 28 07:43:02 PM PDT 24
Peak memory 218064 kb
Host smart-11b51f70-334a-4e3f-b13d-382bca001a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507180081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3507180081
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1649741405
Short name T664
Test name
Test status
Simulation time 512454844 ps
CPU time 31.61 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:29 PM PDT 24
Peak memory 251348 kb
Host smart-691f995b-8842-4336-876b-3cf912d18230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649741405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1649741405
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1228626737
Short name T452
Test name
Test status
Simulation time 160910542 ps
CPU time 6.71 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:05 PM PDT 24
Peak memory 250840 kb
Host smart-7b1bf161-4d2e-4cac-9a9b-4755a302bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228626737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1228626737
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2916695524
Short name T183
Test name
Test status
Simulation time 16992103112 ps
CPU time 94.38 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:44:32 PM PDT 24
Peak memory 276036 kb
Host smart-7fe3adcd-49e4-4f1d-8cbe-415bfed35608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916695524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2916695524
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1872065503
Short name T155
Test name
Test status
Simulation time 9832531930 ps
CPU time 296.33 seconds
Started Jun 28 07:42:50 PM PDT 24
Finished Jun 28 07:47:56 PM PDT 24
Peak memory 294592 kb
Host smart-f3ed1271-9be9-4409-b7d3-3cace61e8323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1872065503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1872065503
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1552801749
Short name T592
Test name
Test status
Simulation time 49129726 ps
CPU time 0.93 seconds
Started Jun 28 07:42:45 PM PDT 24
Finished Jun 28 07:42:56 PM PDT 24
Peak memory 212240 kb
Host smart-66204fa2-2d89-4917-ae95-95476566732c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552801749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1552801749
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1146193
Short name T466
Test name
Test status
Simulation time 22308413 ps
CPU time 1.26 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 209476 kb
Host smart-4ce96b1f-af30-448b-b608-5cac02d993d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1146193
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.91663683
Short name T353
Test name
Test status
Simulation time 286464322 ps
CPU time 13.55 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:11 PM PDT 24
Peak memory 226440 kb
Host smart-bf074320-1c44-4e97-b4bd-a143cfc3f738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91663683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.91663683
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.825995847
Short name T573
Test name
Test status
Simulation time 2221373730 ps
CPU time 13.42 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:43:09 PM PDT 24
Peak memory 217944 kb
Host smart-71cbdead-38f2-4f51-885b-202a1ae5921b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825995847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.825995847
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.654781668
Short name T296
Test name
Test status
Simulation time 103504465 ps
CPU time 2.57 seconds
Started Jun 28 07:42:50 PM PDT 24
Finished Jun 28 07:43:02 PM PDT 24
Peak memory 222684 kb
Host smart-5f2d2f55-6899-4996-aabf-bcffb4ed6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654781668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.654781668
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1359279317
Short name T703
Test name
Test status
Simulation time 221037687 ps
CPU time 11.18 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:09 PM PDT 24
Peak memory 226396 kb
Host smart-b78bb7f3-7d44-4b0b-97e0-d8831982aa7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359279317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1359279317
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3335313185
Short name T601
Test name
Test status
Simulation time 1150805372 ps
CPU time 12.24 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:33 PM PDT 24
Peak memory 218608 kb
Host smart-9e2c4243-a9ff-4b15-a4ae-457f1b27529d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335313185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3335313185
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2735097213
Short name T277
Test name
Test status
Simulation time 1259114636 ps
CPU time 8.98 seconds
Started Jun 28 07:42:50 PM PDT 24
Finished Jun 28 07:43:09 PM PDT 24
Peak memory 226364 kb
Host smart-c2f118aa-cba3-4a51-8646-92b117aac633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735097213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2735097213
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.870520802
Short name T48
Test name
Test status
Simulation time 876655264 ps
CPU time 14.92 seconds
Started Jun 28 07:42:47 PM PDT 24
Finished Jun 28 07:43:12 PM PDT 24
Peak memory 218700 kb
Host smart-0cbdf099-9a86-48a0-99b7-fb842691fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870520802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.870520802
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.727788134
Short name T661
Test name
Test status
Simulation time 343122153 ps
CPU time 2.76 seconds
Started Jun 28 07:42:44 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 218028 kb
Host smart-a550f4f2-1b0c-40fe-914e-c50c1c278d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727788134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.727788134
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1020470853
Short name T856
Test name
Test status
Simulation time 355312917 ps
CPU time 31.95 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:43:30 PM PDT 24
Peak memory 251244 kb
Host smart-fee3ed01-bd9f-43e1-81b2-4f04312cf4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020470853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1020470853
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3988574132
Short name T521
Test name
Test status
Simulation time 68076433 ps
CPU time 3.93 seconds
Started Jun 28 07:42:49 PM PDT 24
Finished Jun 28 07:43:03 PM PDT 24
Peak memory 223056 kb
Host smart-100b9cd5-a5d1-475d-a8dd-d59fc6fc462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988574132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3988574132
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2682301840
Short name T321
Test name
Test status
Simulation time 8994010515 ps
CPU time 149.09 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:45:52 PM PDT 24
Peak memory 281968 kb
Host smart-be7ebb5b-6541-488b-9c1d-c7297c92029e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682301840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2682301840
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3777842561
Short name T436
Test name
Test status
Simulation time 118834224 ps
CPU time 1.22 seconds
Started Jun 28 07:42:48 PM PDT 24
Finished Jun 28 07:42:59 PM PDT 24
Peak memory 218076 kb
Host smart-b2d5398e-decb-4e7d-853f-18a5ae21b3a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777842561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3777842561
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.121287525
Short name T341
Test name
Test status
Simulation time 57072768 ps
CPU time 0.94 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:21 PM PDT 24
Peak memory 209404 kb
Host smart-f2056b0b-2785-4f35-ac2b-a2ca25bdca58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121287525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.121287525
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.229828662
Short name T205
Test name
Test status
Simulation time 67742560 ps
CPU time 0.81 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:21 PM PDT 24
Peak memory 209324 kb
Host smart-9dafcd5b-c86b-466a-9f62-5b872f2398cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229828662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.229828662
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.248569405
Short name T689
Test name
Test status
Simulation time 1518111867 ps
CPU time 19.94 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:43 PM PDT 24
Peak memory 218636 kb
Host smart-0598cc75-7150-4bc1-8430-b25c3c574e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248569405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.248569405
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1300240296
Short name T8
Test name
Test status
Simulation time 283557004 ps
CPU time 3.01 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 217580 kb
Host smart-3bca8729-2f0e-4033-9b8c-1d869e5a7ab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300240296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1300240296
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4113950929
Short name T346
Test name
Test status
Simulation time 3054849550 ps
CPU time 24.46 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:57 PM PDT 24
Peak memory 219076 kb
Host smart-8fcdff0d-361c-4436-9a02-7b6279298e8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113950929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4113950929
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2942912318
Short name T578
Test name
Test status
Simulation time 927441900 ps
CPU time 3.6 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:21 PM PDT 24
Peak memory 218192 kb
Host smart-cf483b4a-2fad-4612-b7ba-c9e3eb59236e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942912318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
942912318
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3393159815
Short name T360
Test name
Test status
Simulation time 359586322 ps
CPU time 5.58 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:39 PM PDT 24
Peak memory 218496 kb
Host smart-57c2efb4-3bdb-4dd1-abfd-4a0e0f765172
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393159815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3393159815
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3045236263
Short name T729
Test name
Test status
Simulation time 1283909091 ps
CPU time 38.21 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:58 PM PDT 24
Peak memory 217996 kb
Host smart-ca6ddba7-7ae2-4bf3-9b18-db2d68ea9976
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045236263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3045236263
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.422325209
Short name T583
Test name
Test status
Simulation time 242737513 ps
CPU time 6.97 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:30 PM PDT 24
Peak memory 217996 kb
Host smart-07c42295-0108-4dcb-8c43-6b9a43015482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422325209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.422325209
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3402823299
Short name T635
Test name
Test status
Simulation time 1810529686 ps
CPU time 12.54 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 251264 kb
Host smart-19d61fb6-ee4d-47ea-ba24-35a5f7e6f510
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402823299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3402823299
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3835460500
Short name T62
Test name
Test status
Simulation time 25866605 ps
CPU time 2.13 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 218624 kb
Host smart-0604c1c3-d7ad-420a-88b6-5003edc4ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835460500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3835460500
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1051131687
Short name T291
Test name
Test status
Simulation time 720617328 ps
CPU time 17.23 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:42 PM PDT 24
Peak memory 218076 kb
Host smart-858b0167-ce6d-4a81-89f1-61d8c0e00f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051131687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1051131687
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1095972889
Short name T52
Test name
Test status
Simulation time 354699555 ps
CPU time 36.51 seconds
Started Jun 28 07:40:05 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 284544 kb
Host smart-8397bc47-6587-4ffe-8d50-2905670a6cbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095972889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1095972889
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.960312981
Short name T536
Test name
Test status
Simulation time 542982240 ps
CPU time 11.36 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:28 PM PDT 24
Peak memory 226448 kb
Host smart-edb659e6-4cb9-46c8-8eda-a3bc07308cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960312981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.960312981
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1615720800
Short name T243
Test name
Test status
Simulation time 908935077 ps
CPU time 9.94 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:30 PM PDT 24
Peak memory 226396 kb
Host smart-7a52189e-b7af-4a65-b3ae-88070e6ac4d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615720800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1615720800
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4071501077
Short name T681
Test name
Test status
Simulation time 392188526 ps
CPU time 9.45 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:27 PM PDT 24
Peak memory 218676 kb
Host smart-49793bec-f8f4-47dc-aef7-9fa89221a045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071501077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
071501077
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.378598462
Short name T337
Test name
Test status
Simulation time 294177997 ps
CPU time 8.7 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:32 PM PDT 24
Peak memory 218608 kb
Host smart-8188cf7f-3552-44a2-b52d-07d48b643305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378598462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.378598462
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1251805616
Short name T331
Test name
Test status
Simulation time 50186053 ps
CPU time 1.76 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:27 PM PDT 24
Peak memory 218044 kb
Host smart-b71c791c-5dd3-4808-a2da-16c77a26989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251805616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1251805616
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1034198860
Short name T113
Test name
Test status
Simulation time 621922906 ps
CPU time 29.19 seconds
Started Jun 28 07:40:05 PM PDT 24
Finished Jun 28 07:40:45 PM PDT 24
Peak memory 246476 kb
Host smart-12f7de4c-6495-4434-9d93-3ab7aa655bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034198860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1034198860
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3197337958
Short name T86
Test name
Test status
Simulation time 154570092 ps
CPU time 6.47 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:29 PM PDT 24
Peak memory 250904 kb
Host smart-e44e8051-56bd-4f84-b2a2-86a53b9a5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197337958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3197337958
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4242321895
Short name T558
Test name
Test status
Simulation time 8169440795 ps
CPU time 139.09 seconds
Started Jun 28 07:40:05 PM PDT 24
Finished Jun 28 07:42:35 PM PDT 24
Peak memory 282888 kb
Host smart-51259712-35e1-4aa2-b978-20766cfb3836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242321895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4242321895
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1793928265
Short name T764
Test name
Test status
Simulation time 52935557170 ps
CPU time 289.84 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:45:19 PM PDT 24
Peak memory 284316 kb
Host smart-e376e680-005b-418b-9fa4-f6b693446f2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1793928265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1793928265
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4273939426
Short name T362
Test name
Test status
Simulation time 53606330 ps
CPU time 1.14 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:26 PM PDT 24
Peak memory 211984 kb
Host smart-52393683-b91c-4f29-9216-a59930145fbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273939426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4273939426
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.794510765
Short name T855
Test name
Test status
Simulation time 16354280 ps
CPU time 1.08 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 209444 kb
Host smart-33487678-6899-495f-b5ee-5887cb588707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794510765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.794510765
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.552943503
Short name T591
Test name
Test status
Simulation time 314209386 ps
CPU time 11.65 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 218628 kb
Host smart-68932158-c83e-47be-82c1-529949e8a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552943503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.552943503
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1512060384
Short name T758
Test name
Test status
Simulation time 645832018 ps
CPU time 3.73 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:15 PM PDT 24
Peak memory 217420 kb
Host smart-494f6908-6f2b-46aa-b3de-30441d3b8865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512060384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1512060384
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4242566851
Short name T306
Test name
Test status
Simulation time 70506270 ps
CPU time 2.06 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 218636 kb
Host smart-2316119b-b070-443f-adb6-b854a6ff7fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242566851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4242566851
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.504463551
Short name T43
Test name
Test status
Simulation time 314720059 ps
CPU time 10.61 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:31 PM PDT 24
Peak memory 226456 kb
Host smart-1b5f824a-31b5-4e25-9adc-ab2157889a72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504463551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.504463551
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3374936273
Short name T236
Test name
Test status
Simulation time 462980429 ps
CPU time 7.67 seconds
Started Jun 28 07:43:05 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 218600 kb
Host smart-2f738859-89ef-4158-94ec-c0e8a27dba74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374936273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3374936273
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.209377193
Short name T300
Test name
Test status
Simulation time 249898968 ps
CPU time 8.3 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:29 PM PDT 24
Peak memory 218592 kb
Host smart-8a8431ac-a853-4c3a-aa9b-ac19d7b8b078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209377193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.209377193
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3089099374
Short name T491
Test name
Test status
Simulation time 1071518749 ps
CPU time 7.15 seconds
Started Jun 28 07:43:06 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 225236 kb
Host smart-7cc4686e-5ba4-4afb-bae1-d71cd949976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089099374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3089099374
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1078020375
Short name T805
Test name
Test status
Simulation time 128466877 ps
CPU time 2.25 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 214820 kb
Host smart-70033f17-7630-4d3f-9681-28390447ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078020375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1078020375
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3539968195
Short name T670
Test name
Test status
Simulation time 1268411503 ps
CPU time 35.28 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:44 PM PDT 24
Peak memory 251332 kb
Host smart-61f25f12-7df2-4f78-8fd3-3fa2977ed4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539968195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3539968195
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3565546036
Short name T825
Test name
Test status
Simulation time 182007061 ps
CPU time 3.43 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 218552 kb
Host smart-a7e3e3d8-0f0e-436f-8b46-0b02a38c4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565546036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3565546036
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2731646552
Short name T785
Test name
Test status
Simulation time 11039383197 ps
CPU time 352.77 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:49:06 PM PDT 24
Peak memory 439520 kb
Host smart-c8d0ae93-92ad-42ff-9730-477e6840ebb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731646552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2731646552
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2560942810
Short name T501
Test name
Test status
Simulation time 37086716 ps
CPU time 0.76 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:20 PM PDT 24
Peak memory 209040 kb
Host smart-ce30d3f7-47b7-4c03-a7db-9c64496b7da2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560942810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2560942810
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2563860726
Short name T519
Test name
Test status
Simulation time 50289864 ps
CPU time 1.01 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 209376 kb
Host smart-66a03c4a-018a-457b-ae42-016394dace20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563860726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2563860726
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.756069533
Short name T437
Test name
Test status
Simulation time 469127542 ps
CPU time 17.28 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:34 PM PDT 24
Peak memory 218616 kb
Host smart-afb866f8-2bb8-4a1c-bccf-b4255c24547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756069533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.756069533
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2174795669
Short name T22
Test name
Test status
Simulation time 661352843 ps
CPU time 6.47 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 217764 kb
Host smart-151b4eea-be8d-457f-8c04-ca520478b9b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174795669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2174795669
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1675344182
Short name T809
Test name
Test status
Simulation time 64572843 ps
CPU time 3.55 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 223044 kb
Host smart-de81e091-f824-4bef-8698-529afa5d78ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675344182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1675344182
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.451987203
Short name T400
Test name
Test status
Simulation time 226338253 ps
CPU time 10.21 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:20 PM PDT 24
Peak memory 226524 kb
Host smart-f57d32d4-326b-46ec-b7b5-c078aff409ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451987203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.451987203
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1526753583
Short name T691
Test name
Test status
Simulation time 471532254 ps
CPU time 8.1 seconds
Started Jun 28 07:43:06 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 218604 kb
Host smart-1e79d987-d12d-419e-8864-2288a984ff9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526753583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1526753583
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3662420767
Short name T632
Test name
Test status
Simulation time 221775186 ps
CPU time 8.53 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:22 PM PDT 24
Peak memory 225324 kb
Host smart-2d0f77b1-b7a4-4dd7-8250-6e77b8844fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662420767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3662420767
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1430276885
Short name T327
Test name
Test status
Simulation time 452435387 ps
CPU time 16.28 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 218620 kb
Host smart-1b2793fb-d9cf-4505-8fd0-69bf8a49f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430276885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1430276885
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2337086861
Short name T657
Test name
Test status
Simulation time 144859420 ps
CPU time 3.66 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:17 PM PDT 24
Peak memory 215264 kb
Host smart-ad7fe5a5-bc3a-4151-a4b4-a3bdddf5999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337086861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2337086861
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1547045822
Short name T158
Test name
Test status
Simulation time 1806967529 ps
CPU time 19.87 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:32 PM PDT 24
Peak memory 251316 kb
Host smart-692a9f9e-ab60-430e-b77e-02eb1935277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547045822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1547045822
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2835394958
Short name T641
Test name
Test status
Simulation time 116464538 ps
CPU time 7.45 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:33 PM PDT 24
Peak memory 251336 kb
Host smart-6e09acc5-3009-4e2e-9619-f5cf1210f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835394958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2835394958
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2399314323
Short name T334
Test name
Test status
Simulation time 29122852023 ps
CPU time 482.5 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:51:26 PM PDT 24
Peak memory 283868 kb
Host smart-bf78d38a-1a3f-4dd9-b86b-cba5ca3d0b2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399314323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2399314323
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3612610975
Short name T744
Test name
Test status
Simulation time 11596615 ps
CPU time 0.98 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 212208 kb
Host smart-aee5048a-8f92-4dcf-95ae-2564be4c2bd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612610975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3612610975
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2631007340
Short name T391
Test name
Test status
Simulation time 16361856 ps
CPU time 1.09 seconds
Started Jun 28 07:43:06 PM PDT 24
Finished Jun 28 07:43:09 PM PDT 24
Peak memory 209380 kb
Host smart-58452f84-b6ac-4fdb-8eee-334c7f574cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631007340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2631007340
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2455530744
Short name T363
Test name
Test status
Simulation time 202034580 ps
CPU time 8.96 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:22 PM PDT 24
Peak memory 226516 kb
Host smart-00fc81af-1473-4ff1-bfbf-0346716c1f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455530744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2455530744
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1320605226
Short name T68
Test name
Test status
Simulation time 114059519 ps
CPU time 1.94 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 217512 kb
Host smart-6414b3a1-ade9-4c2a-9ac0-3270336bec0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320605226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1320605226
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2548550742
Short name T520
Test name
Test status
Simulation time 285562168 ps
CPU time 2.81 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 218648 kb
Host smart-c8922879-1f54-4aed-b9bc-a38b0c34afea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548550742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2548550742
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.265863529
Short name T797
Test name
Test status
Simulation time 244767067 ps
CPU time 7.47 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:19 PM PDT 24
Peak memory 226396 kb
Host smart-d8fbf1fa-d9e0-40c5-ab70-75e8979e3cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265863529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.265863529
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.465032047
Short name T557
Test name
Test status
Simulation time 701721525 ps
CPU time 26.06 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:52 PM PDT 24
Peak memory 218604 kb
Host smart-ea92fd66-9036-4371-8243-20215875812c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465032047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.465032047
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2069997171
Short name T816
Test name
Test status
Simulation time 570363987 ps
CPU time 7.58 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:18 PM PDT 24
Peak memory 226404 kb
Host smart-ed54507f-29b5-4628-94a9-3a80fef13bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069997171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2069997171
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1107502233
Short name T627
Test name
Test status
Simulation time 187714767 ps
CPU time 7.06 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:20 PM PDT 24
Peak memory 218700 kb
Host smart-621475db-a8e5-4e69-a622-d324c816a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107502233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1107502233
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3756298640
Short name T381
Test name
Test status
Simulation time 200976698 ps
CPU time 2.25 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:19 PM PDT 24
Peak memory 214384 kb
Host smart-75a554db-1d34-48be-a60d-88648bf851da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756298640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3756298640
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3361063801
Short name T710
Test name
Test status
Simulation time 768433760 ps
CPU time 18.21 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:41 PM PDT 24
Peak memory 251336 kb
Host smart-69a854df-4bf2-4392-b996-cc4755cfe65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361063801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3361063801
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3537935440
Short name T704
Test name
Test status
Simulation time 376453471 ps
CPU time 3.46 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 226744 kb
Host smart-989686a1-3c0a-4285-9720-91211492643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537935440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3537935440
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.62093798
Short name T20
Test name
Test status
Simulation time 1523364785 ps
CPU time 16.19 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 219764 kb
Host smart-950bee80-f3f0-4384-aa2a-cf209c12ff47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62093798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.lc_ctrl_stress_all.62093798
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1375691075
Short name T629
Test name
Test status
Simulation time 182997231 ps
CPU time 1.13 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 217972 kb
Host smart-4d2fa8c3-2033-47db-8134-4875410ff91d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375691075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1375691075
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2414698847
Short name T510
Test name
Test status
Simulation time 17638201 ps
CPU time 0.94 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 209292 kb
Host smart-eaac0279-5799-44a0-8876-fd4e564f237d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414698847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2414698847
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1049407354
Short name T654
Test name
Test status
Simulation time 1290549265 ps
CPU time 18.98 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:29 PM PDT 24
Peak memory 218640 kb
Host smart-6127f78c-f78b-40d3-aa9f-0209231c43ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049407354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1049407354
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2540797988
Short name T848
Test name
Test status
Simulation time 838980547 ps
CPU time 3.4 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 217456 kb
Host smart-1f88953d-8fb7-4fe2-9ab1-8bc8abac8c98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540797988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2540797988
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3360632852
Short name T179
Test name
Test status
Simulation time 144309304 ps
CPU time 3.08 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:22 PM PDT 24
Peak memory 218552 kb
Host smart-265bd5f4-bff3-4e94-8ece-3a114f413e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360632852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3360632852
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2300375481
Short name T34
Test name
Test status
Simulation time 988935480 ps
CPU time 11.48 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:35 PM PDT 24
Peak memory 226164 kb
Host smart-b715f07b-a4d9-4261-af57-999c1f07a05c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300375481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2300375481
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.215546348
Short name T711
Test name
Test status
Simulation time 2630617949 ps
CPU time 7.46 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:23 PM PDT 24
Peak memory 218676 kb
Host smart-3883a9f2-14fe-41bb-bdb0-565c17491f39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215546348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.215546348
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1404235540
Short name T33
Test name
Test status
Simulation time 3875408485 ps
CPU time 7.83 seconds
Started Jun 28 07:43:06 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 226448 kb
Host smart-be5e289f-4bf2-4967-b836-1d995f983be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404235540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1404235540
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4193948231
Short name T428
Test name
Test status
Simulation time 342920386 ps
CPU time 8.84 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 226448 kb
Host smart-9641d2c6-de24-4022-ab61-54d236fcdec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193948231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4193948231
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2893361068
Short name T59
Test name
Test status
Simulation time 53841901 ps
CPU time 3.5 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:30 PM PDT 24
Peak memory 218068 kb
Host smart-14b18e85-1e16-4129-a624-624ede723e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893361068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2893361068
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1145102773
Short name T746
Test name
Test status
Simulation time 229156263 ps
CPU time 25.24 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:49 PM PDT 24
Peak memory 251128 kb
Host smart-e3f1c7f4-0829-4f9f-93d0-668f446858a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145102773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1145102773
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2396640732
Short name T336
Test name
Test status
Simulation time 117090499 ps
CPU time 7.96 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:25 PM PDT 24
Peak memory 251328 kb
Host smart-961e86ff-4ebd-412c-bedd-2c8ff7595717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396640732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2396640732
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1994336500
Short name T810
Test name
Test status
Simulation time 4378509137 ps
CPU time 68.2 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:44:26 PM PDT 24
Peak memory 267776 kb
Host smart-13fa4b12-126a-4d07-90a4-a7d43df83ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994336500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1994336500
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.800044586
Short name T482
Test name
Test status
Simulation time 43943420 ps
CPU time 0.88 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:26 PM PDT 24
Peak memory 209508 kb
Host smart-49d29256-52e4-483b-9e85-d0064b738b6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800044586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.800044586
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4168390008
Short name T509
Test name
Test status
Simulation time 66159117 ps
CPU time 0.87 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:16 PM PDT 24
Peak memory 209124 kb
Host smart-5b151133-c138-466e-8100-f6c3e2982b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168390008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4168390008
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1237911197
Short name T465
Test name
Test status
Simulation time 845743133 ps
CPU time 10.11 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:37 PM PDT 24
Peak memory 226396 kb
Host smart-f4f94b15-43d2-4c03-982c-da74ab83f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237911197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1237911197
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2297322618
Short name T792
Test name
Test status
Simulation time 2065260299 ps
CPU time 12.6 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:34 PM PDT 24
Peak memory 217852 kb
Host smart-cd5a212d-e21b-42d3-82df-b25df78fd5ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297322618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2297322618
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2261634513
Short name T551
Test name
Test status
Simulation time 386855110 ps
CPU time 4.34 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 223188 kb
Host smart-e207c23a-b0ce-494b-8486-d58c8b9cf859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261634513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2261634513
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2899926428
Short name T421
Test name
Test status
Simulation time 459403368 ps
CPU time 8.95 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:27 PM PDT 24
Peak memory 226452 kb
Host smart-7d6a3e3c-15d2-44da-b230-4b72e33e9c5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899926428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2899926428
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3736400077
Short name T474
Test name
Test status
Simulation time 1134595973 ps
CPU time 11.72 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 218600 kb
Host smart-0ee2abfc-d6cd-4fba-941f-0d68aab5668e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736400077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3736400077
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2272579990
Short name T623
Test name
Test status
Simulation time 4341112080 ps
CPU time 10.03 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:37 PM PDT 24
Peak memory 226280 kb
Host smart-2a3f6a3f-9e58-42f1-94ab-1eccc3546b48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272579990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2272579990
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1143112664
Short name T385
Test name
Test status
Simulation time 475312736 ps
CPU time 10.58 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:29 PM PDT 24
Peak memory 218768 kb
Host smart-b15384b2-7724-49fa-9d76-9277f77f516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143112664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1143112664
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3405689717
Short name T61
Test name
Test status
Simulation time 176276880 ps
CPU time 9.94 seconds
Started Jun 28 07:43:10 PM PDT 24
Finished Jun 28 07:43:26 PM PDT 24
Peak memory 226236 kb
Host smart-b1c4b858-fa2e-4ad8-93e1-64618fcb2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405689717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3405689717
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.332388558
Short name T417
Test name
Test status
Simulation time 741017978 ps
CPU time 22.31 seconds
Started Jun 28 07:43:07 PM PDT 24
Finished Jun 28 07:43:32 PM PDT 24
Peak memory 251244 kb
Host smart-933589f9-3974-4028-b0f9-3b1faa8e83c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332388558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.332388558
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.399892719
Short name T706
Test name
Test status
Simulation time 49612081 ps
CPU time 3.34 seconds
Started Jun 28 07:43:11 PM PDT 24
Finished Jun 28 07:43:23 PM PDT 24
Peak memory 222704 kb
Host smart-6b256768-bb79-43c6-b539-9dde240887e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399892719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.399892719
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4083291185
Short name T755
Test name
Test status
Simulation time 1684785724 ps
CPU time 79.64 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:44:35 PM PDT 24
Peak memory 277244 kb
Host smart-8e37b922-93fe-4914-9535-112a342f9a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083291185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4083291185
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.527584175
Short name T368
Test name
Test status
Simulation time 12400978 ps
CPU time 0.8 seconds
Started Jun 28 07:43:12 PM PDT 24
Finished Jun 28 07:43:24 PM PDT 24
Peak memory 209140 kb
Host smart-9914167f-9f72-4674-8f8d-64301e1be11b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527584175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.527584175
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1067277324
Short name T89
Test name
Test status
Simulation time 27370633 ps
CPU time 0.83 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 209196 kb
Host smart-6875fa76-3c0a-499a-ae2f-0dd558f7a841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067277324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1067277324
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3619680618
Short name T46
Test name
Test status
Simulation time 265619334 ps
CPU time 9.53 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:35 PM PDT 24
Peak memory 218632 kb
Host smart-55c892df-98c2-4340-a777-57cb404adea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619680618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3619680618
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1722116014
Short name T492
Test name
Test status
Simulation time 722379543 ps
CPU time 5.11 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:31 PM PDT 24
Peak memory 217596 kb
Host smart-e5e96231-4bd1-4198-bac4-253bc08fed01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722116014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1722116014
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.272072040
Short name T801
Test name
Test status
Simulation time 19271199 ps
CPU time 1.55 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:27 PM PDT 24
Peak memory 218628 kb
Host smart-b80b6cbf-bcbc-4826-99ba-52bffc9e8548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272072040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.272072040
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3256839449
Short name T472
Test name
Test status
Simulation time 601558412 ps
CPU time 11.07 seconds
Started Jun 28 07:43:14 PM PDT 24
Finished Jun 28 07:43:37 PM PDT 24
Peak memory 226436 kb
Host smart-9af23e39-6aba-4649-bef0-8dacce192571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256839449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3256839449
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1687950039
Short name T773
Test name
Test status
Simulation time 1468902160 ps
CPU time 10.28 seconds
Started Jun 28 07:43:17 PM PDT 24
Finished Jun 28 07:43:38 PM PDT 24
Peak memory 218608 kb
Host smart-6910febe-1255-4c08-be5f-06e371edb1bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687950039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1687950039
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1812626547
Short name T731
Test name
Test status
Simulation time 1952904542 ps
CPU time 11.09 seconds
Started Jun 28 07:43:14 PM PDT 24
Finished Jun 28 07:43:37 PM PDT 24
Peak memory 226372 kb
Host smart-7bd4f206-dfd3-499b-b00d-50437b3a1ba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812626547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1812626547
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.616478538
Short name T530
Test name
Test status
Simulation time 337925318 ps
CPU time 8.63 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:32 PM PDT 24
Peak memory 225980 kb
Host smart-bc5935bf-0cb6-4304-82b2-e4161e154d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616478538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.616478538
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.582454853
Short name T66
Test name
Test status
Simulation time 267602285 ps
CPU time 3.17 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:18 PM PDT 24
Peak memory 214784 kb
Host smart-58d3faf3-5ba5-4018-8971-2fa8eb0cb120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582454853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.582454853
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1142732136
Short name T784
Test name
Test status
Simulation time 571317400 ps
CPU time 34.86 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:44:01 PM PDT 24
Peak memory 251420 kb
Host smart-0bc19672-154f-480c-a0f7-2035db09ec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142732136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1142732136
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1644714004
Short name T707
Test name
Test status
Simulation time 368509882 ps
CPU time 7.83 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:33 PM PDT 24
Peak memory 244932 kb
Host smart-f9a3b26b-4310-4049-9ca0-e9092855fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644714004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1644714004
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1726724524
Short name T30
Test name
Test status
Simulation time 38227687 ps
CPU time 0.9 seconds
Started Jun 28 07:43:13 PM PDT 24
Finished Jun 28 07:43:24 PM PDT 24
Peak memory 209276 kb
Host smart-c048590d-4874-429e-a8e8-bda26dcaf271
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726724524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1726724524
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4284610109
Short name T110
Test name
Test status
Simulation time 13722234 ps
CPU time 0.97 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 209444 kb
Host smart-73d20e45-0d7c-4213-b9b8-b04245a38bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284610109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4284610109
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1590459860
Short name T416
Test name
Test status
Simulation time 6096700361 ps
CPU time 17.1 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:45 PM PDT 24
Peak memory 219336 kb
Host smart-c29d2b20-b8fc-40f8-b847-f64df4545dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590459860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1590459860
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3332889709
Short name T651
Test name
Test status
Simulation time 139864283 ps
CPU time 2.53 seconds
Started Jun 28 07:43:17 PM PDT 24
Finished Jun 28 07:43:31 PM PDT 24
Peak memory 217464 kb
Host smart-dd217e21-2d0b-4b8f-9f6b-49f39c8dca58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332889709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3332889709
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.561514964
Short name T94
Test name
Test status
Simulation time 141417025 ps
CPU time 3.11 seconds
Started Jun 28 07:43:20 PM PDT 24
Finished Jun 28 07:43:33 PM PDT 24
Peak memory 218624 kb
Host smart-c885d69e-baa5-40d9-ba7a-dbc791c9d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561514964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.561514964
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3652728160
Short name T668
Test name
Test status
Simulation time 1658441424 ps
CPU time 13.23 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:41 PM PDT 24
Peak memory 226420 kb
Host smart-b06aaaf6-5eb1-48ea-99c7-770bd3c14136
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652728160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3652728160
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2685273733
Short name T529
Test name
Test status
Simulation time 1038633056 ps
CPU time 9.26 seconds
Started Jun 28 07:43:20 PM PDT 24
Finished Jun 28 07:43:39 PM PDT 24
Peak memory 218620 kb
Host smart-7e020f33-1047-4381-8c57-71131a8ecfa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685273733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2685273733
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1869520582
Short name T57
Test name
Test status
Simulation time 813463493 ps
CPU time 8.3 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:36 PM PDT 24
Peak memory 218560 kb
Host smart-54320845-3e58-444e-89f0-9ea9c51e780b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869520582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1869520582
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3869098926
Short name T683
Test name
Test status
Simulation time 198682539 ps
CPU time 8.68 seconds
Started Jun 28 07:43:20 PM PDT 24
Finished Jun 28 07:43:39 PM PDT 24
Peak memory 226444 kb
Host smart-a1f144b3-19ed-4e25-b405-11382e0f2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869098926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3869098926
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2830889876
Short name T338
Test name
Test status
Simulation time 69770662 ps
CPU time 3.58 seconds
Started Jun 28 07:43:17 PM PDT 24
Finished Jun 28 07:43:32 PM PDT 24
Peak memory 218068 kb
Host smart-ffb6f795-a3df-4442-b11d-f25829903039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830889876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2830889876
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.666581999
Short name T317
Test name
Test status
Simulation time 1048572700 ps
CPU time 18.76 seconds
Started Jun 28 07:43:20 PM PDT 24
Finished Jun 28 07:43:49 PM PDT 24
Peak memory 251336 kb
Host smart-c2568ee6-d89a-4ddb-b9c3-0b2d378494d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666581999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.666581999
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.86565278
Short name T776
Test name
Test status
Simulation time 124773865 ps
CPU time 6.48 seconds
Started Jun 28 07:43:17 PM PDT 24
Finished Jun 28 07:43:35 PM PDT 24
Peak memory 250756 kb
Host smart-6e880645-54ae-4bd1-8726-41788ec52b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86565278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.86565278
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.4225337592
Short name T171
Test name
Test status
Simulation time 26111052963 ps
CPU time 206.69 seconds
Started Jun 28 07:43:17 PM PDT 24
Finished Jun 28 07:46:55 PM PDT 24
Peak memory 272344 kb
Host smart-6de3207a-2e7d-4528-85c0-c8357f401d34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225337592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.4225337592
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4292152255
Short name T854
Test name
Test status
Simulation time 29088890 ps
CPU time 1.07 seconds
Started Jun 28 07:43:20 PM PDT 24
Finished Jun 28 07:43:31 PM PDT 24
Peak memory 212244 kb
Host smart-c90d8d01-6613-427a-83a0-c6cd57bcf44d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292152255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4292152255
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3162429739
Short name T71
Test name
Test status
Simulation time 78831136 ps
CPU time 1 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 209380 kb
Host smart-395f71de-34f5-463f-98c3-d14533378aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162429739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3162429739
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.833446049
Short name T469
Test name
Test status
Simulation time 1660913828 ps
CPU time 12.99 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 218640 kb
Host smart-a535fb25-731c-46c0-b0f9-bbb9f711ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833446049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.833446049
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3560090290
Short name T297
Test name
Test status
Simulation time 478524583 ps
CPU time 5.4 seconds
Started Jun 28 07:43:26 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 217620 kb
Host smart-538c40f0-7d08-46d8-8fab-972ca84197aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560090290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3560090290
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2326563553
Short name T233
Test name
Test status
Simulation time 90359658 ps
CPU time 3.07 seconds
Started Jun 28 07:43:08 PM PDT 24
Finished Jun 28 07:43:14 PM PDT 24
Peak memory 218636 kb
Host smart-6cdd1724-63da-40c4-b0a2-7ee852b336b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326563553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2326563553
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3824209023
Short name T869
Test name
Test status
Simulation time 5814385657 ps
CPU time 10.48 seconds
Started Jun 28 07:43:26 PM PDT 24
Finished Jun 28 07:43:45 PM PDT 24
Peak memory 219992 kb
Host smart-eec0e70e-8b84-4d94-9168-19e8e768536c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824209023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3824209023
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2153893907
Short name T247
Test name
Test status
Simulation time 1545732135 ps
CPU time 15.39 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:53 PM PDT 24
Peak memory 218680 kb
Host smart-a1ee0463-8f4b-4f1e-8680-1c67ec898eb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153893907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2153893907
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2685852797
Short name T841
Test name
Test status
Simulation time 551974512 ps
CPU time 8.75 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:46 PM PDT 24
Peak memory 218600 kb
Host smart-d8236608-c796-487c-b8c1-51a300cb1f8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685852797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2685852797
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.972186793
Short name T818
Test name
Test status
Simulation time 1149922885 ps
CPU time 11.27 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:39 PM PDT 24
Peak memory 226488 kb
Host smart-7490384d-3625-4173-86d9-58d34bb38410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972186793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.972186793
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2633090249
Short name T267
Test name
Test status
Simulation time 164271089 ps
CPU time 2.89 seconds
Started Jun 28 07:43:15 PM PDT 24
Finished Jun 28 07:43:30 PM PDT 24
Peak memory 217872 kb
Host smart-fcf42d8a-2abf-4ac0-bbfa-22581240bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633090249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2633090249
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3740901862
Short name T232
Test name
Test status
Simulation time 2465816276 ps
CPU time 22.93 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:38 PM PDT 24
Peak memory 251404 kb
Host smart-84dfb053-e3c8-4371-850c-61582fb009f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740901862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3740901862
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3802424519
Short name T114
Test name
Test status
Simulation time 54444016 ps
CPU time 5.92 seconds
Started Jun 28 07:43:09 PM PDT 24
Finished Jun 28 07:43:21 PM PDT 24
Peak memory 243148 kb
Host smart-f6bd9d52-28b5-4e49-bf6c-e2c5a4dc346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802424519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3802424519
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.498070739
Short name T553
Test name
Test status
Simulation time 13544439 ps
CPU time 0.83 seconds
Started Jun 28 07:43:16 PM PDT 24
Finished Jun 28 07:43:28 PM PDT 24
Peak memory 209144 kb
Host smart-ad99b040-c016-4d34-b685-6ebee6ce838e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498070739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.498070739
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.75714958
Short name T398
Test name
Test status
Simulation time 76000592 ps
CPU time 1.11 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 209452 kb
Host smart-2f940163-62aa-400a-a35d-e33fa524e3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75714958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.75714958
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3532416058
Short name T788
Test name
Test status
Simulation time 949222581 ps
CPU time 11.28 seconds
Started Jun 28 07:43:31 PM PDT 24
Finished Jun 28 07:43:50 PM PDT 24
Peak memory 226448 kb
Host smart-6d82c9cb-8013-43a7-852f-c818f8b42e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532416058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3532416058
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1083664386
Short name T783
Test name
Test status
Simulation time 719849391 ps
CPU time 8.1 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:43:43 PM PDT 24
Peak memory 217700 kb
Host smart-35af45df-ab0f-4186-a66f-3aa6061765fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083664386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1083664386
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.956836452
Short name T264
Test name
Test status
Simulation time 61973576 ps
CPU time 2.42 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:39 PM PDT 24
Peak memory 222696 kb
Host smart-57f62c34-326f-49af-87fe-38d175d09857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956836452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.956836452
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2083001107
Short name T449
Test name
Test status
Simulation time 208056955 ps
CPU time 7.92 seconds
Started Jun 28 07:43:33 PM PDT 24
Finished Jun 28 07:43:49 PM PDT 24
Peak memory 226444 kb
Host smart-84c7ce42-e9ea-4f91-8a5e-d812eed94e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083001107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2083001107
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.420451293
Short name T500
Test name
Test status
Simulation time 1458347310 ps
CPU time 11.69 seconds
Started Jun 28 07:43:28 PM PDT 24
Finished Jun 28 07:43:47 PM PDT 24
Peak memory 218580 kb
Host smart-7c683643-dad5-4863-aa4d-686b8c101924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420451293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.420451293
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1843676240
Short name T241
Test name
Test status
Simulation time 3001859898 ps
CPU time 14.37 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:52 PM PDT 24
Peak memory 219300 kb
Host smart-2082a4d2-e44b-4e6c-a3f5-8e69a41d8517
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843676240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1843676240
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2340022820
Short name T808
Test name
Test status
Simulation time 351246784 ps
CPU time 13.47 seconds
Started Jun 28 07:43:28 PM PDT 24
Finished Jun 28 07:43:49 PM PDT 24
Peak memory 226448 kb
Host smart-bc3d767f-2d5b-4d27-a4da-50b8203faf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340022820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2340022820
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1087764202
Short name T754
Test name
Test status
Simulation time 852851726 ps
CPU time 3.03 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:43:38 PM PDT 24
Peak memory 215076 kb
Host smart-ce368742-2aa7-4787-8888-87ec6a1b6251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087764202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1087764202
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3581332940
Short name T679
Test name
Test status
Simulation time 822064263 ps
CPU time 18.46 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:56 PM PDT 24
Peak memory 251320 kb
Host smart-7b3d3cf9-06c5-45fd-8aba-6ec483641eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581332940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3581332940
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3378925047
Short name T308
Test name
Test status
Simulation time 100532612 ps
CPU time 7.19 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:43:42 PM PDT 24
Peak memory 250948 kb
Host smart-0609e8a5-a7dc-454d-8d8c-c010060bafa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378925047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3378925047
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3934653188
Short name T438
Test name
Test status
Simulation time 1196496149 ps
CPU time 37.06 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:44:16 PM PDT 24
Peak memory 251308 kb
Host smart-3eced8c1-27a8-44a3-9fd4-6d1855053b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934653188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3934653188
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2268056843
Short name T649
Test name
Test status
Simulation time 34329116 ps
CPU time 0.94 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 212292 kb
Host smart-d99eb186-a173-4792-8383-48ca3de59cd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268056843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2268056843
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3240011210
Short name T488
Test name
Test status
Simulation time 38971211 ps
CPU time 1.02 seconds
Started Jun 28 07:43:31 PM PDT 24
Finished Jun 28 07:43:40 PM PDT 24
Peak memory 209356 kb
Host smart-d3980db8-3f7e-4931-be4c-968e824a8128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240011210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3240011210
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3698998532
Short name T574
Test name
Test status
Simulation time 491408783 ps
CPU time 16.52 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:54 PM PDT 24
Peak memory 218728 kb
Host smart-2d66e9d0-a7f2-4bef-b569-711d2189929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698998532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3698998532
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2489604138
Short name T27
Test name
Test status
Simulation time 1119699475 ps
CPU time 3.91 seconds
Started Jun 28 07:43:26 PM PDT 24
Finished Jun 28 07:43:38 PM PDT 24
Peak memory 217848 kb
Host smart-f55e4fae-2447-4d3f-b1d0-103944bae453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489604138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2489604138
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3052671949
Short name T256
Test name
Test status
Simulation time 39588280 ps
CPU time 2.16 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:43:37 PM PDT 24
Peak memory 218636 kb
Host smart-f774fa2b-bef1-44b0-a0f6-8803c57fd761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052671949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3052671949
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1158791874
Short name T830
Test name
Test status
Simulation time 279465020 ps
CPU time 12.1 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:49 PM PDT 24
Peak memory 226440 kb
Host smart-94cdb920-4101-4c1c-bbb6-7068eae8a2db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158791874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1158791874
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1233141780
Short name T254
Test name
Test status
Simulation time 1348545806 ps
CPU time 24.62 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:44:01 PM PDT 24
Peak memory 218628 kb
Host smart-1eefd488-23ad-42bc-aa90-590848b26271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233141780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1233141780
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.815230751
Short name T777
Test name
Test status
Simulation time 325588791 ps
CPU time 11.03 seconds
Started Jun 28 07:43:28 PM PDT 24
Finished Jun 28 07:43:47 PM PDT 24
Peak memory 218604 kb
Host smart-a3d935e1-9e26-47c5-8880-b88ec0a52170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815230751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.815230751
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1936066393
Short name T686
Test name
Test status
Simulation time 934823658 ps
CPU time 10.15 seconds
Started Jun 28 07:43:30 PM PDT 24
Finished Jun 28 07:43:48 PM PDT 24
Peak memory 218700 kb
Host smart-60982b8f-251c-4bc9-b6cb-fd81547f362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936066393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1936066393
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4000488104
Short name T712
Test name
Test status
Simulation time 56853720 ps
CPU time 1.28 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:43:38 PM PDT 24
Peak memory 218056 kb
Host smart-e3f3ed3b-c49b-456e-9dac-009cccb3b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000488104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4000488104
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3141941404
Short name T485
Test name
Test status
Simulation time 1519957493 ps
CPU time 27.33 seconds
Started Jun 28 07:43:29 PM PDT 24
Finished Jun 28 07:44:04 PM PDT 24
Peak memory 251340 kb
Host smart-66d52096-e381-49a5-8130-8b324ea4a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141941404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3141941404
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3903297709
Short name T781
Test name
Test status
Simulation time 328326625 ps
CPU time 6.84 seconds
Started Jun 28 07:43:32 PM PDT 24
Finished Jun 28 07:43:47 PM PDT 24
Peak memory 250768 kb
Host smart-68b52840-3ac0-4613-b7d8-47a77a9eb322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903297709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3903297709
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2408483021
Short name T56
Test name
Test status
Simulation time 14475620489 ps
CPU time 47.04 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:44:22 PM PDT 24
Peak memory 279700 kb
Host smart-29fa3fd0-eda3-4ad1-871c-a117cc490ad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408483021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2408483021
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.497445272
Short name T166
Test name
Test status
Simulation time 101770578468 ps
CPU time 797.7 seconds
Started Jun 28 07:43:28 PM PDT 24
Finished Jun 28 07:56:54 PM PDT 24
Peak memory 333428 kb
Host smart-9638ff4d-06ff-4848-b39d-bd5cb06d7546
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=497445272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.497445272
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3854216002
Short name T311
Test name
Test status
Simulation time 29517682 ps
CPU time 0.82 seconds
Started Jun 28 07:43:27 PM PDT 24
Finished Jun 28 07:43:35 PM PDT 24
Peak memory 209448 kb
Host smart-29da2e1a-7cc8-47ec-9232-bd8c4e16176a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854216002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3854216002
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2417066418
Short name T383
Test name
Test status
Simulation time 13394891 ps
CPU time 1.05 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:24 PM PDT 24
Peak memory 209364 kb
Host smart-5275de1d-f48c-473e-baa7-a0e12798f958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417066418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2417066418
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.985530476
Short name T316
Test name
Test status
Simulation time 42531442 ps
CPU time 0.79 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:21 PM PDT 24
Peak memory 209320 kb
Host smart-875c28d4-4e57-44cc-9a2d-0c3ed23e0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985530476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.985530476
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.494515161
Short name T862
Test name
Test status
Simulation time 604076744 ps
CPU time 11.39 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:31 PM PDT 24
Peak memory 226392 kb
Host smart-e9e22dd8-f869-4955-a305-45590e77ba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494515161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.494515161
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1190436828
Short name T487
Test name
Test status
Simulation time 340328374 ps
CPU time 9.71 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:32 PM PDT 24
Peak memory 217836 kb
Host smart-caf9bdcc-4b06-4cdc-b604-584daaed09a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190436828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1190436828
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1731092751
Short name T87
Test name
Test status
Simulation time 2154850148 ps
CPU time 48.48 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:41:21 PM PDT 24
Peak memory 218640 kb
Host smart-2885ebe2-137a-4941-8049-e059720dc5f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731092751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1731092751
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1042330469
Short name T508
Test name
Test status
Simulation time 590195564 ps
CPU time 15.47 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:39 PM PDT 24
Peak memory 218128 kb
Host smart-4d6962fe-4293-4e6f-a092-cd643af5a2d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042330469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
042330469
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2791479845
Short name T213
Test name
Test status
Simulation time 1430048351 ps
CPU time 12.76 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 223328 kb
Host smart-62524cb0-8df9-4309-aef4-b7ff5d64e958
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791479845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2791479845
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3386784434
Short name T547
Test name
Test status
Simulation time 5934603828 ps
CPU time 13.88 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:31 PM PDT 24
Peak memory 218052 kb
Host smart-39f12b05-9db8-42ca-a32a-9dcd99d51d09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386784434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3386784434
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3782998347
Short name T597
Test name
Test status
Simulation time 969056838 ps
CPU time 4.19 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:22 PM PDT 24
Peak memory 218068 kb
Host smart-327cbe17-6764-4b0e-933a-80af19e105be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782998347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3782998347
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2790014767
Short name T181
Test name
Test status
Simulation time 1517463255 ps
CPU time 49.75 seconds
Started Jun 28 07:40:09 PM PDT 24
Finished Jun 28 07:41:17 PM PDT 24
Peak memory 251208 kb
Host smart-ff0a99a2-2518-49a0-ad58-0a7526fd71f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790014767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2790014767
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2131238940
Short name T802
Test name
Test status
Simulation time 349716202 ps
CPU time 11.94 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 251244 kb
Host smart-bf896e52-8f7f-4e1f-b173-0bb195421b7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131238940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2131238940
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2162222240
Short name T112
Test name
Test status
Simulation time 35197222 ps
CPU time 2.27 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 218552 kb
Host smart-7fc50671-5200-449c-a555-7c4834a6b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162222240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2162222240
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3383475594
Short name T76
Test name
Test status
Simulation time 243578365 ps
CPU time 10.12 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:42 PM PDT 24
Peak memory 218072 kb
Host smart-1c865a91-e18d-479d-a4d6-035654892a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383475594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3383475594
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2305740541
Short name T576
Test name
Test status
Simulation time 379313504 ps
CPU time 12.19 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 226272 kb
Host smart-071a635c-ac8f-47ae-994e-1edd618778b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305740541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2305740541
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2635561080
Short name T266
Test name
Test status
Simulation time 882728212 ps
CPU time 7.95 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:31 PM PDT 24
Peak memory 218604 kb
Host smart-233cd979-208e-46ec-ad79-f54ca25a6369
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635561080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2635561080
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2327721141
Short name T237
Test name
Test status
Simulation time 523864900 ps
CPU time 6.35 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:39 PM PDT 24
Peak memory 218512 kb
Host smart-cf628c42-7e3f-4aa7-9fe0-a3cc1ad7a90e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327721141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
327721141
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2175694265
Short name T53
Test name
Test status
Simulation time 317857236 ps
CPU time 7.84 seconds
Started Jun 28 07:40:06 PM PDT 24
Finished Jun 28 07:40:25 PM PDT 24
Peak memory 225852 kb
Host smart-69ed1cf4-7541-408b-ac34-cd6ee6cac114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175694265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2175694265
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.636562160
Short name T372
Test name
Test status
Simulation time 115955376 ps
CPU time 6.23 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:26 PM PDT 24
Peak memory 218052 kb
Host smart-7f551d60-ac1a-4725-a9ef-0bdf33a9a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636562160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.636562160
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3579557854
Short name T612
Test name
Test status
Simulation time 1545570193 ps
CPU time 33.23 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:56 PM PDT 24
Peak memory 251324 kb
Host smart-5512ae77-b7c3-4115-8af5-1ed4bf01ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579557854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3579557854
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1933098638
Short name T637
Test name
Test status
Simulation time 82469628 ps
CPU time 6.55 seconds
Started Jun 28 07:40:07 PM PDT 24
Finished Jun 28 07:40:27 PM PDT 24
Peak memory 244768 kb
Host smart-64d6c218-4bc5-49a9-a7d6-c6195631e85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933098638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1933098638
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3484264249
Short name T107
Test name
Test status
Simulation time 13560118 ps
CPU time 0.98 seconds
Started Jun 28 07:40:05 PM PDT 24
Finished Jun 28 07:40:16 PM PDT 24
Peak memory 212300 kb
Host smart-d634e0b2-c2dd-49d9-b888-4aa808d9b9b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484264249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3484264249
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3220230314
Short name T814
Test name
Test status
Simulation time 66436169 ps
CPU time 1.04 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:40:43 PM PDT 24
Peak memory 209468 kb
Host smart-c6297baf-12dd-4ca6-8997-c5f5987b1858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220230314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3220230314
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2299767878
Short name T258
Test name
Test status
Simulation time 30456182 ps
CPU time 0.9 seconds
Started Jun 28 07:40:09 PM PDT 24
Finished Jun 28 07:40:28 PM PDT 24
Peak memory 209200 kb
Host smart-f6e6e7fa-c714-476e-bbd6-18ebaafa3384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299767878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2299767878
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2873133294
Short name T840
Test name
Test status
Simulation time 1246312902 ps
CPU time 18.26 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:53 PM PDT 24
Peak memory 218588 kb
Host smart-9f6b1f3e-8c97-40ea-9380-87e88688ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873133294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2873133294
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1031990481
Short name T24
Test name
Test status
Simulation time 3857414570 ps
CPU time 6.26 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:40:41 PM PDT 24
Peak memory 218204 kb
Host smart-7510d508-902e-4cd8-84c2-87df987ee21a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031990481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1031990481
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.421198630
Short name T481
Test name
Test status
Simulation time 2668321115 ps
CPU time 43.26 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:41:18 PM PDT 24
Peak memory 219552 kb
Host smart-5ecdc28b-3f36-437c-aced-3b458283d726
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421198630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.421198630
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2020563112
Short name T456
Test name
Test status
Simulation time 633689130 ps
CPU time 2.99 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 218108 kb
Host smart-007e99db-a34a-449d-bc2f-38f3e46ed0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020563112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
020563112
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3856728054
Short name T715
Test name
Test status
Simulation time 154251769 ps
CPU time 5.34 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 218716 kb
Host smart-798df154-4b10-49f1-be9b-20ee6388632d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856728054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3856728054
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3666194177
Short name T563
Test name
Test status
Simulation time 872913959 ps
CPU time 22.69 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:41:03 PM PDT 24
Peak memory 218008 kb
Host smart-b669295f-e495-4ed8-940a-a93010f2aff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666194177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3666194177
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1053635189
Short name T614
Test name
Test status
Simulation time 986161879 ps
CPU time 5.96 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:39 PM PDT 24
Peak memory 217992 kb
Host smart-cf50d355-f86d-433a-a98c-a934e44d4f2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053635189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1053635189
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4203671232
Short name T613
Test name
Test status
Simulation time 1436238590 ps
CPU time 59.4 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:41:32 PM PDT 24
Peak memory 268692 kb
Host smart-9b25a4e6-f702-4e12-94d4-150a04852bdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203671232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4203671232
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2412727036
Short name T265
Test name
Test status
Simulation time 4316332012 ps
CPU time 25.99 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:41:01 PM PDT 24
Peak memory 248200 kb
Host smart-6f3d6821-41ff-4bc6-a62c-4e28b9fcd715
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412727036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2412727036
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2983164596
Short name T698
Test name
Test status
Simulation time 143593811 ps
CPU time 2.29 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 222476 kb
Host smart-0213be5f-3975-4a28-9d51-ea992387e054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983164596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2983164596
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2689629875
Short name T769
Test name
Test status
Simulation time 1133912853 ps
CPU time 7.13 seconds
Started Jun 28 07:40:09 PM PDT 24
Finished Jun 28 07:40:34 PM PDT 24
Peak memory 218000 kb
Host smart-d7fa0217-fce3-4cae-9c9f-805b447d3905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689629875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2689629875
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3638317923
Short name T544
Test name
Test status
Simulation time 322184450 ps
CPU time 11.21 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 218788 kb
Host smart-987e0226-a2e3-424a-81cb-a2d5699b4e74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638317923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3638317923
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2746791361
Short name T235
Test name
Test status
Simulation time 7233692741 ps
CPU time 13.98 seconds
Started Jun 28 07:40:18 PM PDT 24
Finished Jun 28 07:40:58 PM PDT 24
Peak memory 218748 kb
Host smart-df8e3a73-2867-4ce4-be87-91a4240055cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746791361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2746791361
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3088138330
Short name T224
Test name
Test status
Simulation time 558628228 ps
CPU time 12.9 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:40:55 PM PDT 24
Peak memory 226404 kb
Host smart-e6dd04f3-816a-48de-8181-f69a78756a2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088138330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
088138330
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.263274756
Short name T721
Test name
Test status
Simulation time 1376067307 ps
CPU time 8.87 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:32 PM PDT 24
Peak memory 218704 kb
Host smart-09d82d5b-989b-40a5-b492-3d6731d746ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263274756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.263274756
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1878205148
Short name T269
Test name
Test status
Simulation time 264326291 ps
CPU time 5.43 seconds
Started Jun 28 07:40:05 PM PDT 24
Finished Jun 28 07:40:20 PM PDT 24
Peak memory 218056 kb
Host smart-704b8315-fb4d-4734-a092-1a24b5dfa4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878205148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1878205148
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2922429152
Short name T587
Test name
Test status
Simulation time 186962879 ps
CPU time 20.39 seconds
Started Jun 28 07:40:13 PM PDT 24
Finished Jun 28 07:40:56 PM PDT 24
Peak memory 251364 kb
Host smart-b0cdb9e3-50e6-4660-91fd-4ebc6852bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922429152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2922429152
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3786299714
Short name T794
Test name
Test status
Simulation time 202820569 ps
CPU time 3.34 seconds
Started Jun 28 07:40:13 PM PDT 24
Finished Jun 28 07:40:39 PM PDT 24
Peak memory 218308 kb
Host smart-7ded9c13-4b12-48fa-a008-d4a8abd5177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786299714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3786299714
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2178588500
Short name T842
Test name
Test status
Simulation time 4575574674 ps
CPU time 130.91 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:42:53 PM PDT 24
Peak memory 284184 kb
Host smart-907ec7b6-a73d-44a3-89cf-f4525a898795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178588500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2178588500
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1577251741
Short name T172
Test name
Test status
Simulation time 16922871063 ps
CPU time 441.41 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:48:05 PM PDT 24
Peak memory 284296 kb
Host smart-0ede3ce1-ee2d-4817-81ff-76c4fc7323d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1577251741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1577251741
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1913868861
Short name T38
Test name
Test status
Simulation time 46139460 ps
CPU time 0.94 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:31 PM PDT 24
Peak memory 213260 kb
Host smart-00225a64-480d-4aca-a5d1-aa82b9e185dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913868861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1913868861
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2192298179
Short name T106
Test name
Test status
Simulation time 62370471 ps
CPU time 1.13 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:33 PM PDT 24
Peak memory 209448 kb
Host smart-afd1e4d2-eafe-4e4f-89b5-89b3044fb2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192298179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2192298179
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.526536474
Short name T201
Test name
Test status
Simulation time 13494884 ps
CPU time 0.97 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:53 PM PDT 24
Peak memory 209304 kb
Host smart-132b1fd0-8684-42c8-a449-f18db35eaced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526536474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.526536474
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1714768374
Short name T41
Test name
Test status
Simulation time 236815818 ps
CPU time 7.98 seconds
Started Jun 28 07:40:22 PM PDT 24
Finished Jun 28 07:41:00 PM PDT 24
Peak memory 226440 kb
Host smart-63c81380-c134-4bd8-91c4-01cde8ea0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714768374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1714768374
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1489725668
Short name T779
Test name
Test status
Simulation time 313925220 ps
CPU time 1.49 seconds
Started Jun 28 07:40:24 PM PDT 24
Finished Jun 28 07:40:54 PM PDT 24
Peak memory 217516 kb
Host smart-554b3a92-0991-4c9f-9c3b-0a0727b61d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489725668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1489725668
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.386887014
Short name T532
Test name
Test status
Simulation time 2273129002 ps
CPU time 34.91 seconds
Started Jun 28 07:40:20 PM PDT 24
Finished Jun 28 07:41:22 PM PDT 24
Peak memory 218700 kb
Host smart-69c8e1d9-ab70-431b-a362-c6d90b0b1a2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386887014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.386887014
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.808682755
Short name T386
Test name
Test status
Simulation time 511507645 ps
CPU time 11.76 seconds
Started Jun 28 07:40:25 PM PDT 24
Finished Jun 28 07:41:04 PM PDT 24
Peak memory 217856 kb
Host smart-2c0ef92d-4d9c-410c-91ef-e81a500c8f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808682755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.808682755
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1973742470
Short name T774
Test name
Test status
Simulation time 276376914 ps
CPU time 7.99 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:00 PM PDT 24
Peak memory 218520 kb
Host smart-c202a445-014e-4803-9fb8-f44d9a1ff7f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973742470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1973742470
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3375205190
Short name T412
Test name
Test status
Simulation time 2784873398 ps
CPU time 19.77 seconds
Started Jun 28 07:40:20 PM PDT 24
Finished Jun 28 07:41:07 PM PDT 24
Peak memory 218036 kb
Host smart-8fc0b759-e663-46a3-bb0d-07a10b7cc237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375205190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3375205190
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2638280950
Short name T406
Test name
Test status
Simulation time 411822191 ps
CPU time 3.63 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:56 PM PDT 24
Peak memory 217988 kb
Host smart-68f2bb23-0927-477a-a6a5-4b827ec164d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638280950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2638280950
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1625315165
Short name T605
Test name
Test status
Simulation time 13669536325 ps
CPU time 79.69 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 268400 kb
Host smart-1407d4e0-e060-485d-bff1-33c4f6b21d58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625315165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1625315165
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3246598318
Short name T747
Test name
Test status
Simulation time 290825078 ps
CPU time 9.68 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:02 PM PDT 24
Peak memory 246812 kb
Host smart-f1c948e6-3a3c-4c1f-b40d-56f6b9e24517
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246598318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3246598318
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.348128762
Short name T857
Test name
Test status
Simulation time 113644913 ps
CPU time 2.26 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:54 PM PDT 24
Peak memory 218648 kb
Host smart-fdfed8e7-3d65-47fc-8250-dcaa40fae195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348128762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.348128762
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1852823784
Short name T489
Test name
Test status
Simulation time 1474684632 ps
CPU time 20.09 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:12 PM PDT 24
Peak memory 217812 kb
Host smart-e3f53a96-2e5a-45fd-b664-6b3e6a4a0cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852823784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1852823784
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2424235174
Short name T511
Test name
Test status
Simulation time 1025678805 ps
CPU time 13.17 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:41:03 PM PDT 24
Peak memory 226516 kb
Host smart-beb2d7b5-e6b5-41a5-9650-bd6ae841e00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424235174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2424235174
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1488139642
Short name T322
Test name
Test status
Simulation time 388476569 ps
CPU time 10.01 seconds
Started Jun 28 07:40:25 PM PDT 24
Finished Jun 28 07:41:03 PM PDT 24
Peak memory 218444 kb
Host smart-13973a05-aabc-4096-a4c3-7138f611280d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488139642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1488139642
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3239987738
Short name T410
Test name
Test status
Simulation time 841476069 ps
CPU time 9.15 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:59 PM PDT 24
Peak memory 218444 kb
Host smart-cacd54fe-248f-4c7a-bee5-e9de8da3568b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239987738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
239987738
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1205721368
Short name T619
Test name
Test status
Simulation time 366009614 ps
CPU time 7.98 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:58 PM PDT 24
Peak memory 226440 kb
Host smart-64a29685-ca2f-4973-b930-e8370cba483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205721368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1205721368
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2549683871
Short name T58
Test name
Test status
Simulation time 36616509 ps
CPU time 2.33 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 218060 kb
Host smart-e3ef59a2-927e-42b5-a20f-4effd2e00d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549683871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2549683871
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3131891399
Short name T645
Test name
Test status
Simulation time 227927480 ps
CPU time 18.13 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:10 PM PDT 24
Peak memory 251328 kb
Host smart-e2beaa15-d8a8-4e3d-b053-70630eb580f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131891399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3131891399
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1300032741
Short name T688
Test name
Test status
Simulation time 312025460 ps
CPU time 8.33 seconds
Started Jun 28 07:40:22 PM PDT 24
Finished Jun 28 07:40:58 PM PDT 24
Peak memory 251324 kb
Host smart-c3c393ce-232c-4bcb-ad20-26c4aefd1b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300032741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1300032741
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4276444547
Short name T817
Test name
Test status
Simulation time 1102218938 ps
CPU time 29.62 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 251332 kb
Host smart-4df39474-e72b-4b84-b0c4-b3b7be45a23a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276444547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4276444547
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4182379936
Short name T165
Test name
Test status
Simulation time 17058304085 ps
CPU time 258.15 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:45:02 PM PDT 24
Peak memory 287124 kb
Host smart-21bdabf3-d4a4-4204-99a2-cf5b65bcdaa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4182379936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4182379936
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.418010221
Short name T37
Test name
Test status
Simulation time 22373151 ps
CPU time 1.03 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:51 PM PDT 24
Peak memory 213200 kb
Host smart-0f340e43-1f99-409a-9625-31e84f0ce0d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418010221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.418010221
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1120485129
Short name T655
Test name
Test status
Simulation time 19870092 ps
CPU time 1.11 seconds
Started Jun 28 07:40:19 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 209424 kb
Host smart-4b02b407-b2ae-4603-a6e5-aea5a5006699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120485129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1120485129
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.539053367
Short name T351
Test name
Test status
Simulation time 16783310 ps
CPU time 0.94 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 209376 kb
Host smart-f853c5ef-a13c-4052-8eab-6fa710992fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539053367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.539053367
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1549535743
Short name T16
Test name
Test status
Simulation time 1399885117 ps
CPU time 13.22 seconds
Started Jun 28 07:40:13 PM PDT 24
Finished Jun 28 07:40:49 PM PDT 24
Peak memory 226196 kb
Host smart-f9d30d02-7e3f-4eaf-8fd3-f313c9dd4114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549535743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1549535743
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.939458371
Short name T184
Test name
Test status
Simulation time 181205314 ps
CPU time 3.04 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 217204 kb
Host smart-0be0d097-7fb8-4557-9b45-3bf79282e11b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939458371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.939458371
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2259480567
Short name T180
Test name
Test status
Simulation time 5799081280 ps
CPU time 44.56 seconds
Started Jun 28 07:40:13 PM PDT 24
Finished Jun 28 07:41:20 PM PDT 24
Peak memory 218636 kb
Host smart-483e16da-0592-4a3d-99e6-c2b96008cc0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259480567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2259480567
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1189541868
Short name T319
Test name
Test status
Simulation time 344197168 ps
CPU time 4.08 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 217864 kb
Host smart-126069a7-3c09-46df-96d0-d21a333c376a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189541868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
189541868
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1214988002
Short name T212
Test name
Test status
Simulation time 791881776 ps
CPU time 20.9 seconds
Started Jun 28 07:40:08 PM PDT 24
Finished Jun 28 07:40:46 PM PDT 24
Peak memory 218584 kb
Host smart-05bde36a-378d-457f-9297-eb09b1f7878a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214988002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1214988002
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.861679987
Short name T433
Test name
Test status
Simulation time 2981388662 ps
CPU time 22.04 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 07:40:55 PM PDT 24
Peak memory 218000 kb
Host smart-c01c8b3e-ee3c-49c1-bed5-e6328b609bcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861679987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.861679987
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3745911571
Short name T636
Test name
Test status
Simulation time 540802169 ps
CPU time 4.79 seconds
Started Jun 28 07:40:10 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 217988 kb
Host smart-8bd8d3cb-dd4a-4e39-8da2-0f4b890e7dc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745911571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3745911571
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.95059512
Short name T845
Test name
Test status
Simulation time 2620784054 ps
CPU time 60.81 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:41:42 PM PDT 24
Peak memory 267856 kb
Host smart-f9a6c9bc-4d8b-4cbe-a6ad-30d456aba562
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95059512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
state_failure.95059512
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1449841189
Short name T427
Test name
Test status
Simulation time 23751432 ps
CPU time 1.88 seconds
Started Jun 28 07:40:24 PM PDT 24
Finished Jun 28 07:40:55 PM PDT 24
Peak memory 218628 kb
Host smart-16a508b5-7227-4a76-a87b-67eea3d3cb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449841189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1449841189
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1409983180
Short name T719
Test name
Test status
Simulation time 954408705 ps
CPU time 9.68 seconds
Started Jun 28 07:40:09 PM PDT 24
Finished Jun 28 07:40:37 PM PDT 24
Peak memory 214880 kb
Host smart-7fc4ec1b-92c8-4132-8e7b-83264de6797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409983180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1409983180
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2124926453
Short name T248
Test name
Test status
Simulation time 1092459975 ps
CPU time 12.03 seconds
Started Jun 28 07:40:12 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 226448 kb
Host smart-10e650f9-8c01-47b7-83ec-a4ba37da6c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124926453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2124926453
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3926863029
Short name T55
Test name
Test status
Simulation time 662824773 ps
CPU time 15.8 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:40:56 PM PDT 24
Peak memory 218732 kb
Host smart-b655096c-2559-4021-8634-a80eb03d95b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926863029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3926863029
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3677445531
Short name T680
Test name
Test status
Simulation time 297856624 ps
CPU time 8.63 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:40:50 PM PDT 24
Peak memory 218720 kb
Host smart-e263e185-27d5-4d59-9a6b-f9ab4a978b9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677445531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
677445531
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3811483307
Short name T728
Test name
Test status
Simulation time 1103266750 ps
CPU time 11.43 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 226572 kb
Host smart-149a2558-da94-4643-9f04-7bec6164ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811483307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3811483307
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3156549423
Short name T177
Test name
Test status
Simulation time 174841291 ps
CPU time 2.74 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:40:45 PM PDT 24
Peak memory 214496 kb
Host smart-0841ba5b-da3f-413f-bed4-cc0542ba7141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156549423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3156549423
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.915563854
Short name T630
Test name
Test status
Simulation time 1311902161 ps
CPU time 29.07 seconds
Started Jun 28 07:40:16 PM PDT 24
Finished Jun 28 07:41:11 PM PDT 24
Peak memory 251080 kb
Host smart-ab392c06-7091-4b97-a2bd-5a4a593580b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915563854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.915563854
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2316713811
Short name T835
Test name
Test status
Simulation time 575124834 ps
CPU time 8.46 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:01 PM PDT 24
Peak memory 251340 kb
Host smart-ebdfb095-a1b5-4735-ac6d-806be92fd7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316713811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2316713811
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1145721785
Short name T832
Test name
Test status
Simulation time 26828388589 ps
CPU time 805.31 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:54:06 PM PDT 24
Peak memory 251132 kb
Host smart-63119a9b-5915-476b-bd8e-d0c507917e73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145721785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1145721785
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3978628815
Short name T117
Test name
Test status
Simulation time 94032144951 ps
CPU time 8426.24 seconds
Started Jun 28 07:40:11 PM PDT 24
Finished Jun 28 10:01:01 PM PDT 24
Peak memory 1626156 kb
Host smart-9663ed1a-826d-411e-9453-bf25dec35c20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3978628815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3978628815
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2407619545
Short name T342
Test name
Test status
Simulation time 38922812 ps
CPU time 0.87 seconds
Started Jun 28 07:40:25 PM PDT 24
Finished Jun 28 07:40:54 PM PDT 24
Peak memory 209240 kb
Host smart-dc1eabfe-a004-455a-a531-66e2ac64af5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407619545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2407619545
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2012030653
Short name T620
Test name
Test status
Simulation time 25824877 ps
CPU time 1.14 seconds
Started Jun 28 07:40:20 PM PDT 24
Finished Jun 28 07:40:48 PM PDT 24
Peak memory 209380 kb
Host smart-f8a04abf-e7b8-4cec-8392-084cdafc727b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012030653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2012030653
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2870982239
Short name T202
Test name
Test status
Simulation time 13762279 ps
CPU time 0.86 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:51 PM PDT 24
Peak memory 209092 kb
Host smart-0bfaae41-7054-4a95-a3d1-02302d8f0dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870982239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2870982239
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2360256806
Short name T626
Test name
Test status
Simulation time 291144992 ps
CPU time 12.31 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:40:56 PM PDT 24
Peak memory 218664 kb
Host smart-18412ca1-60b4-4a46-916e-4a8b4686bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360256806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2360256806
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1487528132
Short name T108
Test name
Test status
Simulation time 1987086373 ps
CPU time 4.69 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:55 PM PDT 24
Peak memory 217504 kb
Host smart-77d50531-fc94-4d2b-860e-34d95512f33d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487528132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1487528132
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3685218236
Short name T252
Test name
Test status
Simulation time 3239361973 ps
CPU time 47.74 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:40 PM PDT 24
Peak memory 219284 kb
Host smart-e1e5fb00-a4c3-4398-8294-3bb962c40390
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685218236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3685218236
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.508275927
Short name T320
Test name
Test status
Simulation time 448857457 ps
CPU time 2.04 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:54 PM PDT 24
Peak memory 217816 kb
Host smart-d15305ec-c26e-414d-9358-7b499768ae75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508275927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.508275927
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2770763328
Short name T535
Test name
Test status
Simulation time 473921972 ps
CPU time 6.32 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:59 PM PDT 24
Peak memory 218564 kb
Host smart-b9ef45d7-1ded-44e0-8a57-448e051e6a14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770763328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2770763328
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3024205870
Short name T749
Test name
Test status
Simulation time 5284327843 ps
CPU time 21.9 seconds
Started Jun 28 07:40:24 PM PDT 24
Finished Jun 28 07:41:15 PM PDT 24
Peak memory 218052 kb
Host smart-f8412425-273d-4722-b7c6-49b0789bf86c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024205870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3024205870
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.353911632
Short name T824
Test name
Test status
Simulation time 293229732 ps
CPU time 4.39 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:40:57 PM PDT 24
Peak memory 217992 kb
Host smart-77c3e796-d937-4f0f-8eb7-9bea05d09f08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353911632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.353911632
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3990808136
Short name T690
Test name
Test status
Simulation time 3940185063 ps
CPU time 63.82 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:56 PM PDT 24
Peak memory 284088 kb
Host smart-4ab9f558-ee51-4040-983e-8787307b9e06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990808136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3990808136
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2899458911
Short name T215
Test name
Test status
Simulation time 935989688 ps
CPU time 15.21 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:07 PM PDT 24
Peak memory 250928 kb
Host smart-ef1aa3fd-92f1-4ed3-93b7-d0573e86b950
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899458911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2899458911
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3521435474
Short name T603
Test name
Test status
Simulation time 62750450 ps
CPU time 2.41 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:40:43 PM PDT 24
Peak memory 218460 kb
Host smart-1a14a385-43bc-4568-bc73-b986e3482387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521435474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3521435474
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3742085199
Short name T850
Test name
Test status
Simulation time 716837046 ps
CPU time 12.24 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:41:02 PM PDT 24
Peak memory 218060 kb
Host smart-162f53e4-1cb8-4d78-9227-cdbc552a6ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742085199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3742085199
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1725808468
Short name T868
Test name
Test status
Simulation time 362877157 ps
CPU time 14.96 seconds
Started Jun 28 07:40:23 PM PDT 24
Finished Jun 28 07:41:07 PM PDT 24
Peak memory 219216 kb
Host smart-ecb0043b-4b29-4792-916c-9f640e75c4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725808468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1725808468
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2936507569
Short name T219
Test name
Test status
Simulation time 458481313 ps
CPU time 16.56 seconds
Started Jun 28 07:40:24 PM PDT 24
Finished Jun 28 07:41:09 PM PDT 24
Peak memory 218520 kb
Host smart-ac7aac98-dfd4-4507-82b7-86ac1a904e52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936507569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2936507569
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3576476789
Short name T348
Test name
Test status
Simulation time 3201657211 ps
CPU time 13.28 seconds
Started Jun 28 07:40:20 PM PDT 24
Finished Jun 28 07:41:00 PM PDT 24
Peak memory 218636 kb
Host smart-467fba52-6c0b-477d-87a1-c4d326941fd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576476789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
576476789
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1974819432
Short name T581
Test name
Test status
Simulation time 825302286 ps
CPU time 6.98 seconds
Started Jun 28 07:40:15 PM PDT 24
Finished Jun 28 07:40:47 PM PDT 24
Peak memory 218720 kb
Host smart-8e6d1536-6db3-403c-9a58-e79db12394fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974819432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1974819432
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2508169054
Short name T476
Test name
Test status
Simulation time 185247845 ps
CPU time 2.06 seconds
Started Jun 28 07:40:21 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 214920 kb
Host smart-080f8efb-a818-4389-9b6b-820ee754c733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508169054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2508169054
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1749090381
Short name T608
Test name
Test status
Simulation time 888920000 ps
CPU time 25.7 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:41:08 PM PDT 24
Peak memory 246592 kb
Host smart-29c32058-dba7-418a-98ee-5d9acc20f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749090381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1749090381
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.245128160
Short name T344
Test name
Test status
Simulation time 59226678 ps
CPU time 6.83 seconds
Started Jun 28 07:40:18 PM PDT 24
Finished Jun 28 07:40:52 PM PDT 24
Peak memory 251344 kb
Host smart-b9c141fa-92a5-42de-bb40-f49533acfd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245128160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.245128160
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1765023748
Short name T116
Test name
Test status
Simulation time 6441514998 ps
CPU time 157.79 seconds
Started Jun 28 07:40:17 PM PDT 24
Finished Jun 28 07:43:20 PM PDT 24
Peak memory 333352 kb
Host smart-fa53aa9b-6bf3-43f1-b764-fa1d008670bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765023748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1765023748
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1559449753
Short name T502
Test name
Test status
Simulation time 48259982 ps
CPU time 0.86 seconds
Started Jun 28 07:40:18 PM PDT 24
Finished Jun 28 07:40:45 PM PDT 24
Peak memory 212316 kb
Host smart-2ed2354e-879b-40e2-8948-f1b12336bd15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559449753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1559449753
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%