Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1191137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1409303

1

T3

15

T8

13

T4

305

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2254505	1			T3	16		T8	80		T4	300
values[0x0]	172728	1			T3	10		T8	8		T4	103
values[0x1]	173207	1			T3	4		T8	8		T4	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	943699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1656741

1

T3

19

T8

43

T4

351

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10861	1			T4	1		T12	49		T14	136
valid_sources[0x01]	8668	1			T4	1		T12	43		T14	152
valid_sources[0x02]	7340	1			T4	5		T10	2		T12	55
valid_sources[0x03]	10277	1			T4	1		T6	18		T12	34
valid_sources[0x04]	7535	1			T4	2		T10	1		T12	32
valid_sources[0x05]	7229	1			T10	5		T11	17		T12	46
valid_sources[0x06]	7604	1			T10	1		T12	32		T14	178
valid_sources[0x07]	7274	1			T4	1		T10	5		T12	32
valid_sources[0x08]	14273	1			T4	3		T10	3		T12	44
valid_sources[0x09]	7440	1			T4	6		T10	7		T12	42
valid_sources[0x0a]	7496	1			T4	7		T5	31		T12	57
valid_sources[0x0b]	8600	1			T4	4		T12	36		T13	1
valid_sources[0x0c]	8847	1			T3	1		T10	5		T12	52
valid_sources[0x0d]	9596	1			T4	4		T10	6		T12	37
valid_sources[0x0e]	7512	1			T12	40		T14	146		T15	3
valid_sources[0x0f]	8514	1			T4	1		T10	4		T6	3
valid_sources[0x10]	7506	1			T3	1		T10	3		T6	11
valid_sources[0x11]	7692	1			T4	1		T10	1		T12	47
valid_sources[0x12]	7428	1			T4	2		T10	2		T6	4
valid_sources[0x13]	10695	1			T4	5		T5	19		T12	43
valid_sources[0x14]	8308	1			T10	2		T12	46		T14	148
valid_sources[0x15]	26229	1			T4	6		T10	2		T12	43
valid_sources[0x16]	10057	1			T3	2		T4	2		T10	2
valid_sources[0x17]	10343	1			T10	2		T12	45		T13	6
valid_sources[0x18]	7410	1			T4	3		T6	36		T12	41
valid_sources[0x19]	7305	1			T4	1		T12	37		T13	2
valid_sources[0x1a]	7389	1			T6	3		T12	34		T13	6
valid_sources[0x1b]	7835	1			T10	1		T11	17		T12	39
valid_sources[0x1c]	7477	1			T4	2		T10	3		T12	48
valid_sources[0x1d]	7765	1			T10	1		T12	42		T14	150
valid_sources[0x1e]	7651	1			T4	2		T10	3		T5	1
valid_sources[0x1f]	8210	1			T4	1		T10	1		T12	48
valid_sources[0x20]	7854	1			T4	4		T10	2		T12	53
valid_sources[0x21]	48658	1			T10	2		T12	38		T13	2
valid_sources[0x22]	7765	1			T4	3		T10	2		T12	41
valid_sources[0x23]	7395	1			T4	2		T10	5		T12	46
valid_sources[0x24]	14866	1			T4	2		T10	5		T12	46
valid_sources[0x25]	12766	1			T4	2		T10	2		T12	37
valid_sources[0x26]	7893	1			T4	5		T10	1		T12	43
valid_sources[0x27]	7533	1			T10	2		T12	43		T14	118
valid_sources[0x28]	7715	1			T4	2		T12	48		T13	2
valid_sources[0x29]	7269	1			T4	1		T10	1		T12	45
valid_sources[0x2a]	7074	1			T5	3		T11	17		T12	38
valid_sources[0x2b]	8286	1			T3	1		T4	1		T5	1
valid_sources[0x2c]	7694	1			T4	2		T10	4		T12	42
valid_sources[0x2d]	7606	1			T4	1		T10	2		T6	22
valid_sources[0x2e]	7960	1			T4	1		T6	6		T12	32
valid_sources[0x2f]	7269	1			T4	5		T10	2		T5	2
valid_sources[0x30]	7710	1			T4	2		T10	1		T6	10
valid_sources[0x31]	8974	1			T10	1		T12	38		T13	1
valid_sources[0x32]	7856	1			T4	1		T10	1		T12	35
valid_sources[0x33]	35336	1			T3	1		T4	2		T10	1
valid_sources[0x34]	7572	1			T4	5		T10	4		T6	12
valid_sources[0x35]	9081	1			T4	3		T12	35		T14	136
valid_sources[0x36]	7624	1			T4	1		T10	4		T12	32
valid_sources[0x37]	7926	1			T4	4		T10	4		T12	34
valid_sources[0x38]	9055	1			T4	2		T12	47		T13	2
valid_sources[0x39]	7622	1			T4	3		T10	2		T12	39
valid_sources[0x3a]	8703	1			T10	1		T12	33		T13	2
valid_sources[0x3b]	7652	1			T3	1		T4	1		T10	2
valid_sources[0x3c]	7530	1			T10	1		T12	41		T13	7
valid_sources[0x3d]	7872	1			T4	4		T10	3		T11	17
valid_sources[0x3e]	11880	1			T4	1		T10	2		T12	49
valid_sources[0x3f]	7475	1			T4	4		T10	4		T11	17
valid_sources[0x40]	7158	1			T4	1		T10	2		T12	41
valid_sources[0x41]	7387	1			T4	1		T10	1		T6	3
valid_sources[0x42]	9822	1			T4	1		T10	2		T12	48
valid_sources[0x43]	22360	1			T3	1		T11	17		T12	28
valid_sources[0x44]	12185	1			T4	2		T10	1		T12	58
valid_sources[0x45]	11794	1			T4	2		T6	10		T12	38
valid_sources[0x46]	9980	1			T4	1		T10	2		T5	13
valid_sources[0x47]	7544	1			T12	50		T14	147		T7	1
valid_sources[0x48]	8959	1			T4	4		T10	2		T12	42
valid_sources[0x49]	8509	1			T4	2		T10	2		T12	44
valid_sources[0x4a]	7641	1			T10	2		T12	39		T13	2
valid_sources[0x4b]	8575	1			T4	4		T10	4		T5	5
valid_sources[0x4c]	7224	1			T4	3		T10	1		T6	17
valid_sources[0x4d]	7562	1			T4	3		T12	32		T14	131
valid_sources[0x4e]	7717	1			T4	4		T10	1		T6	1
valid_sources[0x4f]	7636	1			T4	2		T10	1		T12	45
valid_sources[0x50]	8061	1			T3	1		T4	3		T10	2
valid_sources[0x51]	7733	1			T10	4		T12	45		T14	127
valid_sources[0x52]	8263	1			T4	3		T10	3		T6	34
valid_sources[0x53]	7508	1			T4	2		T10	2		T12	40
valid_sources[0x54]	17711	1			T4	3		T12	37		T14	143
valid_sources[0x55]	7938	1			T10	1		T12	37		T14	134
valid_sources[0x56]	9129	1			T10	5		T12	34		T13	3
valid_sources[0x57]	8546	1			T4	1		T10	6		T12	47
valid_sources[0x58]	7741	1			T4	1		T10	1		T6	5
valid_sources[0x59]	7473	1			T4	4		T10	2		T12	43
valid_sources[0x5a]	7439	1			T4	5		T10	4		T12	36
valid_sources[0x5b]	7559	1			T4	1		T10	4		T6	13
valid_sources[0x5c]	9023	1			T4	5		T10	1		T12	39
valid_sources[0x5d]	7571	1			T4	3		T10	1		T12	44
valid_sources[0x5e]	7969	1			T4	1		T10	1		T12	48
valid_sources[0x5f]	7332	1			T4	2		T10	4		T12	47
valid_sources[0x60]	7448	1			T4	4		T10	2		T11	17
valid_sources[0x61]	7523	1			T4	3		T10	4		T6	1
valid_sources[0x62]	7367	1			T4	3		T12	47		T13	2
valid_sources[0x63]	15140	1			T4	2		T12	41		T14	146
valid_sources[0x64]	7398	1			T3	2		T4	3		T10	1
valid_sources[0x65]	7635	1			T4	5		T10	1		T12	38
valid_sources[0x66]	9073	1			T4	5		T10	1		T12	40
valid_sources[0x67]	9386	1			T4	4		T10	2		T12	48
valid_sources[0x68]	7714	1			T10	2		T12	52		T14	136
valid_sources[0x69]	7628	1			T4	5		T5	10		T12	36
valid_sources[0x6a]	7674	1			T4	1		T10	1		T5	1
valid_sources[0x6b]	7598	1			T4	4		T10	7		T12	39
valid_sources[0x6c]	8855	1			T11	17		T12	31		T14	129
valid_sources[0x6d]	8949	1			T4	3		T10	2		T5	1
valid_sources[0x6e]	9037	1			T4	1		T10	1		T12	38
valid_sources[0x6f]	7687	1			T4	2		T10	1		T12	41
valid_sources[0x70]	7189	1			T12	42		T14	115		T15	4
valid_sources[0x71]	7289	1			T4	1		T12	38		T13	1
valid_sources[0x72]	10325	1			T4	5		T10	4		T12	37
valid_sources[0x73]	8004	1			T4	2		T10	1		T5	25
valid_sources[0x74]	8814	1			T4	1		T6	9		T12	33
valid_sources[0x75]	7942	1			T4	4		T11	17		T12	35
valid_sources[0x76]	9376	1			T4	2		T10	4		T6	2
valid_sources[0x77]	35253	1			T4	1		T11	17		T12	44
valid_sources[0x78]	7749	1			T3	1		T4	1		T12	37
valid_sources[0x79]	8648	1			T4	2		T12	41		T13	3
valid_sources[0x7a]	7703	1			T4	3		T11	17		T12	29
valid_sources[0x7b]	7951	1			T4	1		T6	4		T12	28
valid_sources[0x7c]	7763	1			T4	3		T9	579		T10	1
valid_sources[0x7d]	7612	1			T10	4		T12	42		T13	3
valid_sources[0x7e]	7265	1			T4	1		T10	1		T11	17
valid_sources[0x7f]	34157	1			T4	1		T12	53		T14	148
valid_sources[0x80]	7617	1			T3	1		T4	4		T12	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1111722

1

T3

8

T8

1

T4

138

values[0x0]

all_enables

biggest_size

149548

1

T3

4

T8

7

T4

89

values[0x1]

all_enables

biggest_size

148033

1

T3

3

T8

5

T4

78