Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101515321	15587	0	0
claim_transition_if_regwen_rd_A	101515321	1433	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101515321	15587	0	0
T7	63544	0	0	0
T11	141129	5	0	0
T12	459817	0	0	0
T13	5544	0	0	0
T14	113474	0	0	0
T15	28263	0	0	0
T16	21125	0	0	0
T24	40214	0	0	0
T30	35558	0	0	0
T39	0	3	0	0
T63	0	1	0	0
T67	26749	0	0	0
T137	0	1	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	6	0	0
T141	0	17	0	0
T142	0	3	0	0
T143	0	5	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101515321	1433	0	0
T71	86605	0	0	0
T117	0	2	0	0
T123	0	34	0	0
T144	345851	8	0	0
T145	0	16	0	0
T146	0	9	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	34	0	0
T150	0	5	0	0
T151	0	47	0	0
T152	41759	0	0	0
T153	20708	0	0	0
T154	83828	0	0	0
T155	32581	0	0	0
T156	41237	0	0	0
T157	31019	0	0	0
T158	25724	0	0	0
T159	36620	0	0	0